1 #ifndef _DEV_ATH_ATHVAR_H
2 #define _DEV_ATH_ATHVAR_H
5 #include <adf_os_types.h>
6 #include <adf_os_dma.h>
7 #include <adf_os_timer.h>
8 #include <adf_os_lock.h>
10 #include <adf_os_mem.h>
11 #include <adf_os_util.h>
12 #include <adf_os_stdtypes.h>
13 #include <adf_os_defer.h>
14 #include <adf_os_atomic.h>
17 #include <adf_net_types.h>
18 #include <adf_net_wcmd.h>
19 #include <asf_queue.h>
22 #include "ieee80211_var.h"
23 #include "ieee80211_node.h"
24 #include "if_athrate.h"
26 #include <Magpie_api.h>
27 #include <htc_services.h>
32 #define tq_struct adf_os_bh_t
33 #define ATH_INIT_TQUEUE(a,b,c,d) adf_os_init_bh((a),(b),(c),(void *)(d))
34 #define ATH_SCHEDULE_TQUEUE(a,b) adf_os_sched_bh((a),(b))
35 typedef void * TQUEUE_ARG;
37 #define ATH_MIN(a,b) ((a) < (b) ? (a) : (b))
38 #define ATH_AC_2_TXQ(_sc, _ac) (_sc)->sc_ac2q[(_ac)]
39 #define TID_TO_ACTXQ(tidno) sc->sc_ac2q[ TID_TO_WME_AC(tidno)]
41 #define RATE_TABLE_SIZE 32
43 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
45 #define IEEE80211_SEQ_MAX 4096
46 #define SEQNO_FROM_BF_SEQNO(_x) (_x >> IEEE80211_SEQ_SEQ_SHIFT)
47 #define BAW_WITHIN(_start, _bawsz, _seqno) \
48 ((((_seqno) - (_start)) & 4095) < (_bawsz))
50 #define __stats(sc, _x) sc->sc_tx_stats._x ++
51 #define __statsn(sc, _x, _n) sc->sc_tx_stats._x += _n
53 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
57 ATH_TGT_AGGR_BAW_CLOSED,
63 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
64 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
66 #define ATH_DS_BA_SEQ(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_seqnum
67 #define ATH_DS_BA_BITMAP(_ds) (&((struct ath_tx_desc *)_ds)->ds_us.tx.ba_low)
68 #define ATH_DS_TX_BA(_ds) (((struct ath_tx_desc *)_ds)->ds_us.tx.ts_flags & HAL_TX_BA)
69 #define ATH_DS_TX_STATUS(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_status
70 #define ATH_DS_TX_FLAGS(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_flags
71 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
73 #define ATH_AGGR_DELIM_SZ 4
74 #define ATH_AGGR_MINPLEN 256
75 #define ATH_AGGR_ENCRYPTDELIM 10
77 #define ATH_AGGR_GET_NDELIM(_len) \
78 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
79 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
81 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
82 #define OWLMAX_RETRIES 10
83 #define OWLMAX_BAR_RETRIES 10
85 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
88 #define ATH_TXMAXTRY 11
89 #define TARGET_NODE_MAX ATH_NODE_MAX
90 #define TARGET_VAP_MAX ATH_VAP_MAX
92 #define ATH_NODE_TARGET(_n) ((struct ath_node *)(_n))
94 #define MAX_RATE_POWER 63
95 #define ATH_COMP_PROC_NO_COMP_NO_CCS 3
97 #define ATH_BUFSTATUS_DONE 0x00000001 /* hw processing complete, desc processed by hal */
99 #define ATH_AGGR_MIN_QDEPTH 1
101 struct ath_softc_tgt;
105 #define ATH_TXQ(_sc, _qi) (&(_sc)->sc_txq[(_qi)])
106 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
108 #define ATH_NODE_TARGET(_n) ((struct ath_node_target *)(_n))
111 * Built-in implementation for skb free.
113 #define ath_free_rx_skb(_sc,_skb) BUF_Pool_free_buf(_sc->pool_handle, POOL_ID_WLAN_RX_BUF, _skb)
114 #define ath_free_tx_skb(_htc_handle, endpt, _skb) HTC_ReturnBuffers(_htc_handle, endpt, _skb);
116 typedef void (*ath_txq_add_fn_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
117 typedef void (*ath_tx_comp_fn_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
119 struct ath_buf_state {
120 ath_tx_comp_fn_t bfs_comp; /* completion function */
121 ath_txq_add_fn_t bfs_txq_add; /* txq buffer add function */
122 a_uint16_t bfs_pktlen; /* pktlen including crc */
123 a_uint16_t bfs_seqno; /* sequence nuber */
124 a_uint8_t bfs_hdrlen; /* header length */
125 a_uint8_t bfs_keyix; /* key index */
126 a_uint8_t bfs_atype; /* packet type */
127 a_uint8_t bfs_ndelim; /* # delims for padding */
128 a_uint8_t bfs_nframes; /* # frames in aggregate */
129 a_uint8_t bfs_tidno; /* tid of the buffer */
130 a_uint16_t bfs_al; /* length of aggregate */
131 struct ath_rc_series bfs_rcs[4]; /* rate series */
132 struct ath_txq *bfs_txq; /* transmit h/w queue */
133 a_uint8_t bfs_protmode; /* protection mode */
134 a_uint8_t bfs_keytype; /* encr key type */
135 a_uint8_t bfs_retries; /* current retries */
136 a_uint32_t bfs_ismcast : 1; /* is multicast */
137 a_uint32_t bfs_shpream : 1; /* use short preamble */
138 a_uint32_t bfs_isaggr : 1; /* is an aggregate */
139 a_uint32_t bfs_isretried: 1; /* is retried */
142 #define bf_comp bf_state.bfs_comp
143 #define bf_txq_add bf_state.bfs_txq_add
144 #define bf_pktlen bf_state.bfs_pktlen
145 #define bf_hdrlen bf_state.bfs_hdrlen
146 #define bf_keyix bf_state.bfs_keyix
147 #define bf_atype bf_state.bfs_atype
148 #define bf_seqno bf_state.bfs_seqno
149 #define bf_ndelim bf_state.bfs_ndelim
150 #define bf_nframes bf_state.bfs_nframes
151 #define bf_al bf_state.bfs_al
152 #define bf_tidno bf_state.bfs_tidno
153 #define bf_rcs bf_state.bfs_rcs
154 #define bf_txq bf_state.bfs_txq
155 #define bf_protmode bf_state.bfs_protmode
156 #define bf_keytype bf_state.bfs_keytype
157 #define bf_ismcast bf_state.bfs_ismcast
158 #define bf_shpream bf_state.bfs_shpream
159 #define bf_isaggr bf_state.bfs_isaggr
160 #define bf_isretried bf_state.bfs_isretried
161 #define bf_retries bf_state.bfs_retries
163 #define ATH_GENERIC_BUF \
164 asf_tailq_entry(ath_buf) bf_list; \
165 struct ath_buf *bf_next; \
166 struct ath_desc *bf_desc; \
167 struct ath_desc *bf_descarr; \
168 adf_os_dma_map_t bf_dmamap; \
169 adf_os_dmamap_info_t bf_dmamap_info; \
170 struct ieee80211_node_target *bf_node; \
171 adf_nbuf_queue_t bf_skbhead; \
173 struct ath_desc *bf_lastds;
183 struct ath_buf_state bf_state;
185 HTC_ENDPOINT_ID bf_endpt;
193 a_uint32_t bf_status;
194 struct ath_rx_status bf_rx_status;
197 #define ATH_BUF_GET_DESC_PHY_ADDR(bf) bf->bf_desc
198 #define ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, idx) (adf_os_dma_addr_t)(&bf->bf_descarr[idx])
199 #define ATH_BUF_SET_DESC_PHY_ADDR(bf, addr)
200 #define ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, idx, addr)
202 typedef asf_tailq_head(ath_deschead_s, ath_rx_desc) ath_deschead;
203 typedef asf_tailq_head(ath_bufhead_s, ath_buf) ath_bufhead;
205 #define WME_NUM_TID 8
206 #define WME_BA_BMP_SIZE 64
207 #define WME_MAX_BA WME_BA_BMP_SIZE
208 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
209 #define TID_CLEANUP_INPROGRES 0x1
210 #define TID_AGGR_ENABLED 0x2
211 #define TID_REINITIALIZE 0x4
213 #define TAILQ_DEQ(_q, _elm, _field) do { \
214 (_elm) = asf_tailq_first((_q)); \
216 asf_tailq_remove((_q), (_elm), _field); \
220 #define TX_BUF_BITMAP_SIZE 32
221 #define TX_BUF_BITMAP_SET(bitmap, i) bitmap[i>>5] |= ((a_uint32_t)1 << (i&0x1f))
222 #define TX_BUF_BITMAP_CLR(bitmap, i) bitmap[i>>5] &= (~((a_uint32_t)1 << (i&0x1f)))
223 #define TX_BUF_BITMAP_IS_SET(bitmap, i) ((bitmap[i>>5] & ((a_uint32_t)1 << (i&0x1f))) != 0)
225 typedef struct ath_atx_tid {
227 a_uint16_t seq_start;
232 a_uint32_t tx_buf_bitmap[ATH_TID_MAX_BUFS/TX_BUF_BITMAP_SIZE];
233 asf_tailq_entry(ath_atx_tid) tid_qelem;
234 asf_tailq_head(ath_tid_rbq,ath_buf) buf_q;
239 struct ath_node_target *an;
242 struct ath_node_target {
243 struct ieee80211_node_target ni;
244 struct ath_atx_tid tid[WME_NUM_TID];
250 const a_int8_t *dd_name;
251 struct ath_desc *dd_desc;
252 adf_os_dma_map_t dd_desc_dmamap;
253 adf_os_dma_addr_t dd_desc_paddr;
254 adf_os_size_t dd_desc_len;
255 struct ath_buf *dd_bufptr;
260 a_uint32_t *axq_link;
261 asf_tailq_head(,ath_buf) axq_q;
262 a_uint32_t axq_depth;
263 struct ath_buf *axq_linkbuf;
264 asf_tailq_head(,ath_atx_tid) axq_tidq;
267 struct wmi_rc_rate_mask_cmd {
274 struct ath_vap_target {
275 struct ieee80211vap_target av_vap;
276 struct ath_txq av_mcastq;
277 struct ath_buf *av_bcbuf;
278 a_uint32_t av_rate_mask[2]; /* 0 - 2G, 1 - 5G */
279 a_uint8_t av_minrateidx[2]; /* 0 - 2G, 1 - 5G */
283 #define ATH_RXBUF_RESET(bf) \
288 /* Target-side HTC/HIF/WMI related data structure */
289 pool_handle_t pool_handle;
290 hif_handle_t tgt_hif_handle;
291 htc_handle_t tgt_htc_handle;
292 wmi_handle_t tgt_wmi_handle;
294 /* Target HTC Service IDs */
295 HTC_SERVICE htc_beacon_service;
296 HTC_SERVICE htc_cab_service;
297 HTC_SERVICE htc_uapsd_service;
298 HTC_SERVICE htc_mgmt_service;
299 HTC_SERVICE htc_data_VO_service;
300 HTC_SERVICE htc_data_VI_service;
301 HTC_SERVICE htc_data_BE_service;
302 HTC_SERVICE htc_data_BK_service;
305 /* Target HTC Endpoint IDs */
306 HTC_ENDPOINT_ID wmi_command_ep;
307 HTC_ENDPOINT_ID beacon_ep;
308 HTC_ENDPOINT_ID cab_ep;
309 HTC_ENDPOINT_ID uapsd_ep;
310 HTC_ENDPOINT_ID mgmt_ep;
311 HTC_ENDPOINT_ID data_VO_ep;
312 HTC_ENDPOINT_ID data_VI_ep;
313 HTC_ENDPOINT_ID data_BE_ep;
314 HTC_ENDPOINT_ID data_BK_ep;
316 adf_os_handle_t sc_hdl;
317 adf_os_device_t sc_dev;
319 struct ath_ratectrl *sc_rc;
321 a_uint32_t sc_invalid : 1,
322 sc_txstbcsupport : 1,
323 sc_rxstbcsupport : 2,
327 a_int32_t sc_rxbufsize;
328 a_uint16_t sc_cachelsz;
330 struct ath_interrupt_stats sc_int_stats;
331 struct ath_tx_stats sc_tx_stats;
332 struct ath_rx_stats sc_rx_stats;
334 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
335 const HAL_RATE_TABLE *sc_currates;
337 a_uint8_t sc_rixmap[256];
339 enum ieee80211_phymode sc_curmode;
341 a_uint8_t sc_protrix;
345 tq_struct sc_bmisstq;
347 tq_struct sc_fataltq;
349 ath_bufhead sc_rxbuf;
351 ath_deschead sc_rxdesc_idle;
352 ath_deschead sc_rxdesc;
353 struct ath_desc *sc_rxdesc_held;
355 struct ath_buf *sc_txbuf_held;
357 struct ath_descdma sc_rxdma;
358 struct ath_descdma sc_txdma;
359 struct ath_descdma sc_bdma;
361 a_uint32_t *sc_rxlink;
362 ath_bufhead sc_txbuf;
363 a_uint8_t sc_txqsetup;
365 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
366 struct ath_txq *sc_ac2q[WME_NUM_AC];
369 struct ath_hal *sc_ah;
370 struct ath_txq *sc_cabq;
371 struct ath_txq *sc_uapsdq;
372 struct ath_node_target sc_sta[TARGET_NODE_MAX];
373 struct ath_vap_target sc_vap[TARGET_VAP_MAX];
374 struct ieee80211com_target sc_ic;
377 a_uint64_t sc_swba_tsf;
379 WMI_TXSTATUS_EVENT tx_status[2];
382 #define SM(_v, _f) (((_v) << _f##_S) & _f)
383 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
385 #define ATH9K_HTC_TXSTAT_ACK 1<<0
386 #define ATH9K_HTC_TXSTAT_FILT 1<<1
387 #define ATH9K_HTC_TXSTAT_RTC_CTS 1<<2
388 #define ATH9K_HTC_TXSTAT_MCS 1<<3
389 #define ATH9K_HTC_TXSTAT_CW40 1<<4
390 #define ATH9K_HTC_TXSTAT_SGI 1<<5
392 #define ATH9K_HTC_TXSTAT_RATE 0x0f
393 #define ATH9K_HTC_TXSTAT_RATE_S 0
394 #define ATH9K_HTC_TXSTAT_EPID 0xf0
395 #define ATH9K_HTC_TXSTAT_EPID_S 4
397 #define TAILQ_INSERTQ_HEAD(head, tq, field) do { \
398 if ((head)->tqh_first) { \
399 *(tq)->tqh_last = (head)->tqh_first; \
400 (head)->tqh_first->field.tqe_prev = (tq)->tqh_last; \
402 (head)->tqh_last = (tq)->tqh_last; \
404 (head)->tqh_first = (tq)->tqh_first; \
405 (tq)->tqh_first->field.tqe_prev = &(head)->tqh_first; \
408 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
409 asf_tailq_insert_tail( &(_tq)->axq_q, (_elm), _field); \
410 (_tq)->axq_depth++; \
411 (_tq)->axq_linkbuf = (_elm); \
413 #define ATH_TXQ_REMOVE_HEAD(_tq, _elm, _field) do { \
414 asf_tailq_remove(&(_tq)->axq_q, (_elm), _field); \
415 (_tq)->axq_depth--; \
418 struct ieee80211_rate {
419 struct ieee80211_rateset rates;
420 struct ieee80211_rateset htrates;
421 } __attribute__((packed));
423 struct wmi_rc_state_change_cmd {
428 struct ieee80211_rate rs;
429 } __attribute__((packed));
431 struct wmi_rc_rate_update_cmd {
432 a_uint8_t node_index;
436 struct ieee80211_rate rs;
437 } __attribute__((packed));
445 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp);
447 #define ath_hal_getratetable(_ah, _mode) \
448 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
449 #define ath_hal_intrset(_ah, _mask) \
450 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
451 #define ath_hal_intrpend(_ah) \
452 ((*(_ah)->ah_isInterruptPending)((_ah)))
453 #define ath_hal_getisr(_ah, _pmask) \
454 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
455 #define ath_hal_updatetxtriglevel(_ah, _inc) \
456 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
457 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
458 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
459 #define ath_hal_rxprocdescfast(_ah, _ds, _dspa, _dsnext, _rx_stats) \
460 ((*(_ah)->ah_procRxDescFast)((_ah), (_ds), (_dspa), (_dsnext), (_rx_stats)))
461 #define ath_hal_stoptxdma(_ah, _qnum) \
462 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
463 #define ath_hal_aborttxdma(_ah) \
464 ((*(_ah)->ah_abortTxDma)(_ah))
465 #define ath_hal_set11n_txdesc(_ah, _ds, _pktlen, _type, _txpower,\
466 _keyix, _keytype, _flags) \
467 ((*(_ah)->ah_set11nTxDesc)(_ah, _ds, _pktlen, _type, _txpower, _keyix,\
469 #define ath_hal_set11n_ratescenario(_ah, _ds, _durupdate, _rtsctsrate, _rtsctsduration, \
470 _series, _nseries, _flags) \
471 ((*(_ah)->ah_set11nRateScenario)(_ah, _ds, _durupdate, _rtsctsrate, _rtsctsduration,\
472 _series, _nseries, _flags))
473 #define ath_hal_clr11n_aggr(_ah, _ds) \
474 ((*(_ah)->ah_clr11nAggr)(_ah, _ds))
475 #define ath_hal_set11n_burstduration(_ah, _ds, _burstduration) \
476 ((*(_ah)->ah_set11nBurstDuration)(_ah, _ds, _burstduration))
477 #define ath_hal_set11n_virtualmorefrag(_ah, _ds, _vmf) \
478 ((*(_ah)->ah_set11nVirtualMoreFrag)(_ah, _ds, _vmf))
479 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
480 _txr0, _txtr0, _keyix, _ant, _flags, \
481 _rtsrate, _rtsdura, \
482 _compicvlen, _compivlen, _comp) \
483 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
484 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
485 (_flags), (_rtsrate), (_rtsdura), \
486 (_compicvlen), (_compivlen), (_comp)))
487 #define ath_hal_fillkeytxdesc(_ah, _ds, _keytype) \
488 ((*(_ah)->ah_fillKeyTxDesc)((_ah), (_ds), (_keytype)))
489 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
490 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
491 #define ath_hal_txprocdesc(_ah, _ds) \
492 ((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
493 #define ath_hal_putrxbuf(_ah, _bufaddr) \
494 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
495 #define ath_hal_rxena(_ah) \
496 ((*(_ah)->ah_enableReceive)((_ah)))
497 #define ath_hal_stopdmarecv(_ah) \
498 ((*(_ah)->ah_stopDmaReceive)((_ah)))
499 #define ath_hal_stoppcurecv(_ah) \
500 ((*(_ah)->ah_stopPcuReceive)((_ah)))
501 #define ath_hal_htsupported(_ah) \
502 (ath_hal_getcapability(_ah, HAL_CAP_HT, 0, NULL) == HAL_OK)
503 #define ath_hal_rxstbcsupport(_ah, _rxstbc) \
504 (ath_hal_getcapability(_ah, HAL_CAP_RX_STBC, 0, _rxstbc) == HAL_OK)
505 #define ath_hal_txstbcsupport(_ah, _txstbc) \
506 (ath_hal_getcapability(_ah, HAL_CAP_TX_STBC, 0, _txstbc) == HAL_OK)
507 #define ath_hal_getrtsaggrlimit(_ah, _pv) \
508 (ath_hal_getcapability(_ah, HAL_CAP_RTS_AGGR_LIMIT, 0, _pv) == HAL_OK)
509 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
510 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
511 #define ath_hal_txstart(_ah, _q) \
512 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
513 #define ath_hal_setrxfilter(_ah, _filter) \
514 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
515 #define ath_hal_gettsf64(_ah) \
516 ((*(_ah)->ah_getTsf64)((_ah)))
517 #define ath_hal_intrset(_ah, _mask) \
518 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
519 #define ath_hal_getcapability(_ah, _cap, _param, _result) \
520 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
521 #define ath_hal_set11n_aggr_first(_ah, _ds, _aggrlen, _numdelims) \
522 ((*(_ah)->ah_set11nAggrFirst)(_ah, _ds, _aggrlen, _numdelims))
523 #define ath_hal_set11n_aggr_middle(_ah, _ds, _numdelims) \
524 ((*(_ah)->ah_set11nAggrMiddle)(_ah, _ds, _numdelims))
525 #define ath_hal_set11n_aggr_last(_ah, _ds) \
526 ((*(_ah)->ah_set11nAggrLast)(_ah, _ds))
527 #define ath_hal_numtxpending(_ah, _q) \
528 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
530 #endif /* _DEV_ATH_ATHVAR_H */