1 #ifndef _ATH_AR5416_DESC_H_
2 #define _ATH_AR5416_DESC_H_
4 #define ds_ctl8 u.tx.ctl8
5 #define ds_ctl9 u.tx.ctl9
6 #define ds_ctl10 u.tx.ctl10
7 #define ds_ctl11 u.tx.ctl11
9 struct ar5416_desc_20 {
10 a_uint32_t ds_link; /* link pointer */
11 a_uint32_t ds_data; /* data buffer pointer */
12 a_uint32_t ds_ctl0; /* DMA control 0 */
13 a_uint32_t ds_ctl1; /* DMA control 1 */
37 struct { /* rx desc has 2 control words + 9 status words */
51 #define AR5416DESC_20(_ds) ((struct ar5416_desc_20 *)(_ds))
52 #define AR5416DESC_CONST_20(_ds) ((const struct ar5416_desc_20 *)(_ds))
54 #define ds_ctl2 u.tx.ctl2
55 #define ds_ctl3 u.tx.ctl3
56 #define ds_ctl4 u.tx.ctl4
57 #define ds_ctl5 u.tx.ctl5
58 #define ds_ctl6 u.tx.ctl6
59 #define ds_ctl7 u.tx.ctl7
61 #define ds_txstatus0 u.tx.status0
62 #define ds_txstatus1 u.tx.status1
63 #define ds_txstatus2 u.tx.status2
64 #define ds_txstatus3 u.tx.status3
65 #define ds_txstatus4 u.tx.status4
66 #define ds_txstatus5 u.tx.status5
67 #define ds_txstatus6 u.tx.status6
68 #define ds_txstatus7 u.tx.status7
69 #define ds_txstatus8 u.tx.status8
70 #define ds_txstatus9 u.tx.status9
72 #define ds_rxstatus0 u.rx.status0
73 #define ds_rxstatus1 u.rx.status1
74 #define ds_rxstatus2 u.rx.status2
75 #define ds_rxstatus3 u.rx.status3
76 #define ds_rxstatus4 u.rx.status4
77 #define ds_rxstatus5 u.rx.status5
78 #define ds_rxstatus6 u.rx.status6
79 #define ds_rxstatus7 u.rx.status7
80 #define ds_rxstatus8 u.rx.status8
87 #define AR_FrameLen 0x00000fff
88 #define AR_VirtMoreFrag 0x00001000
89 #define AR_TxCtlRsvd00 0x0000e000
91 #define AR_XmitPower 0x003f0000
92 #define AR_XmitPower_S 16
94 #define AR_RTSEnable 0x00400000
95 #define AR_VEOL 0x00800000
96 #define AR_ClrDestMask 0x01000000
97 #define AR_TxCtlRsvd01 0x1e000000
98 #define AR_TxIntrReq 0x20000000
99 #define AR_DestIdxValid 0x40000000
100 #define AR_CTSEnable 0x80000000
103 #define AR_BufLen 0x00000fff
104 #define AR_TxMore 0x00001000
105 #define AR_DestIdx 0x000fe000
106 #define AR_DestIdx_S 13
107 #define AR_FrameType 0x00f00000
108 #define AR_FrameType_S 20
109 #define AR_NoAck 0x01000000
110 #define AR_InsertTS 0x02000000
111 #define AR_CorruptFCS 0x04000000
112 #define AR_ExtOnly 0x08000000
113 #define AR_ExtAndCtl 0x10000000
114 #define AR_MoreAggr 0x20000000
115 #define AR_IsAggr 0x40000000
116 #define AR_MoreRifs 0x80000000
119 #define AR_BurstDur 0x00007fff
120 #define AR_BurstDur_S 0
121 #define AR_DurUpdateEn 0x00008000
122 #define AR_XmitDataTries0 0x000f0000
123 #define AR_XmitDataTries0_S 16
124 #define AR_XmitDataTries1 0x00f00000
125 #define AR_XmitDataTries1_S 20
126 #define AR_XmitDataTries2 0x0f000000
127 #define AR_XmitDataTries2_S 24
128 #define AR_XmitDataTries3 0xf0000000
129 #define AR_XmitDataTries3_S 28
132 #define AR_XmitRate0 0x000000ff
133 #define AR_XmitRate0_S 0
134 #define AR_XmitRate1 0x0000ff00
135 #define AR_XmitRate1_S 8
136 #define AR_XmitRate2 0x00ff0000
137 #define AR_XmitRate2_S 16
138 #define AR_XmitRate3 0xff000000
139 #define AR_XmitRate3_S 24
142 #define AR_PacketDur0 0x00007fff
143 #define AR_PacketDur0_S 0
144 #define AR_RTSCTSQual0 0x00008000
145 #define AR_PacketDur1 0x7fff0000
146 #define AR_PacketDur1_S 16
147 #define AR_RTSCTSQual1 0x80000000
150 #define AR_PacketDur2 0x00007fff
151 #define AR_PacketDur2_S 0
152 #define AR_RTSCTSQual2 0x00008000
153 #define AR_PacketDur3 0x7fff0000
154 #define AR_PacketDur3_S 16
155 #define AR_RTSCTSQual3 0x80000000
158 #define AR_AggrLen 0x0000ffff
159 #define AR_AggrLen_S 0
160 #define AR_TxCtlRsvd60 0x00030000
161 #define AR_PadDelim 0x03fc0000
162 #define AR_PadDelim_S 18
163 #define AR_EncrType 0x1c000000
164 #define AR_EncrType_S 26
165 #define AR_TxCtlRsvd61 0xf0000000
168 #define AR_2040_0 0x00000001
169 #define AR_GI0 0x00000002
170 #define AR_ChainSel0 0x0000001c
171 #define AR_ChainSel0_S 2
172 #define AR_2040_1 0x00000020
173 #define AR_GI1 0x00000040
174 #define AR_ChainSel1 0x00000380
175 #define AR_ChainSel1_S 7
176 #define AR_2040_2 0x00000400
177 #define AR_GI2 0x00000800
178 #define AR_ChainSel2 0x00007000
179 #define AR_ChainSel2_S 12
180 #define AR_2040_3 0x00008000
181 #define AR_GI3 0x00010000
182 #define AR_ChainSel3 0x000e0000
183 #define AR_ChainSel3_S 17
184 #define AR_RTSCTSRate 0x0ff00000
185 #define AR_RTSCTSRate_S 20
186 #define AR_TxCtlRsvd70 0xf0000000
187 #define AR_STBC0 0x10000000
188 #define AR_STBC1 0x20000000
189 #define AR_STBC2 0x40000000
190 #define AR_STBC3 0x80000000
194 #define AR_TxCtlRsvd80 0xffffffff
197 #define AR_TxCtlRsvd90 0x00ffffff
198 #define AR_XmitPower1 0x3f000000
199 #define AR_XmitPower1_S 24
200 #define AR_TxCtlRsvd91 0xc0000000
203 #define AR_TxCtlRsvd100 0x00ffffff
204 #define AR_XmitPower2 0x3f000000
205 #define AR_XmitPower2_S 24
206 #define AR_TxCtlRsvd101 0xc0000000
209 #define AR_TxCtlRsvd110 0x00ffffff
210 #define AR_XmitPower3 0x3f000000
211 #define AR_XmitPower3_S 24
212 #define AR_TxCtlRsvd111 0xc0000000
220 #define AR_TxRSSIAnt00 0x000000ff
221 #define AR_TxRSSIAnt00_S 0
222 #define AR_TxRSSIAnt01 0x0000ff00
223 #define AR_TxRSSIAnt01_S 8
224 #define AR_TxRSSIAnt02 0x00ff0000
225 #define AR_TxRSSIAnt02_S 16
226 #define AR_TxStatusRsvd00 0x3f000000
227 #define AR_TxBaStatus 0x40000000
228 #define AR_TxStatusRsvd01 0x80000000
231 #define AR_FrmXmitOK 0x00000001
232 #define AR_ExcessiveRetries 0x00000002
233 #define AR_FIFOUnderrun 0x00000004
234 #define AR_Filtered 0x00000008
235 #define AR_RTSFailCnt 0x000000f0
236 #define AR_RTSFailCnt_S 4
237 #define AR_DataFailCnt 0x00000f00
238 #define AR_DataFailCnt_S 8
239 #define AR_VirtRetryCnt 0x0000f000
240 #define AR_VirtRetryCnt_S 12
241 #define AR_TxDelimUnderrun 0x00010000
242 #define AR_TxDataUnderrun 0x00020000
243 #define AR_DescCfgErr 0x00040000
244 #define AR_TxTimerExpired 0x00080000
245 #define AR_TxStatusRsvd10 0xfff00000
248 #define AR_SendTimestamp ds_txstatus2
251 #define AR_BaBitmapLow ds_txstatus3
254 #define AR_BaBitmapHigh ds_txstatus4
257 #define AR_TxRSSIAnt10 0x000000ff
258 #define AR_TxRSSIAnt10_S 0
259 #define AR_TxRSSIAnt11 0x0000ff00
260 #define AR_TxRSSIAnt11_S 8
261 #define AR_TxRSSIAnt12 0x00ff0000
262 #define AR_TxRSSIAnt12_S 16
263 #define AR_TxRSSICombined 0xff000000
264 #define AR_TxRSSICombined_S 24
267 #define AR_TxEVM0 ds_txstatus5
270 #define AR_TxEVM1 ds_txstatus6
273 #define AR_TxEVM2 ds_txstatus7
276 #define AR_TxDone 0x00000001
277 #define AR_SeqNum 0x00001ffe
278 #define AR_SeqNum_S 1
279 #define AR_TxStatusRsvd80 0x0001e000
280 #define AR_TxOpExceeded 0x00020000
281 #define AR_TxStatusRsvd81 0x001c0000
282 #define AR_FinalTxIdx 0x00600000
283 #define AR_FinalTxIdx_S 21
284 #define AR_TxStatusRsvd82 0x01800000
285 #define AR_PowerMgmt 0x02000000
286 #define AR_TxStatusRsvd83 0xfc000000
293 #define AR_RxCTLRsvd00 0xffffffff
296 #define AR_BufLen 0x00000fff
297 #define AR_RxCtlRsvd00 0x00001000
298 #define AR_RxIntrReq 0x00002000
299 #define AR_RxCtlRsvd01 0xffffc000
306 #define AR_RxRSSIAnt00 0x000000ff
307 #define AR_RxRSSIAnt00_S 0
308 #define AR_RxRSSIAnt01 0x0000ff00
309 #define AR_RxRSSIAnt01_S 8
310 #define AR_RxRSSIAnt02 0x00ff0000
311 #define AR_RxRSSIAnt02_S 16
312 #define AR_RxRate 0xff000000
313 #define AR_RxRate_S 24
314 #define AR_RxStatusRsvd00 0xff000000
317 #define AR_DataLen 0x00000fff
318 #define AR_RxMore 0x00001000
319 #define AR_NumDelim 0x003fc000
320 #define AR_NumDelim_S 14
321 #define AR_RxStatusRsvd10 0xff800000
324 #define AR_RcvTimestamp ds_rxstatus2
327 #define AR_GI 0x00000001
328 #define AR_2040 0x00000002
329 #define AR_Parallel40 0x00000004
330 #define AR_Parallel40_S 2
331 #define AR_RxStatusRsvd30 0x000000f8
332 #define AR_RxAntenna 0xffffff00
333 #define AR_RxAntenna_S 8
336 #define AR_RxRSSIAnt10 0x000000ff
337 #define AR_RxRSSIAnt10_S 0
338 #define AR_RxRSSIAnt11 0x0000ff00
339 #define AR_RxRSSIAnt11_S 8
340 #define AR_RxRSSIAnt12 0x00ff0000
341 #define AR_RxRSSIAnt12_S 16
342 #define AR_RxRSSICombined 0xff000000
343 #define AR_RxRSSICombined_S 24
346 #define AR_RxEVM0 ds_rxstatus4
349 #define AR_RxEVM1 ds_rxstatus5
352 #define AR_RxEVM2 ds_rxstatus6
355 #define AR_RxDone 0x00000001
356 #define AR_RxFrameOK 0x00000002
357 #define AR_CRCErr 0x00000004
358 #define AR_DecryptCRCErr 0x00000008
359 #define AR_PHYErr 0x00000010
360 #define AR_MichaelErr 0x00000020
361 #define AR_PreDelimCRCErr 0x00000040
362 #define AR_RxStatusRsvd70 0x00000080
363 #define AR_RxKeyIdxValid 0x00000100
364 #define AR_KeyIdx 0x0000fe00
365 #define AR_KeyIdx_S 9
366 #define AR_PHYErrCode 0x0000ff00
367 #define AR_PHYErrCode_S 8
368 #define AR_RxMoreAggr 0x00010000
369 #define AR_RxAggr 0x00020000
370 #define AR_PostDelimCRCErr 0x00040000
371 #define AR_RxStatusRsvd71 0x3ff80000
372 #define AR_DecryptBusyErr 0x40000000
373 #define AR_KeyMiss 0x80000000
375 #define RXSTATUS_RATE(ah, ads) (MS(ads->ds_rxstatus0, AR_RxRate))
376 #define VALID_TX_RATES \
377 ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)| \
378 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)| \
379 (1<<0x1d)|(1<<0x18)|(1<<0x1c))
380 #define isValidTxRate(_r) ((1<<(_r)) & VALID_TX_RATES)
382 #define set11nTries(_series, _index) \
383 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
385 #define set11nRate(_series, _index) \
386 (SM((_series)[_index].Rate, AR_XmitRate##_index))
388 #define set11nPktDurRTSCTS(_series, _index) \
389 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) |\
390 ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ?\
391 AR_RTSCTSQual##_index : 0))
393 #define set11nRateFlags(_series, _index) \
394 ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \
395 |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_GI##_index : 0) \
396 |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_STBC##_index : 0) \
397 |SM((_series)[_index].ChSel, AR_ChainSel##_index)
399 #define set11nTxPower(_index, _txpower) \
400 SM(_txpower, AR_XmitPower##_index)
402 extern HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *,
403 HAL_BOOL IncTrigLevel);
404 extern a_uint32_t ar5416GetTxDP(struct ath_hal *ah, a_uint32_t q);
405 extern HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp);
406 extern HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q);
407 extern a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q);
408 extern HAL_BOOL ar5416StopTxDma(struct ath_hal *ah, a_uint32_t q);
409 extern HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah);
410 extern void ar5416GetTxIntrQueue(struct ath_hal *ah, a_uint32_t *);
411 extern HAL_BOOL ar5416SetGlobalTxTimeout(struct ath_hal *, a_uint32_t);
412 extern a_uint32_t ar5416GetGlobalTxTimeout(struct ath_hal *);
413 extern HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah);
414 extern a_uint32_t ar5416GetRxDP(struct ath_hal *ath);
415 extern void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp);
416 extern void ar5416EnableReceive(struct ath_hal *ah);
417 extern HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah);
418 extern void ar5416StartPcuReceive(struct ath_hal *ah);
419 extern void ar5416StopPcuReceive(struct ath_hal *ah);
420 extern void ar5416AbortPcuReceive(struct ath_hal *ah);
421 extern void ar5416SetMulticastFilter(struct ath_hal *ah,
422 a_uint32_t filter0, a_uint32_t filter1);
423 extern HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *, a_uint32_t ix);
424 extern HAL_BOOL ar5416SetMulticastFilterIndex(struct ath_hal *, a_uint32_t ix);
425 extern a_uint32_t ar5416GetRxFilter(struct ath_hal *ah);
426 extern void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits);
427 extern HAL_BOOL ar5416UpdateCTSForBursting_20(struct ath_hal *, struct ath_desc *,
428 struct ath_desc *,struct ath_desc *, struct ath_desc *,
429 a_uint32_t, a_uint32_t);
430 extern HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_desc *ds,
431 a_uint32_t pktLen, a_uint32_t hdrLen, HAL_PKT_TYPE type, a_uint32_t txPower,
432 a_uint32_t txRate0, a_uint32_t txTries0,
433 a_uint32_t keyIx, a_uint32_t antMode, a_uint32_t flags,
434 a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration,
435 a_uint32_t compicvLen, a_uint32_t compivLen, a_uint32_t comp);
436 extern HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_desc *ds,
437 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
438 const struct ath_desc *ds0);
439 extern HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_desc *,HAL_KEY_TYPE);
440 extern HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_desc *);
442 extern void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds);
443 extern void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_desc *ds,
444 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
445 a_uint32_t keyIx, HAL_KEY_TYPE keyType, a_uint32_t flags);
446 extern void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_desc *ds,
447 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration, HAL_11N_RATE_SERIES series[],
448 a_uint32_t nseries, a_uint32_t flags);
449 extern void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_desc *ds,
450 a_uint32_t aggrLen, a_uint32_t numDelims);
451 extern void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_desc *ds,
452 a_uint32_t numDelims);
453 extern void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_desc *ds);
454 extern void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_desc *ds);
455 extern void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_desc *ds,
456 a_uint32_t burstDuration);
457 extern void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_desc *ds,
459 extern HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *,
460 struct ath_desc *, a_uint32_t size, a_uint32_t flags);
461 extern HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah,
462 struct ath_desc *, a_uint32_t,
464 struct ath_rx_status *);