1 /*************************************************************************/
2 /* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */
4 /* Module Name : rom_cfg.h */
7 /* This file contains definition of platform and sysmte config . */
12 /*************************************************************************/
17 /************************** FPGA version **************************/
18 #define MAGPIE_FPGA_RAM_256K 0
20 /************************** SYSTEM WIDE ***************************/
22 * D : Daily build (Development)
23 * R : Official Release
25 #define ATH_VER_RELEASE_CODE "D"
26 #define ATH_VER_PLATFORM_NUMBER "0"
27 #define ATH_VER_MAJOR_NUMBER "0"
28 #define ATH_VER_MINOR_NUMBER "0"
29 #define ATH_VER_BUILD_NUMBER "3"
31 #define ATH_VER_DATES __DATE__" "__TIME__
33 #define ATH_VERSION_STR "["ATH_VER_RELEASE_CODE "." \
34 ATH_VER_PLATFORM_NUMBER "." \
35 ATH_VER_MAJOR_NUMBER "." \
36 ATH_VER_MINOR_NUMBER "." \
37 ATH_VER_BUILD_NUMBER "] " \
40 /* ROM Code Version (16 bit)
41 * Bit 15 : 0 means ASIC, 1 means FPGA
42 * Bit 14 : 0 means ROM, 1 means FLASH
43 * Bit 13-8 : Major Version Number
44 * Bit 7-0 : Minor Version Number
47 #define ROM_PLATFORM (1)
49 #define ROM_PLATFORM (0)
52 #if defined(SFLASH_BOOT)
58 /* Define ROM Code Version Number here */
59 #define ROM_MAJOR_VER_NUM (1)
60 #define ROM_MINOR_VER_NUM (8)
62 #define BOOTROM_VER ( (ROM_PLATFORM<<15) | (ROM_TYPE<<14) | (ROM_MAJOR_VER_NUM<<8) | ROM_MINOR_VER_NUM )
66 #define SYSTEM_FREQ 10 // For FPGA, it is 10 MHz; For SoC, it is 40 MHz during ROM booting, and then change to 117 MHz during firmware execution
68 #define SYSTEM_FREQ 40 // For FPGA, it is 10 MHz; For SoC, it is 40 MHz during ROM booting, and then change to 117 MHz during firmware execution
71 #define SYSTEM_CLK SYSTEM_FREQ*1000*1000 //40mhz
73 #define ONE_MSEC (SYSTEM_FREQ*1000)
75 /////////////////////////////////////////////////////////////////
77 * Supported reference clock speeds.
79 * Note: MAC HAL code has multiple tables indexed by these values,
80 * so do not rearrange them. Add any new refclk values at the end.
83 SYS_CFG_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */
84 SYS_CFG_REFCLK_10_MHZ = 0,
85 SYS_CFG_REFCLK_20_MHZ = 1,
86 SYS_CFG_REFCLK_40_MHZ = 2,
89 /////////////////////////////////////////////////////////////////
92 /////////////////////////////////////////////////////////////////
95 #define SYSTEM_MODULE_MEM 1
97 #define SYSTEM_MODULE_MISC 1
99 #define SYSTEM_MODULE_USB 1
101 #if SYSTEM_MODULE_USB
102 #define SYSTEM_MODULE_HP_EP1 1
103 #define SYSTEM_MODULE_HP_EP5 1
104 #define SYSTEM_MODULE_HP_EP6 1
107 #define SYSTEM_MODULE_INTR 1
109 #define SYSTEM_MODULE_CLOCK 1
111 #define SYSTEM_MODULE_DESC 0
113 #define SYSTEM_MODULE_ALLOCRAM 1
115 #define SYSTEM_MODULE_UART 1 //uart module to dump the dbg message
117 #define SYSTEM_MODULE_TIMER 1 // a virtual timer, before we don't have the real timer
119 #define SYSTEM_MODULE_WDT 1 // a watchdog timer
121 #define SYSTEM_MODULE_EEPROM 1 // a eeprom interface (pcie_rc's eeprom not apb eeprom)
123 #define SYSTEM_MODULE_SFLASH 1 // a serial flash interface
125 #if SYSTEM_MODULE_UART
126 #define SYSTEM_MODULE_PRINT 1 // dependency on UART module
127 #define MOVE_PRINT_TO_RAM 1 // dependency on PRINT & UART module
128 #define SYSTEM_MODULE_DBG 1 // dependency on PRINT & UART module
129 #define MOVE_DBG_TO_RAM 1 // dependency on PRINT & UART module
132 #define SYSTEM_MODULE_ROM_PATCH 1 // patch install module
134 #define SYSTEM_MODULE_PCI 0
136 #define SYSTEM_MODULE_GMAC 0
138 #define SYSTEM_MODULE_TESTING 0 // backdoor test module
140 #if SYSTEM_MODULE_TESTING
141 #define SYSTEM_MODULE_MEMORY_TEST 0
142 #define SYSTEM_MODULE_DHRYSTONE_TEST 0
144 #define SYSTEM_MODULE_SYS_MONITOR 0
145 #define SYSTEM_MODULE_IDLE_TASK 0
147 #endif /* SYSTEM_MODULE_TESTING */
149 /****************************** UART ******************************/
150 #define UART_INPUT_CLK SYSTEM_CLK
151 #define UART_DEFAULT_BAUD 19200
152 #define UART_RETRY_COUNT 10000
154 /****************************** USB *******************************/
156 /* Firmware Loopback */
157 #define ZM_FM_LOOPBACK 0
158 #define ZM_SELF_TEST_MODE 1 // USB-IF Eye Pattern Test
160 #define ENABLE_SWAP_DATA_MODE 1 // byte swap function
161 #define ENABLE_SW_SWAP_DATA_MODE 1
163 #define ENABLE_STREAM_MODE 0 // stream mode
165 #define USB_STREAM_MODE_AGG_CNT 0 // 2 packets, 2: 3packets, 3: 4packets etc...
166 #define USB_STREAM_MODE_TIMEOUT_CTRL 0x0 // the unit is 32 USB (30Mhz) clock cycles
167 #define USB_STREAM_MODE_HOST_BUF_SZ (BIT4) // define the host dma buffer size (bit5,bit4)- 4096(0,0) 8192 (0,1) 16384(1,0) 32768(1,1) bytes
169 /************************* MEMORY DEFS ***************************/
171 #if defined(PROJECT_MAGPIE)
172 #include "magpie_mem.h"
173 #elif defined(PROJECT_K2)
178 // the end of 16 bytes are used to record some debug state and watchdog event and counter
179 #define WATCH_DOG_MAGIC_PATTERN_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x4) // 0x53fffc,magic pattern address
180 #define WATCH_DOG_RESET_COUNTER_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x8) // 0x53fff8,record the reset counter
181 #define DEBUG_SYSTEM_STATE_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0xc) // 0x53fff4,record the state of system
182 #define CURRENT_PROGRAM_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x10) // 0x53fff0,reserved
184 #define WATCH_DOG_MAGIC_PATTERN (*((volatile u32_t*)(WATCH_DOG_MAGIC_PATTERN_ADDR)))
185 #define WATCH_DOG_RESET_COUNTER (*((volatile u32_t*)(WATCH_DOG_RESET_COUNTER_ADDR)))
186 #define DEBUG_SYSTEM_STATE (*((volatile u32_t*)(DEBUG_SYSTEM_STATE_ADDR)))
187 #define CURRENT_PROGRAM (*((volatile u32_t*)(CURRENT_PROGRAM_ADDR)))
189 #define WDT_MAGIC_PATTERN 0x5F574454 //_WDT
190 #define SUS_MAGIC_PATTERN 0x5F535553 //_SUS
192 /****************************** WATCH DOG *******************************/
193 #define WDT_DEFAULT_TIMEOUT_VALUE 3*ONE_MSEC*1000 // Initial value is 3 seconds, firmware changes it to 65 milliseconds
195 #endif /* _ROM_CFG_H_ */