ath9k_htc/sboot/magpie_1_1/sboot/hif/usb/src/usb_fifo.c

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35 #include "usb_defs.h"
  36 #include "usb_type.h"
  37 #include "usb_pre.h"
  38 #include "usb_extr.h"
  39 #include "usb_std.h"
  40 #include "dt_defs.h"
  41 #include "sys_cfg.h"
  42
  43 #include "athos_api.h"
  44
  45 #if SYSTEM_MODULE_USB
  46
  47 extern uint16_t       u8UsbConfigValue;
  48 extern uint16_t       u8UsbInterfaceValue;
  49 extern uint16_t       u8UsbInterfaceAlternateSetting;
  50
  51 #if 1
  52
  53 void mUsbEPMap(uint8_t EPn, uint8_t MAP)
  54 {
  55     //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x30+(EPn-1));
  56     //*reg = MAP;
  57     uint8_t reg = (0x30+(EPn-1));
  58
  59 //    A_PRINTF("=>mUsbEPMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg));
  60     USB_BYTE_REG_WRITE(reg, MAP );
  61
  62 //    A_PRINTF("<=mUsbEPMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg));
  63
  64     //zfUartSendStr("mUsbEPMap\r\n");
  65     //zfUartSendStrAndHex("EPn=", EPn);
  66     //zfUartSendStrAndHex("MAP=", MAP);
  67 }
  68
  69 void mUsbFIFOMap(uint8_t FIFOn, uint8_t MAP)
  70 {
  71     //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x80+FIFOn);
  72     //*reg = MAP;
  73
  74     uint8_t reg = (0x80+FIFOn);
  75
  76     reg = reg;
  77
  78 //    A_PRINTF("=>mUsbFIFOMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg));
  79     USB_BYTE_REG_WRITE( reg, MAP );
  80
  81 //    A_PRINTF("<=mUsbFIFOMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg));
  82     //zfUartSendStr("mUsbFIFOMap\r\n");
  83     //zfUartSendStrAndHex("FIFOn=", FIFOn);
  84     //zfUartSendStrAndHex("MAP=", MAP);
  85 }
  86
  87 void mUsbFIFOConfig(uint8_t FIFOn, uint8_t cfg)
  88 {
  89     //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x90+FIFOn);
  90     //*reg = cfg;
  91     uint8_t reg = (0x90+FIFOn);
  92
  93 //    A_PRINTF("=>mUsbFIFOConfig: write: %02x to %02x (0x%08x)\n\r", cfg , reg, USB_WORD_REG_READ(reg));
  94     USB_BYTE_REG_WRITE( reg, cfg );
  95
  96 //    A_PRINTF("<=mUsbFIFOConfig: write: %02x to %02x (0x%08x)\n\r", cfg , reg, USB_WORD_REG_READ(reg));
  97     //zfUartSendStr((uint8_t *)"mUsbFIFOConfig\r\n");
  98     //zfUartSendStrAndHex((uint8_t *)"FIFOn=", FIFOn);
  99     //zfUartSendStrAndHex((uint8_t *)"cfg=", cfg);
 100 }
 101
 102 void mUsbEPMxPtSzHigh(uint8_t EPn, uint8_t dir, uint16_t size)
 103 {
 104     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+EPn << 1));
 105     //*reg = (size >> 8) & 0xf;
 106     uint8_t reg = (ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+(EPn << 1)));
 107
 108 //    A_PRINTF("=>mUsbEPMxPtSzHigh: write: %02x to %02x (0x%08x)\n\r", ((size >> 8) & 0xff), reg, USB_WORD_REG_READ(reg));
 109     USB_BYTE_REG_WRITE(reg, ((size >> 8) & 0xff));
 110
 111 //    A_PRINTF("<=mUsbEPMxPtSzHigh: write: %02x to %02x (0x%08x)\n\r", ((size >> 8) & 0xff), reg, USB_WORD_REG_READ(reg));
 112     //USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+EPn << 1)), ((size >> 8) & 0xf));
 113 }
 114
 115 void mUsbEPMxPtSzLow(uint8_t EPn, uint8_t dir, uint16_t size)
 116 {
 117     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_LOW_OFFSET+(((dir) * 0x20)+EPn << 1));
 118     //*reg = (size & 0xff);
 119
 120     uint8_t reg = (ZM_EP_IN_MAX_SIZE_LOW_OFFSET+(((dir) * 0x20)+(EPn << 1)));
 121 //    A_PRINTF("=>mUsbEPMxPtSzLow: write: %02x to %02x (0x%08x)\n\r", (size & 0xff), reg, USB_WORD_REG_READ(reg));
 122     USB_BYTE_REG_WRITE(reg, (size & 0xff));
 123
 124 //    A_PRINTF("<=mUsbEPMxPtSzLow: write: %02x to %02x (0x%08x)\n\r", (size & 0xff), reg, USB_WORD_REG_READ(reg));
 125 }
 126
 127 void mUsbEPinHighBandSet(uint8_t EPn, uint8_t dir, uint16_t size)
 128 {
 129 #if 1
 130     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1));
 131
 132     //*reg &= ~(BIT6 | BIT5);
 133     //*reg |= (((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir));
 134
 135     uint8_t reg = (ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1));
 136 //    uint8_t reg2 = (((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir));
 137     uint8_t reg2 = (((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir));
 138
 139 //    A_PRINTF("=>mUsbEPinHighBandSet(%d)(size:%d)(dir:%d): write: %02x to %02x (0x%08x)\n\r", EPn, size, dir, (USB_BYTE_REG_READ(reg)|reg2), reg, USB_WORD_REG_READ(reg));
 140     USB_BYTE_REG_WRITE(reg, (USB_BYTE_REG_READ(reg)&~(BIT6 | BIT5)));
 141     USB_BYTE_REG_WRITE(reg,  (USB_BYTE_REG_READ(reg)|reg2));
 142
 143 //    A_PRINTF("=>mUsbEPinHighBandSet(%d)(size:%d)(dir:%d): write: %02x to %02x (0x%08x)\n\r", EPn, size, dir, (USB_BYTE_REG_READ(reg)|reg2), reg, USB_WORD_REG_READ(reg));
 144 #endif
 145 }
 146
 147 #else
 148
 149 #define mUsbEPMap( EPn, MAP)    USB_BYTE_REG_WRITE( (0x30+(EPn-1)), MAP )
 150
 151 #define mUsbFIFOMap( FIFOn, MAP)    USB_BYTE_REG_WRITE( (0x80+FIFOn), MAP )
 152
 153 #define mUsbFIFOConfig(FIFOn, cfg)    USB_BYTE_REG_WRITE( (0x90+FIFOn), cfg )
 154
 155 #define mUsbEPMxPtSzHigh(EPn, dir, size)  USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+EPn << 1)), ((size >> 8) & 0xf))
 156
 157 #define mUsbEPMxPtSzLow(EPn, dir, size)   USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_LOW_OFFSET+(((dir) * 0x20)+EPn << 1)), (size & 0xff))
 158
 159 #define mUsbEPinHighBandSet( EPn, dir, size)                                                \
 160 {                                                                                                                       \
 161     USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)),  \
 162                     (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1))&(~(BIT6 | BIT5)))));       \
 163     USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)),  \
 164                     (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)|((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir)))));   \
 165 }
 166
 167 #endif
 168
 169 /////////////////////////////////////////////////////
 170 //      vUsbFIFO_EPxCfg_HS(void)
 171 //      Description:
 172 //          1. Configure the FIFO and EPx map
 173 //      input: none
 174 //      output: none
 175 /////////////////////////////////////////////////////
 176 void vUsbFIFO_EPxCfg_HS(void)
 177 {
 178
 179     int i;
 180
 181     switch (u8UsbConfigValue)
 182     {
 183         #if (HS_CONFIGURATION_NUMBER >= 1)
 184         // Configuration 0X01
 185         case 0X01:
 186             switch (u8UsbInterfaceValue)
 187             {
 188                 #if (HS_C1_INTERFACE_NUMBER >= 1)
 189                 // Interface 0
 190                 case 0:
 191                     switch (u8UsbInterfaceAlternateSetting)
 192                     {
 193                         #if (HS_C1_I0_ALT_NUMBER >= 1)
 194                         // AlternateSetting 0
 195                         case 0:
 196                             #if (HS_C1_I0_A0_EP_NUMBER >= 1)
 197                             //EP0X01
 198                             mUsbEPMap(EP1, HS_C1_I0_A0_EP1_MAP);
 199                             mUsbFIFOMap(HS_C1_I0_A0_EP1_FIFO_START, HS_C1_I0_A0_EP1_FIFO_MAP);
 200
 201                             mUsbFIFOMap(HS_C1_I0_A0_EP1_FIFO_START+1, HS_C1_I0_A0_EP1_FIFO_MAP);    //ryan
 202
 203                             mUsbFIFOConfig(HS_C1_I0_A0_EP1_FIFO_START, HS_C1_I0_A0_EP1_FIFO_CONFIG);
 204
 205                             for(i = HS_C1_I0_A0_EP1_FIFO_START + 1 ;
 206                                 i < HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO ;
 207                                 i ++)
 208                             {
 209                                 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP1_FIFO_CONFIG & (~BIT7)) );
 210                             }
 211
 212                             mUsbEPMxPtSzHigh(EP1, HS_C1_I0_A0_EP1_DIRECTION, (HS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff) );
 213                             mUsbEPMxPtSzLow(EP1, HS_C1_I0_A0_EP1_DIRECTION, (HS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff) );
 214                             mUsbEPinHighBandSet(EP1 , HS_C1_I0_A0_EP1_DIRECTION , HS_C1_I0_A0_EP1_MAX_PACKET);
 215
 216                             #endif
 217                             #if (HS_C1_I0_A0_EP_NUMBER >= 2)
 218                             //EP0X02
 219                             mUsbEPMap(EP2, HS_C1_I0_A0_EP2_MAP);
 220                             mUsbFIFOMap(HS_C1_I0_A0_EP2_FIFO_START, HS_C1_I0_A0_EP2_FIFO_MAP);
 221
 222                             mUsbFIFOMap(HS_C1_I0_A0_EP2_FIFO_START+1, HS_C1_I0_A0_EP2_FIFO_MAP);//ryan
 223
 224                             mUsbFIFOConfig(HS_C1_I0_A0_EP2_FIFO_START, HS_C1_I0_A0_EP2_FIFO_CONFIG);
 225
 226                             for(i = HS_C1_I0_A0_EP2_FIFO_START + 1 ;
 227                                 i < HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO ;
 228                                 i ++)
 229                             {
 230                                 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP2_FIFO_CONFIG & (~BIT7)) );
 231                             }
 232
 233                             mUsbEPMxPtSzHigh(EP2, HS_C1_I0_A0_EP2_DIRECTION, (HS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff) );
 234                             mUsbEPMxPtSzLow(EP2, HS_C1_I0_A0_EP2_DIRECTION, (HS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff) );
 235                             mUsbEPinHighBandSet(EP2 , HS_C1_I0_A0_EP2_DIRECTION , HS_C1_I0_A0_EP2_MAX_PACKET);
 236
 237                             #endif
 238                             #if (HS_C1_I0_A0_EP_NUMBER >= 3)
 239                             //EP0X03
 240                             mUsbEPMap(EP3, HS_C1_I0_A0_EP3_MAP);
 241                             mUsbFIFOMap(HS_C1_I0_A0_EP3_FIFO_START, HS_C1_I0_A0_EP3_FIFO_MAP);
 242                             mUsbFIFOConfig(HS_C1_I0_A0_EP3_FIFO_START, HS_C1_I0_A0_EP3_FIFO_CONFIG);
 243
 244                             for(i = HS_C1_I0_A0_EP3_FIFO_START + 1 ;
 245                                 i < HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO ;
 246                                 i ++)
 247                             {
 248                                 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP3_FIFO_CONFIG & (~BIT7)) );
 249                             }
 250
 251                             mUsbEPMxPtSzHigh(EP3, HS_C1_I0_A0_EP3_DIRECTION, (HS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff) );
 252                             mUsbEPMxPtSzLow(EP3, HS_C1_I0_A0_EP3_DIRECTION, (HS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff) );
 253                             mUsbEPinHighBandSet(EP3 , HS_C1_I0_A0_EP3_DIRECTION , HS_C1_I0_A0_EP3_MAX_PACKET);
 254
 255                             #endif
 256                             #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
 257                             //EP0X04
 258                             mUsbEPMap(EP4, HS_C1_I0_A0_EP4_MAP);
 259                             mUsbFIFOMap(HS_C1_I0_A0_EP4_FIFO_START, HS_C1_I0_A0_EP4_FIFO_MAP);
 260                             mUsbFIFOConfig(HS_C1_I0_A0_EP4_FIFO_START, HS_C1_I0_A0_EP4_FIFO_CONFIG);
 261
 262                             for(i = HS_C1_I0_A0_EP4_FIFO_START + 1 ;
 263                                 i < HS_C1_I0_A0_EP4_FIFO_START + HS_C1_I0_A0_EP4_FIFO_NO ;
 264                                 i ++)
 265                             {
 266                                 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP4_FIFO_CONFIG & (~BIT7)) );
 267                             }
 268
 269                             mUsbEPMxPtSzHigh(EP4, HS_C1_I0_A0_EP4_DIRECTION, (HS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff) );
 270                             mUsbEPMxPtSzLow(EP4, HS_C1_I0_A0_EP4_DIRECTION, (HS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff) );
 271                             mUsbEPinHighBandSet(EP4 , HS_C1_I0_A0_EP4_DIRECTION , HS_C1_I0_A0_EP4_MAX_PACKET);
 272
 273                             #endif
 274 //////////////////////////////////////////////////////////////
 275 #if SYSTEM_MODULE_HP_EP5
 276                             #if (HS_C1_I0_A0_EP_NUMBER >= 5)
 277                             //EP0X05
 278                             mUsbEPMap(EP5, HS_C1_I0_A0_EP5_MAP);
 279                             mUsbFIFOMap(HS_C1_I0_A0_EP5_FIFO_START, HS_C1_I0_A0_EP5_FIFO_MAP);
 280
 281                             mUsbFIFOMap(HS_C1_I0_A0_EP5_FIFO_START+1, HS_C1_I0_A0_EP5_FIFO_MAP);        //ryan
 282
 283                             mUsbFIFOConfig(HS_C1_I0_A0_EP5_FIFO_START, HS_C1_I0_A0_EP5_FIFO_CONFIG);
 284
 285                             for(i = HS_C1_I0_A0_EP5_FIFO_START + 1 ;
 286                                 i < HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO ;
 287                                 i ++)
 288                             {
 289                                 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP5_FIFO_CONFIG & (~BIT7)) );
 290                             }
 291
 292                             mUsbEPMxPtSzHigh(EP5, HS_C1_I0_A0_EP5_DIRECTION, (HS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff) );
 293                             mUsbEPMxPtSzLow(EP5, HS_C1_I0_A0_EP5_DIRECTION, (HS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff) );
 294                             mUsbEPinHighBandSet(EP5 , HS_C1_I0_A0_EP5_DIRECTION , HS_C1_I0_A0_EP5_MAX_PACKET);
 295                             #endif
 296 #endif //SYSTEM_MODULE_HP_EP5
 297
 298 //////////////////////////////////////////////////////////////
 299 #if SYSTEM_MODULE_HP_EP6
 300                             #if (HS_C1_I0_A0_EP_NUMBER >= 6)
 301                             //EP0X06
 302                             mUsbEPMap(EP6, HS_C1_I0_A0_EP6_MAP);
 303                             mUsbFIFOMap(HS_C1_I0_A0_EP6_FIFO_START, HS_C1_I0_A0_EP6_FIFO_MAP);
 304
 305                             mUsbFIFOMap(HS_C1_I0_A0_EP6_FIFO_START+1, HS_C1_I0_A0_EP6_FIFO_MAP);        //ryan
 306
 307                             mUsbFIFOConfig(HS_C1_I0_A0_EP6_FIFO_START, HS_C1_I0_A0_EP6_FIFO_CONFIG);
 308
 309                             for(i = HS_C1_I0_A0_EP6_FIFO_START + 1 ;
 310                                 i < HS_C1_I0_A0_EP6_FIFO_START + HS_C1_I0_A0_EP6_FIFO_NO ;
 311                                 i ++)
 312                             {
 313                                 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP6_FIFO_CONFIG & (~BIT7)) );
 314                             }
 315
 316                             mUsbEPMxPtSzHigh(EP6, HS_C1_I0_A0_EP6_DIRECTION, (HS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff) );
 317                             mUsbEPMxPtSzLow(EP6, HS_C1_I0_A0_EP6_DIRECTION, (HS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff) );
 318                             mUsbEPinHighBandSet(EP6 , HS_C1_I0_A0_EP6_DIRECTION , HS_C1_I0_A0_EP6_MAX_PACKET);
 319                             #endif
 320                             break;
 321 #endif //SYSTEM_MODULE_HP_EP6
 322
 323                         #endif
 324                         default:
 325                             break;
 326                     }
 327                     break;
 328                 #endif
 329                 default:
 330                     break;
 331             }
 332             break;
 333         #endif
 334         default:
 335             break;
 336     }
 337     //mCHECK_STACK();
 338
 339 }
 340
 341 void vUsbFIFO_EPxCfg_FS(void)
 342 {
 343
 344 int i;
 345
 346     switch (u8UsbConfigValue)
 347     {
 348         #if (FS_CONFIGURATION_NUMBER >= 1)
 349         // Configuration 0X01
 350         case 0X01:
 351             switch (u8UsbInterfaceValue)
 352             {
 353                 #if (FS_C1_INTERFACE_NUMBER >= 1)
 354                 // Interface 0
 355                 case 0:
 356                     switch (u8UsbInterfaceAlternateSetting)
 357                     {
 358                         #if (FS_C1_I0_ALT_NUMBER >= 1)
 359                         // AlternateSetting 0
 360                         case 0:
 361                             #if (FS_C1_I0_A0_EP_NUMBER >= 1)
 362                             //EP0X01
 363                             mUsbEPMap(EP1, FS_C1_I0_A0_EP1_MAP);
 364                             mUsbFIFOMap(FS_C1_I0_A0_EP1_FIFO_START, FS_C1_I0_A0_EP1_FIFO_MAP);
 365                             mUsbFIFOConfig(FS_C1_I0_A0_EP1_FIFO_START, FS_C1_I0_A0_EP1_FIFO_CONFIG);
 366
 367                             for(i = FS_C1_I0_A0_EP1_FIFO_START + 1 ;
 368                                 i < FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO ;
 369                                 i ++)
 370                             {
 371                                 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP1_FIFO_CONFIG & (~BIT7)) );
 372                             }
 373
 374                             mUsbEPMxPtSzHigh(EP1, FS_C1_I0_A0_EP1_DIRECTION, (FS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff));
 375                             mUsbEPMxPtSzLow(EP1, FS_C1_I0_A0_EP1_DIRECTION, (FS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff));
 376                         //``.JWEI 2003/04/29
 377                             mUsbEPinHighBandSet(EP1 , FS_C1_I0_A0_EP1_DIRECTION, FS_C1_I0_A0_EP1_MAX_PACKET);
 378
 379                             #endif
 380                             #if (FS_C1_I0_A0_EP_NUMBER >= 2)
 381                             //EP0X02
 382                             mUsbEPMap(EP2, FS_C1_I0_A0_EP2_MAP);
 383                             mUsbFIFOMap(FS_C1_I0_A0_EP2_FIFO_START, FS_C1_I0_A0_EP2_FIFO_MAP);
 384                             mUsbFIFOConfig(FS_C1_I0_A0_EP2_FIFO_START, FS_C1_I0_A0_EP2_FIFO_CONFIG);
 385
 386                             for(i = FS_C1_I0_A0_EP2_FIFO_START + 1 ;
 387                                 i < FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO ;
 388                                 i ++)
 389                             {
 390                                 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP2_FIFO_CONFIG & (~BIT7)) );
 391                             }
 392
 393                             mUsbEPMxPtSzHigh(EP2, FS_C1_I0_A0_EP2_DIRECTION, (FS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff));
 394                             mUsbEPMxPtSzLow(EP2, FS_C1_I0_A0_EP2_DIRECTION, (FS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff));
 395                             mUsbEPinHighBandSet(EP2 , FS_C1_I0_A0_EP2_DIRECTION, FS_C1_I0_A0_EP2_MAX_PACKET);
 396
 397                             #endif
 398                             #if (FS_C1_I0_A0_EP_NUMBER >= 3)
 399                             //EP0X03
 400                             mUsbEPMap(EP3, FS_C1_I0_A0_EP3_MAP);
 401                             mUsbFIFOMap(FS_C1_I0_A0_EP3_FIFO_START, FS_C1_I0_A0_EP3_FIFO_MAP);
 402                             mUsbFIFOConfig(FS_C1_I0_A0_EP3_FIFO_START, FS_C1_I0_A0_EP3_FIFO_CONFIG);
 403
 404                             for(i = FS_C1_I0_A0_EP3_FIFO_START + 1 ;
 405                                 i < FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO ;
 406                                 i ++)
 407                             {
 408                                 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP3_FIFO_CONFIG & (~BIT7)) );
 409                             }
 410
 411                             mUsbEPMxPtSzHigh(EP3, FS_C1_I0_A0_EP3_DIRECTION, (FS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff));
 412                             mUsbEPMxPtSzLow(EP3, FS_C1_I0_A0_EP3_DIRECTION, (FS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff));
 413                             mUsbEPinHighBandSet(EP3 , FS_C1_I0_A0_EP3_DIRECTION, FS_C1_I0_A0_EP3_MAX_PACKET);
 414
 415                             #endif
 416                             #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
 417                             //EP0X04
 418                             mUsbEPMap(EP4, FS_C1_I0_A0_EP4_MAP);
 419                             mUsbFIFOMap(FS_C1_I0_A0_EP4_FIFO_START, FS_C1_I0_A0_EP4_FIFO_MAP);
 420                             mUsbFIFOConfig(FS_C1_I0_A0_EP4_FIFO_START, FS_C1_I0_A0_EP4_FIFO_CONFIG);
 421
 422                             for(i = FS_C1_I0_A0_EP4_FIFO_START + 1 ;
 423                                 i < FS_C1_I0_A0_EP4_FIFO_START + FS_C1_I0_A0_EP4_FIFO_NO ;
 424                                 i ++)
 425                             {
 426                                 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP4_FIFO_CONFIG & (~BIT7)) );
 427                             }
 428
 429                             mUsbEPMxPtSzHigh(EP4, FS_C1_I0_A0_EP4_DIRECTION, (FS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff));
 430                             mUsbEPMxPtSzLow(EP4, FS_C1_I0_A0_EP4_DIRECTION, (FS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff));
 431                             mUsbEPinHighBandSet(EP4 , FS_C1_I0_A0_EP4_DIRECTION, FS_C1_I0_A0_EP4_MAX_PACKET);
 432
 433                             #endif
 434                             #if (FS_C1_I0_A0_EP_NUMBER >= 5)
 435                             //EP0X05
 436                             mUsbEPMap(EP5, FS_C1_I0_A0_EP5_MAP);
 437                             mUsbFIFOMap(FS_C1_I0_A0_EP5_FIFO_START, FS_C1_I0_A0_EP5_FIFO_MAP);
 438                             mUsbFIFOConfig(FS_C1_I0_A0_EP5_FIFO_START, FS_C1_I0_A0_EP5_FIFO_CONFIG);
 439
 440                             for(i = FS_C1_I0_A0_EP5_FIFO_START + 1 ;
 441                                 i < FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO ;
 442                                 i ++)
 443                             {
 444                                 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP5_FIFO_CONFIG & (~BIT7)) );
 445                             }
 446
 447                             mUsbEPMxPtSzHigh(EP5, FS_C1_I0_A0_EP5_DIRECTION, (FS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff));
 448                             mUsbEPMxPtSzLow(EP5, FS_C1_I0_A0_EP5_DIRECTION, (FS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff));
 449                             mUsbEPinHighBandSet(EP5 , FS_C1_I0_A0_EP5_DIRECTION, FS_C1_I0_A0_EP5_MAX_PACKET);
 450                             #endif
 451                             break;
 452                         #endif
 453                         default:
 454                             break;
 455                     }
 456                     break;
 457                 #endif
 458                 default:
 459                     break;
 460             }
 461             break;
 462         #endif
 463         default:
 464             break;
 465     }
 466     //mCHECK_STACK();
 467 }
 468
 469 #endif