1 Copyright (c) 1999 Massachusetts Institute of Technology
3 This program is free software; you can redistribute it and/or modify
4 it under the terms of the GNU General Public License as published by
5 the Free Software Foundation; either version 3 of the License, or (at
6 your option) any later version.
8 This program is distributed in the hope that it will be useful, but
9 WITHOUT ANY WARRANTY; without even the implied warranty of
10 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 General Public License for more details.
13 You should have received a copy of the GNU General Public License
14 along with this program; if not, write to the Free Software
15 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
16 ------------------------------
20 This file attempts to maintain up-to-date documentation on
21 ITS interrupts. Those wonderful
22 souls who update the information in any way (additions,
23 deletions, corrections) should describe their
24 modifications in a brief note to INFO-ITS@AI so
25 that interested parties can correct their copies or
26 conceptions without needing to print or read the
27 entire file again. For example:
29 :QMAIL INFO-ITS@AI I added more details to the %PIJST interrupt ^C
31 If you want to be put on the INFO-ITS mailing list,
32 just say so in a message to it.
33 -------------------------------------------------
35 <Most of ITS INTRUP is not here...>
37 FIRST The Interrupt Bits in the First Interrupt Word.
39 The interrupt classes are:
40 [1] stops job and interrupts superior (fatal intr)
41 [2] stops job and interrupts superior unless enabled and undeferred
42 [3] does nothing unless enabled; waits if deferred.
44 Bits in the left half have two names: %PI... as a bit in the word,
45 and %PJ... shifted down by 18. bits.
47 The following interrupts abort the instruction, and leave the PC pointing
48 before the instruction if %OPOPC is 1 (as is winning), or after it if
49 %OPOPC is 0: %PIMPV, %PIOOB, %PIIOC, %PIILO, %PITTY, %PIWRO, %PIFET, %PITRP.
51 "(S)" indicates a synchronous interrupt; "(A)", an asynchronous one.
52 An interrupt is synchronous if its occurrence is always directly related
53 to the instruction that is being executed when it is signaled.
55 SECOND The Interrupt Bits in the Second Interrupt Word.
57 The right half of the second word (.IFPIR) is used for I/O channel
58 interrupts that signal the arrival of or need for data.
59 They should not be confused with I/O channel error interrupts
60 or IOCERRors. Each channel has its own bit: 1.1 is for channel
61 0; 1.2, for channel 1; ... 2.7, for channel 17 .
62 They are all class 3, and their significance depends on the device
65 The left half of the second word (.IFPIR) is used for
66 "inferior got a fatal interrupt" interrupts. Each of a job's
67 inferiors is assigned its own interrupt bit from among the
68 bottom 8 bits of the left half. When an inferior job is created,
69 its interrupt bit should be read and remembered by reading the
70 .INTB variable with a .USET. Every time that inferior gets a fatal
71 interrupt, it will be stopped and the superior will receive an
72 interrupt on that inferior's bit in .IFPIR. The inferior may
73 be restarted by zeroing its .USTP variable, but if the fatal
74 interrupts remain and are still fatal the inferior will simply
75 stop and interrupt the superior again. "Inferior got a fatal
76 interrupt" interrupts are all class 3.
78 The reason that inferiors interrupt through a special set of bits
79 instead of using I/O channel interrupts is that it makes it possible
80 to receive interrupts from all one's inferiors without having them
81 all open on I/O channels at all times. DDT normally keeps only
82 its current job open, and when it receives an interrupt from some
83 other job it opens that job temporarily.
85 STACK The format of the new-style interrupt stack
87 -----------------------------------
88 | 1st word interrupt bits |
89 -----------------------------------
90 | 2nd word interrupt bits |
91 -----------------------------------
93 -----------------------------------
95 -----------------------------------
96 | Saved program counter |
97 -----------------------------------
99 | Saved accumulators, if any |
101 -----------------------------------
102 | Saved .JPC, if requested |
103 -----------------------------------
104 | Saved .SUUOH, if requested |
105 -----------------------------------
106 Top -> | Saved LSPCL, if requested |
107 -----------------------------------
109 %PICLI CLI interrupt [3] (A)
111 Some job opened the CLI device with filenames equal
112 to the uname and jname of this job.
114 %PIPDL PDL overflow [3] (S)
116 %PILTP 340 or E&S light pen hit [3] (A)
118 %PIMAR MAR hit. [2] (S)
120 The MAR is a hardware feature that allows
121 references to a specific memory location to
122 be trapped. This is the interrupt that happens
123 when such a reference is detected. The guilty
124 instuction is usually not aborted; if it is, the
125 PC is SOS'ed regardless of the setting of %OPOPC.
126 See the .MARA and .MARPC variables.
128 %PIMPV MPV (memory protect violation) [2] (S)
130 The job referenced a non-existent memory location.
131 The address of that location (roundd down to
132 a page boundary on KA-10's) may be found in .MPVA.
133 The guilty instruction was aborted, and the PC was
134 left set according to %OPOPC.
136 %PICLK Slow (1/2 sec) clock [3] (A)
138 %PI1PR Single-instruction proceed [1] (S)
140 If a job is started with the one-proceed flag
141 (%PC1PR on KA-10's) set, after one instruction
142 is completed a %PI1PR interrupt will occur.
143 DDT's ^N command uses this feature.
145 %PIBRK .BREAK instruction executed. [1] (S)
147 .BREAK is used for DDT breakpoints, and for explicit
148 program requests to DDT.
150 %PIOOB Address out of bounds [2] (S)
152 This is an obscure condition that used to
153 happen on USR device IOT's, when an attempt
154 was made to refer to a nonexistent location in the
155 other job. Now this always causes an MPV.
156 The guilty instruction was aborted, and the PC was
157 left set according to %OPOPC.
159 %PIIOC IOCERR (I/O channel error) [2] (S)
161 This indicates the failure of an I/O system
162 call. The channel that was being operated on is
163 in .BCHN, and its .IOS word should contain, in
164 bits 4.5 - 4.1, an error code.
165 The guilty instruction was aborted, and the PC was
166 left set according to %OPOPC.
168 %PIVAL .VALUE instruction executed [1] (S)
170 %PIDWN System-going-down status change [3] (A)
172 If the system changes its mind about whether
173 or when it is scheduled to go down, this interrupt
176 %PIILO ILOPR, ILUUO (illegal operation) [2] (S)
178 This can be caused by a returnable uuo when the
179 program's 41 doesn't seem suitable for handling one
180 (see ITS UUOS). It can also be used to report
181 the failure of certain more archaic system calls.
182 The guilty instruction was aborted, and the PC was
183 left set according to %OPOPC.
185 %PIDIS Display memory protect [2] (A)
187 The 340 or E&S display got an MPV.
188 This is now obsolete since the 340 and E&S
191 %PIARO Arithmetic overflow [3] (S)
193 The PDP-10's built-in arithmetic overflow
194 condition was detected by the hardware.
195 In fact, overflow occurs so often
196 that enabling this interrupt causes the
197 machine to slow down considerably,
198 and it should be avoided.
200 %PIB42 BADPI (Bad location 42) [1] (S)
202 If in attempting to interrupt a job it turns out
203 to be necessary to refer to nonexistent memory
204 or write in read-only memory, this interrupt
205 is signaled, instead of MPV or WIRO.
206 This is so that the program will return to DDT
207 instead of mysteriously looping.
209 %PIC.Z ^Z or CALL typed on terminal [1] (A)
211 %PITYI TTY input (obsolete) [3] (A)
213 %PIRLT Real-time timer went off [3] (A)
215 These interrupts are controlled by the .REALT
218 %PIRUN Run-time timer went off [3] (A)
220 This interrupt is requested (in advance)
223 %PINXI Non-existent IO register [2] (S)
225 A Job in User IOT mode referenced a non-existent IO
226 register on the KS10 Unibus. The PC is left pointing
227 before the guilty instruction. The address of the
228 non-existant register may be found in .MPVA.
230 %PIJST Job Status display request. [3] (A)
232 The sequence ^_J was typed on the
233 console owned by this process or some inferior.
235 %PIDCL Deferred call. [1] (S)
237 An attempt was made to read TTY input
238 and the next character was a deferred-call
239 character (^_D or Control-CALL).
240 This deferred-call character is never seen
241 by the program; it just causes the interrupt.
242 It differs from ordinary CALL or ^Z
243 in that it takes effect when the program
244 gets around to reading it, not immediately.
246 %PIATY TTY returned. [3] (A)
248 This interrupt happens when the TTY is
249 returned by the superior, after having
250 been taken away. TECO uses this to know
251 that it must redisplay the entire screen.
253 %PITTY Don't have TTY [2] (S)
255 This results from an attempt to use the job's
256 console tty when the job does not own it, if
257 %TBINT is 1 and %TBWAT is 0. See ITS TTY.
258 The guilty instruction is aborted, and the PC is
259 left set according to %OPOPC.
261 %PIPAR Memory parity error [2] (A)
263 Programs are not intended to try to recover
264 from parity errors, on the assumption that they
265 are probably permanently screwed up.
266 This interrupt is asynchronous because it can
267 be caused by a parity error in another job
268 which destroys data in a page shared with this job.
270 %PIFOV ARFOV (Floating overflow) [3] (S)
272 This is a non-aborting PDP-10 hardware condition.
274 %PIWRO WIRO (Write in read-only page) [2] (S)
276 The guilty instruction was aborted, and the PC was
277 left set according to %OPOPC. The address of read
278 only location (rounded down to a page boundary on
279 KA-10's) may be found in .MPVA.
281 %PIFET Fetched insn from impure page [2] (S)
283 On KA-10's, if bit %PCPUR of the PC flags is 1,
284 fetching an instruction from an impure page
285 will cause this interrupt. This is supposed to
286 facilitate catching jumps to randomness.
287 The guilty instruction is aborted, and the PC is
288 left set according to %OPOPC.
290 %PITRP SYSUUO (System uuo in trap mode) [2] (S)
292 A job whose .UTRAP variable was nonzero either
293 attempted to execute an instruction that trapped
294 to the system, or was about to be interrupted.
295 This feature is intended to be used by the superior
296 to provide a non-ITS environment for the inferior.
297 For that purpose, this interrupt should not be
298 enabled for the inferior, so that it will be fatal.
299 The guilty instruction was aborted, and the PC was
300 left set according to %OPOPC.
302 %PIDBG System being debugged state change [3] (A)
304 When the system enters or leaves "debugging mode",
305 this interrupt is signaled.
307 %PILOS Lossage signaled. [2] (S)
309 A .LOSE UUO or a LOSE system call was executed.