1 #ifndef SPECIAL_PURPOSE_REGISTER_H_
2 #define SPECIAL_PURPOSE_REGISTER_H_
4 /* Special purpose register definitions */
6 #define SPR_RXE_0x00 spr000
7 #define SPR_RXE_Copy_Offset spr001
8 #define SPR_RXE_Copy_Length spr002
9 #define SPR_RXE_FIFOCTL0 spr003
10 #define SPR_RXE_FIFOCTL1 spr004
11 #define RXE_FIFOCTL1_STARTCOPY 0 /* bit0: Start copying the data into the FIFO */
12 #define RXE_FIFOCTL1_SUSPEND 2 /* bit2: Suspend the RX engine. Used during TX */
13 #define RXE_FIFOCTL1_HAVEPAD 5 /* bit5: Padding for RX frame present */
14 #define SPR_Received_Frame_Count spr005
15 #define SPR_RXE_0x0c spr006
16 #define SPR_RXE_RXHDR_OFFSET spr007
17 #define SPR_RXE_RXHDR_LEN spr008
18 #define SPR_RXE_PHYRXSTAT0 spr009
19 #define SPR_RXE_PHYRXSTAT1 spr00a
20 #define SPR_RXE_0x16 spr00b
21 #define SPR_RXE_FRAMELEN spr00c
22 #define SPR_RXE_0x1a spr00d
23 #define RXE_0x1a_OVERFLOW 15 /* bit15: Indicate FIFO overflow */
24 #define SPR_RXE_ENCODING spr00e
25 #define RXE_ENCODING_OFDM 13 /* bit13: Frame encoding was OFDM */
26 #define SPR_RXE_0x1e spr00f
27 #define SPR_RCM_Control spr010
28 #define SPR_RCM_Match_Data spr011
29 #define SPR_RCM_Match_Mask spr012
30 #define SPR_RCM_Match_Delay spr013
31 #define SPR_RCM_Condition_Mask_Low spr014
32 #define SPR_RCM_Condition_Mask_High spr015
33 #define SPR_RCM_Condition_Delay spr016
34 #define SPR_RXE_0x2e spr017
35 #define SPR_Ext_IHR_Address spr018
36 #define SPR_Ext_IHR_Data spr019
37 #define SPR_RXE_PHYRXSTAT2 spr01a
38 #define SPR_RXE_PHYRXSTAT3 spr01b
39 #define SPR_PHY_Mode spr01c
40 #define SPR_RCM_TA_Control spr01d
41 #define SPR_RCM_TA_Size spr01e
42 #define SPR_RCM_TA_Address_0 spr01f
43 #define SPR_RCM_TA_Address_1 spr020
44 #define SPR_RCM_TA_Address_2 spr021
45 #define SPR_RXE_0x44 spr022
46 #define SPR_RXE_0x46 spr023
47 #define SPR_RXE_0x48 spr024
48 #define SPR_RXE_0x4a spr025
49 #define SPR_RXE_0x4c spr026
50 #define SPR_RXE_0x4e spr027
51 #define SPR_RXE_0x50 spr028
52 #define SPR_RXE_0x52 spr029
53 #define SPR_RXE_0x54 spr02a
54 #define SPR_RXE_0x56 spr02b
55 #define SPR_RXE_0x58 spr02c
56 #define SPR_RXE_0x5a spr02d
57 #define SPR_RXE_0x5c spr02e
58 #define SPR_RXE_0x5e spr02f
59 #define SPR_RXE_0x60 spr030
60 #define SPR_RXE_0x62 spr031
61 #define SPR_RXE_0x64 spr032
62 #define SPR_RXE_0x66 spr033
63 #define SPR_RXE_0x68 spr034
64 #define SPR_RXE_0x6a spr035
65 #define SPR_RXE_0x6c spr036
66 #define SPR_RXE_0x6e spr037
67 #define SPR_RXE_0x70 spr038
68 #define SPR_RXE_0x72 spr039
69 #define SPR_RXE_0x74 spr03a
70 #define SPR_RXE_0x76 spr03b
71 #define SPR_RXE_0x78 spr03c
72 #define SPR_RXE_0x7a spr03d
73 #define SPR_RXE_0x7c spr03e
74 #define SPR_RXE_0x7e spr03f
75 #define SPR_MAC_MAX_NAP spr040
76 #define SPR_MAC_CTLHI spr041
77 #define SPR_MAC_IRQLO spr042
78 #define SPR_MAC_IRQHI spr043
79 #define SPR_MAC_IRQMASKLO spr044
80 #define SPR_MAC_IRQMASKHI spr045
81 #define SPR_PSM_0x0c spr046
82 #define SPR_MAC_CMD spr047
83 #define MACCMD_BEAC0 0 /* bit0: Beacon 0 busy/valid */
84 #define MACCMD_BEAC1 1 /* bit1: Beacon 1 busy/valid */
85 #define MACCMD_DFQ 2 /* bit2: Directed frame queue valid */
86 #define MACCMD_CCA 3 /* bit3: Channel clear assessment */
87 #define MACCMD_BGNOISE 4 /* bit4: BG-noise measurement request */
88 #define SPR_BRC spr048
89 #define BRC_TXMOREFRAGS 4 /* bit4: Set if there are more TX frags to come */
90 #define SPR_PHY_HDR_Parameter spr049
91 #define SPR_Postcard spr04a
92 #define SPR_Postcard_Location_Low spr04b
93 #define SPR_Postcard_Location_High spr04c
94 #define SPR_GPIO_IN spr04d
95 #define SPR_GPIO_OUT spr04e
96 #define SPR_GPIO_OUTEN spr04f
97 #define SPR_BRED0 spr050
98 #define SPR_BRED1 spr051
99 #define SPR_BRED2 spr052
100 #define SPR_BRED3 spr053
101 #define SPR_BRCL0 spr054
102 #define SPR_BRCL1 spr055
103 #define SPR_BRCL2 spr056
104 #define SPR_BRCL3 spr057
105 #define SPR_BRPO0 spr058
106 #define SPR_BRPO1 spr059
107 #define SPR_BRPO2 spr05a
108 #define SPR_BRPO3 spr05b
109 #define SPR_BRWK0 spr05c
110 #define SPR_BRWK1 spr05d
111 #define SPR_BRWK2 spr05e
112 #define SPR_BRWK3 spr05f
113 #define SPR_BASE0 spr060 /* Offset Register 0 */
114 #define SPR_BASE1 spr061 /* Offset Register 1 */
115 #define SPR_BASE2 spr062 /* Offset Register 2 */
116 #define SPR_BASE3 spr063 /* Offset Register 3 */
117 #define SPR_BASE4 spr064 /* Offset Register 4 */
118 #define SPR_BASE5 spr065 /* Offset Register 5 */
119 #define SPR_BASE6 spr066 /* Do not use. It's broken! */
120 #define SPR_PSM_0x4e spr067
121 #define SPR_PC0 spr068 /* Link Register 0 */
122 #define SPR_PC1 spr069 /* Link Register 1 */
123 #define SPR_PC2 spr06a /* Link Register 2 */
124 #define SPR_PC3 spr06b /* Link Register 3 */
125 #define SPR_PSM_COND spr06c /* PSM external condition bits */
126 #define SPR_PSM_0x5a spr06d
127 #define SPR_PSM_0x5c spr06e
128 #define SPR_PSM_0x5e spr06f
129 #define SPR_PSM_0x60 spr070
130 #define SPR_PSM_0x62 spr071
131 #define SPR_PSM_0x64 spr072
132 #define SPR_PSM_0x66 spr073
133 #define SPR_PSM_0x68 spr074
134 #define SPR_PSM_0x6a spr075
135 #define SPR_PSM_0x6c spr076
136 #define SPR_PSM_0x6e spr077
137 #define SPR_PSM_0x70 spr078
138 #define SPR_PSM_0x72 spr079
139 #define SPR_PSM_0x74 spr07a
140 #define SPR_PSM_0x76 spr07b
141 #define SPR_PSM_0x78 spr07c
142 #define SPR_PSM_0x7a spr07d
143 #define SPR_PSM_0x7c spr07e
144 #define SPR_PSM_0x7e spr07f
145 #define SPR_TXE0_CTL spr080
146 #define TXE_CTL_ENABLED 0 /* bit0: The engine is enabled */
147 #define TXE_CTL_FCS 14 /* bit14: Generate the FCS */
148 #define SPR_TXE0_AUX spr081
149 #define SPR_TXE0_TS_LOC spr082
150 #define SPR_TXE0_TIMEOUT spr083
151 #define SPR_TXE0_WM0 spr084
152 #define SPR_TXE0_WM1 spr085
153 #define SPR_TXE0_PHY_CTL spr086
154 #define SPR_TXE0_STATUS spr087
155 #define TXE_STATUS_BUSY 7 /* bit7: TX engine busy */
156 #define TXE_STATUS_MEND 10 /* bit10: TXE M end */
157 #define SPR_TXE0_0x16 spr08b
159 // New Registers; Source: d11.h 578947 2015-08-13 04:46:06Z
160 // http://github.com/tuapuikia/asuswrt-phantom/blob/master/release/src-rt-7.14.114.x/src/include/d11.h
161 #define SPR_TXE0_MMPLCP0 spr088
162 #define SPR_TXE0_MMPLCP1 spr089
163 #define SPR_TXE0_PHY_CTL1 spr08a
165 #define SPR_TX_STATUS0 spr08c
166 #define SPR_TX_STATUS1 spr08d
167 #define SPR_TX_STATUS2 spr08e
168 #define SPR_TX_STATUS3 spr08f
169 #define SPR_TXE0_FIFO_Def spr090
171 // New Registers; Source: d11.h 578947 2015-08-13 04:46:06Z
172 // http://github.com/tuapuikia/asuswrt-phantom/blob/master/release/src-rt-7.14.114.x/src/include/d11.h
173 #define SPR_TXE0_FIFO_Frame_Count spr091 /* Corerev >= 16 */
174 #define SPR_TXE0_FIFO_Byte_Count spr092 /* Corerev >= 16 */
175 #define SPR_TXE0_FIFO_Head spr093 /* Corerev >= 16 */
176 #define SPR_TXE0_FIFO_Read_Pointer spr094 /* Corerev >= 16 */
177 #define SPR_TXE0_FIFO_Write_Pointer spr095 /* Corerev >= 16 */
178 #define SPR_TXE0_FIFO_DEF1 spr096 /* Corerev >= 16 */
180 // New Registers; Source: d11.h 578947 2015-08-13 04:46:06Z
181 // http://github.com/tuapuikia/asuswrt-phantom/blob/master/release/src-rt-7.14.114.x/src/include/d11.h
182 #define SPR_TXE0_AGGFIFO_CMD spr097
183 #define SPR_TXE0_AGGFIFO_STAT spr098
184 #define SPR_TXE0_AGGFIFO_CFG_Control spr099
185 #define SPR_TXE0_AGGFIFO_CFG_Data spr09a
186 #define SPR_TXE0_AGGFIFO_MPDUNUM spr09b
187 #define SPR_TXE0_AGGFIFO_Length spr09c
188 #define SPR_TXE0_AGGFIFO_BMP spr09d
189 #define SPR_TXE0_AGGFIFO_ACKEDCNT spr09e
190 #define SPR_TXE0_AGGFIFO_SEL spr09f
192 #define SPR_TXE0_FIFO_CMD spr0a0
193 #define TXE_FIFO_CMD_TXDONE 13 /* bit13: Set after the current transmission finished */
194 #define TXE_FIFO_CMD_COPY 14 /* bit14: Start copying of data */
195 #define SPR_TXE0_FIFO_FLUSH spr0a1
196 #define SPR_TXE0_FIFO_THRES spr0a2
197 #define SPR_TXE0_FIFO_RDY spr0a3 /* FIFO-ready bitmask. bit-nr = FIFO-nr */
198 #define SPR_TXE0_FIFO_PRI_RDY spr0a4
199 #define SPR_TXE0_FIFO_RQ_PRI spr0a5
200 #define SPR_TXE0_Template_TX_Pointer spr0a6
201 #define SPR_TXE0_0x4e spr0a7
202 #define SPR_TXE0_Template_Pointer spr0a8
204 // New Registers; Source: d11.h 578947 2015-08-13 04:46:06Z
205 // http://github.com/tuapuikia/asuswrt-phantom/blob/master/release/src-rt-7.14.114.x/src/include/d11.h
206 #define SPR_TXE0_CLCT_STRPTR spr0a9 /* Corerev >= 22 */
207 #define SPR_TXE0_CLCT_STPPTR spr0aa /* Corerev >= 22 */
208 #define SPR_TXE0_CLCT_CURPTR spr0ab /* Corerev >= 22 */
209 #define SPR_TXE0_AGGFIFO_Data spr0ac
211 #define SPR_TXE0_0x5a spr0ad
212 #define SPR_TXE0_0x5c spr0ae
213 #define SPR_TXE0_0x5e spr0af
215 #define SPR_TXE0_Template_Data_Low spr0b0
216 #define SPR_TXE0_Template_Data_High spr0b1
217 #define SPR_TXE0_0x64 spr0b2
218 #define SPR_TXE0_0x66 spr0b3
219 #define SPR_TXE0_SELECT spr0b4
220 #define TXE_SELECT_DST 0x0003 /* Destination code mask */
221 #define TXE_SELECT_DST_SHM 0x0001 /* Destination code for the SHM */
222 #define TXE_SELECT_DST_PHY 0x0002 /* Destination code for the PHY */
223 #define TXE_SELECT_DST_DISCARD 0x0003 /* Destination code for discarding */
224 #define TXE_SELECT_USE_TXCNT 2 /* bit2: Use the TX_COUNT register */
225 #define TXE_SELECT_UNK0x20 5 /* bit5: ??FIXME: Unknown meaning. Seems to be PHY related. */
226 #define TXE_SELECT_SRC 0x1F00 /* Source code mask */
227 #define TXE_SELECT_SRC_SHIFT 8
228 #define TXE_SELECT_SRC_FIFO0 0x0000 /* Source code for FIFO 0 */
229 #define TXE_SELECT_SRC_FIFO1 0x0100 /* Source code for FIFO 1 */
230 #define TXE_SELECT_SRC_FIFO2 0x0200 /* Source code for FIFO 2 */
231 #define TXE_SELECT_SRC_FIFO3 0x0300 /* Source code for FIFO 3 */
232 #define TXE_SELECT_SRC_FIFO4 0x0400 /* Source code for FIFO 4 */
233 #define TXE_SELECT_SRC_FIFO5 0x0500 /* Source code for FIFO 5 */
234 #define TXE_SELECT_SRC_FIFO6 0x0600 /* Source code for FIFO 6 */
235 #define TXE_SELECT_SRC_FIFO7 0x0700 /* Source code for FIFO 7 */
236 #define TXE_SELECT_SRC_TRAM 0x0800 /* Source code for Template Ram */
237 #define SPR_TXE0_TX_COUNT spr0b5 /* Number of bytes to process */
238 #define SPR_TXE0_TX_SHM_ADDR spr0b6 /* The SHM address to copy the TX header to (in bytes!) */
239 #define SPR_TXE0_0x6e spr0b7
240 #define SPR_TXE0_0x70 spr0b8
241 #define SPR_TXE0_0x72 spr0b9
242 #define SPR_TXE0_0x74 spr0ba
243 #define SPR_TXE0_0x76 spr0bb
244 #define SPR_TXE0_0x78 spr0bc
245 #define SPR_TXE0_0x7a spr0bd
246 #define SPR_TXE0_0x7c spr0be
247 #define SPR_TXE0_0x7e spr0bf
248 /* Transmit Modify Engine masks */
249 #define SPR_TME_MASK0 spr0c0
250 #define SPR_TME_MASK2 spr0c1
251 #define SPR_TME_MASK4 spr0c2
252 #define SPR_TME_MASK6 spr0c3
253 #define SPR_TME_MASK8 spr0c4
254 #define SPR_TME_MASK10 spr0c5
255 #define SPR_TME_MASK12 spr0c6
256 #define SPR_TME_MASK14 spr0c7
257 #define SPR_TME_MASK16 spr0c8
258 #define SPR_TME_MASK18 spr0c9
259 #define SPR_TME_MASK20 spr0ca
260 #define SPR_TME_MASK22 spr0cb
261 #define SPR_TME_MASK24 spr0cc
262 #define SPR_TME_MASK26 spr0cd
263 #define SPR_TME_MASK28 spr0ce
264 #define SPR_TME_MASK30 spr0cf
265 #define SPR_TME_MASK32 spr0d0
266 #define SPR_TME_MASK34 spr0d1
267 #define SPR_TME_MASK36 spr0d2
268 #define SPR_TME_MASK38 spr0d3
269 #define SPR_TME_MASK40 spr0d4
270 #define SPR_TME_MASK42 spr0d5
271 #define SPR_TME_MASK44 spr0d6
272 #define SPR_TME_MASK46 spr0d7
273 #define SPR_TME_MASK48 spr0d8
274 #define SPR_TME_MASK50 spr0d9
275 #define SPR_TME_MASK52 spr0da
276 #define SPR_TME_MASK54 spr0db
277 #define SPR_TME_MASK56 spr0dc
278 #define SPR_TME_MASK58 spr0dd
279 #define SPR_TME_MASK60 spr0de
280 #define SPR_TME_MASK62 spr0df
281 /* Transmit Modify Engine values */
282 #define SPR_TME_VAL0 spr0e0
283 #define SPR_TME_VAL2 spr0e1
284 #define SPR_TME_VAL4 spr0e2
285 #define SPR_TME_VAL6 spr0e3
286 #define SPR_TME_VAL8 spr0e4
287 #define SPR_TME_VAL10 spr0e5
288 #define SPR_TME_VAL12 spr0e6
289 #define SPR_TME_VAL14 spr0e7
290 #define SPR_TME_VAL16 spr0e8
291 #define SPR_TME_VAL18 spr0e9
292 #define SPR_TME_VAL20 spr0ea
293 #define SPR_TME_VAL22 spr0eb
294 #define SPR_TME_VAL24 spr0ec
295 #define SPR_TME_VAL26 spr0ed
296 #define SPR_TME_VAL28 spr0ee
297 #define SPR_TME_VAL30 spr0ef
298 #define SPR_TME_VAL32 spr0f0
299 #define SPR_TME_VAL34 spr0f1
300 #define SPR_TME_VAL36 spr0f2
301 #define SPR_TME_VAL38 spr0f3
302 #define SPR_TME_VAL40 spr0f4
303 #define SPR_TME_VAL42 spr0f5
304 #define SPR_TME_VAL44 spr0f6
305 #define SPR_TME_VAL46 spr0f7
306 #define SPR_TME_VAL48 spr0f8
307 #define SPR_TME_VAL50 spr0f9
308 #define SPR_TME_VAL52 spr0fa
309 #define SPR_TME_VAL54 spr0fb
310 #define SPR_TME_VAL56 spr0fc
311 #define SPR_TME_VAL58 spr0fd
312 #define SPR_TME_VAL60 spr0fe
313 #define SPR_TME_VAL62 spr0ff
314 #define SPR_TSF_0x00 spr100
315 #define SPR_TSF_0x02 spr101
316 #define SPR_TSF_CFP_Start_Low spr102
317 #define SPR_TSF_CFP_Start_High spr103
318 #define SPR_TSF_0x08 spr104
319 #define SPR_TSF_0x0a spr105
320 #define SPR_TSF_0x0c spr106
321 #define SPR_TSF_0x0e spr107
322 #define SPR_TSF_0x10 spr108
323 #define SPR_TSF_CFP_PreTBTT spr109
324 #define SPR_TSF_0x14 spr10a
325 #define SPR_TSF_0x16 spr10b
326 #define SPR_TSF_0x18 spr10c
327 #define SPR_TSF_0x1a spr10d
328 #define SPR_TSF_0x1c spr10e
329 #define SPR_TSF_0x1e spr10f
330 #define SPR_TSF_0x20 spr110
331 #define SPR_TSF_0x22 spr111
332 #define SPR_TSF_0x24 spr112
333 #define SPR_TSF_0x26 spr113
334 #define SPR_TSF_0x28 spr114
335 #define SPR_TSF_0x2a spr115
336 #define SPR_TX_FES_Time spr116
337 #define SPR_TSF_0x2e spr117
338 #define SPR_TSF_0x30 spr118
339 #define SPR_TSF_WORD0 spr119
340 #define SPR_TSF_WORD1 spr11a
341 #define SPR_TSF_WORD2 spr11b
342 #define SPR_TSF_WORD3 spr11c
343 #define SPR_TSF_0x3a spr11d
344 #define SPR_TSF_0x3c spr11e
345 #define SPR_TSF_0x3e spr11f
346 #define SPR_TSF_0x40 spr120
347 #define SPR_TSF_0x42 spr121
348 #define SPR_TSF_0x44 spr122
349 #define SPR_TSF_GPT0_STAT spr123
350 #define GPT_STAT_EN 15 /* bit15: Enable the timer */
351 #define GPT_STAT_8MHZ 14 /* bit14: Use 8MHz base (otherwise 88MHz) */
352 #define SPR_TSF_GPT1_STAT spr124
353 #define SPR_TSF_GPT0_CNTLO spr125
354 #define SPR_TSF_GPT1_CNTLO spr126
355 #define SPR_TSF_GPT0_CNTHI spr127
356 #define SPR_TSF_GPT1_CNTHI spr128
357 #define SPR_TSF_GPT0_VALLO spr129
358 #define SPR_TSF_GPT1_VALLO spr12a
359 #define SPR_TSF_GPT0_VALHI spr12b
360 #define SPR_TSF_GPT1_VALHI spr12c
361 #define SPR_TSF_RANDOM spr12d
362 #define SPR_TSF_0x5c spr12e
363 #define SPR_TSF_0x5e spr12f
364 #define SPR_TSF_0x60 spr130
365 #define SPR_TSF_0x62 spr131
366 #define SPR_TSF_0x64 spr132
367 #define SPR_TSF_GPT2_STAT spr133
368 #define SPR_TSF_GPT2_CNTLO spr134
369 #define SPR_TSF_GPT2_CNTHI spr135
370 #define SPR_TSF_GPT2_VALLO spr136
371 #define SPR_TSF_GPT2_VALHI spr137
372 #define SPR_TSF_GPT_ALL_STAT spr138
373 #define SPR_TSF_0x72 spr139
374 #define SPR_TSF_0x74 spr13a
375 #define SPR_TSF_0x76 spr13b
376 #define SPR_TSF_0x78 spr13c
377 #define SPR_TSF_0x7a spr13d
378 #define SPR_TSF_0x7c spr13e
379 #define SPR_TSF_0x7e spr13f
380 #define SPR_IFS_sifs_rx_tx_tx spr140
381 #define SPR_IFS_sifs_nav_tx spr141
382 #define SPR_IFS_slot spr142
383 #define SPR_IFS_0x06 spr143
384 #define SPR_IFS_CTL spr144
385 #define SPR_IFS_BKOFFTIME spr145 /* BackoffTime; in units of PHY slots */
386 #define SPR_IFS_0x0c spr146
387 #define SPR_IFS_0x0e spr147
388 #define SPR_IFS_STAT spr148
389 #define SPR_IFS_med_busy_ctl spr149
390 #define SPR_IFS_if_tx_duration spr14a
391 #define SPR_IFS_0x16 spr14b
392 #define SPR_IFS_0x18 spr14c
393 #define SPR_IFS_0x1a spr14d
395 // New Registers; Source: d11.h 578947 2015-08-13 04:46:06Z
396 // http://github.com/tuapuikia/asuswrt-phantom/blob/master/release/src-rt-7.14.114.x/src/include/d11.h
397 /* EDCF support in dot11macs with corerevs >= 16 */
398 #define SPR_IFS_AIFSN spr14e
399 #define SPR_IFS_CTL1 spr14f
401 #define SPR_SCC_Control spr150
402 #define SPR_SCC_Timer_Low spr151
403 #define SPR_SCC_Timer_High spr152
404 #define SPR_SCC_Divisor spr153
405 #define SPR_SCC_Fast_Powerup_Delay spr154
406 #define SPR_SCC_Period spr155
407 #define SPR_SCC_Period_Divisor spr156
409 // New Registers; Source: d11.h 578947 2015-08-13 04:46:06Z
410 // http://github.com/tuapuikia/asuswrt-phantom/blob/master/release/src-rt-7.14.114.x/src/include/d11.h
411 #define SPR_SCC_CAL_Timer_Low spr157
412 #define SPR_SCC_CAL_Timer_High spr158
414 #define SPR_IFS_0x32 spr159
416 // New Registers; Source: d11.h 578947 2015-08-13 04:46:06Z
417 // http://github.com/tuapuikia/asuswrt-phantom/blob/master/release/src-rt-7.14.114.x/src/include/d11.h
418 /* BTCX block on corerev >=13 */
419 #define SPR_BTCX_Control spr15a
420 #define SPR_BTCX_Stat spr15b
421 #define SPR_BTCX_Transmit_Control spr15c
422 #define SPR_BTCX_PRI_WIN spr15d
423 #define SPR_BTCX_TX_Conf_Timer spr15e
424 #define SPR_BTCX_ANT_SW_Timer spr15f
425 #define SPR_BTCX_PRV_RFACT_Timer spr160
426 #define SPR_BTCX_CUR_RFACT_Timer spr161
427 #define SPR_BTCX_RFACT_DUR_Timer spr162
428 #define SPR_IFS_CTL_SEL_PRICRS spr163
429 #define SPR_IFS_CTL_SEL_SECCRS spr164
431 #define SPR_IFS_0x4a spr165
432 #define SPR_IFS_0x4c spr166
433 #define SPR_IFS_0x4e spr167
434 #define SPR_IFS_0x50 spr168
435 #define SPR_IFS_0x52 spr169
436 #define SPR_IFS_0x54 spr16a
437 #define SPR_IFS_0x56 spr16b
438 #define SPR_IFS_0x58 spr16c
439 #define SPR_IFS_0x5a spr16d
440 #define SPR_IFS_0x5c spr16e
441 #define SPR_IFS_0x5e spr16f
442 #define SPR_IFS_0x60 spr170
443 #define SPR_IFS_0x62 spr171
444 #define SPR_IFS_0x64 spr172
445 #define SPR_IFS_0x66 spr173
446 #define SPR_IFS_0x68 spr174
447 #define SPR_IFS_0x6a spr175
448 #define SPR_IFS_0x6c spr176
449 #define SPR_IFS_0x6e spr177
451 // New Registers; Source: d11.h 578947 2015-08-13 04:46:06Z
452 // http://github.com/tuapuikia/asuswrt-phantom/blob/master/release/src-rt-7.14.114.x/src/include/d11.h
453 /* ECI regs on corerev >=14 */
454 #define SPR_BTCX_ECI_Address spr178
455 #define SPR_BTCX_ECI_Data spr179
457 #define SPR_IFS_0x74 spr17a
458 #define SPR_IFS_0x76 spr17b
459 #define SPR_IFS_0x78 spr17c
460 #define SPR_IFS_0x7a spr17d
461 #define SPR_IFS_0x7c spr17e
462 #define SPR_IFS_0x7e spr17f
464 #define SPR_NAV_CTL spr180
465 #define SPR_NAV_STAT spr181
466 #define SPR_NAV_0x04 spr182
467 #define SPR_NAV_0x06 spr183
468 #define SPR_NAV_0x08 spr184
469 #define SPR_NAV_0x0a spr185
470 #define SPR_NAV_ALLOCATION spr186
471 #define SPR_NAV_0x0e spr187
472 #define SPR_NAV_0x10 spr188
473 #define SPR_NAV_0x12 spr189
474 #define SPR_NAV_0x14 spr18a
475 #define SPR_NAV_0x16 spr18b
476 #define SPR_NAV_0x18 spr18c
477 #define SPR_NAV_0x1a spr18d
478 #define SPR_NAV_0x1c spr18e
479 #define SPR_NAV_0x1e spr18f
480 #define SPR_NAV_0x20 spr190
481 #define SPR_NAV_0x22 spr191
482 #define SPR_NAV_0x24 spr192
483 #define SPR_NAV_0x26 spr193
484 #define SPR_NAV_0x28 spr194
485 #define SPR_NAV_0x2a spr195
486 #define SPR_NAV_0x2c spr196
487 #define SPR_NAV_0x2e spr197
488 #define SPR_NAV_0x30 spr198
489 #define SPR_NAV_0x32 spr199
490 #define SPR_NAV_0x34 spr19a
491 #define SPR_NAV_0x36 spr19b
492 #define SPR_NAV_0x38 spr19c
493 #define SPR_NAV_0x3a spr19d
494 #define SPR_NAV_0x3c spr19e
495 #define SPR_NAV_0x3e spr19f
496 #define SPR_NAV_0x40 spr1a0
497 #define SPR_NAV_0x42 spr1a1
498 #define SPR_NAV_0x44 spr1a2
499 #define SPR_NAV_0x46 spr1a3
500 #define SPR_NAV_0x48 spr1a4
501 #define SPR_NAV_0x4a spr1a5
502 #define SPR_NAV_0x4c spr1a6
503 #define SPR_NAV_0x4e spr1a7
504 #define SPR_NAV_0x50 spr1a8
505 #define SPR_NAV_0x52 spr1a9
506 #define SPR_NAV_0x54 spr1aa
507 #define SPR_NAV_0x56 spr1ab
508 #define SPR_NAV_0x58 spr1ac
509 #define SPR_NAV_0x5a spr1ad
510 #define SPR_NAV_0x5c spr1ae
511 #define SPR_NAV_0x5e spr1af
512 #define SPR_NAV_0x60 spr1b0
513 #define SPR_NAV_0x62 spr1b1
514 #define SPR_NAV_0x64 spr1b2
515 #define SPR_NAV_0x66 spr1b3
516 #define SPR_NAV_0x68 spr1b4
517 #define SPR_NAV_0x6a spr1b5
518 #define SPR_NAV_0x6c spr1b6
519 #define SPR_NAV_0x6e spr1b7
520 #define SPR_NAV_0x70 spr1b8
521 #define SPR_NAV_0x72 spr1b9
522 #define SPR_NAV_0x74 spr1ba
523 #define SPR_NAV_0x76 spr1bb
524 #define SPR_NAV_0x78 spr1bc
525 #define SPR_NAV_0x7a spr1bd
526 #define SPR_NAV_0x7c spr1be
527 #define SPR_NAV_0x7e spr1bf
528 #define SPR_WEP_0x00 spr1c0
529 #define SPR_WEP_0x02 spr1c1
530 #define SPR_WEP_0x04 spr1c2
531 #define SPR_WEP_0x06 spr1c3
532 #define SPR_WEP_0x08 spr1c4
533 #define SPR_WEP_0x0a spr1c5
534 #define SPR_WEP_0x0c spr1c6
535 #define SPR_WEP_0x0e spr1c7
536 #define SPR_WEP_0x10 spr1c8
537 #define SPR_WEP_0x12 spr1c9
538 #define SPR_WEP_0x14 spr1ca
539 #define SPR_WEP_0x16 spr1cb
540 #define SPR_WEP_0x18 spr1cc
541 #define SPR_WEP_0x1a spr1cd
542 #define SPR_WEP_0x1c spr1ce
543 #define SPR_WEP_0x1e spr1cf
544 #define SPR_WEP_0x20 spr1d0
545 #define SPR_WEP_0x22 spr1d1
546 #define SPR_WEP_0x24 spr1d2
547 #define SPR_WEP_0x26 spr1d3
548 #define SPR_WEP_0x28 spr1d4
549 #define SPR_WEP_0x2a spr1d5
550 #define SPR_WEP_0x2c spr1d6
551 #define SPR_WEP_0x2e spr1d7
552 #define SPR_WEP_0x30 spr1d8
553 #define SPR_WEP_0x32 spr1d9
554 #define SPR_WEP_0x34 spr1da
555 #define SPR_WEP_0x36 spr1db
556 #define SPR_WEP_0x38 spr1dc
557 #define SPR_WEP_0x3a spr1dd
558 #define SPR_WEP_0x3c spr1de
559 #define SPR_WEP_0x3e spr1df
560 #define SPR_WEP_CTL spr1e0
561 #define SPR_WEP_IV_Location spr1e1
562 #define SPR_WEP_IV_Key spr1e2
563 #define SPR_WEP_WKey spr1e3
564 #define SPR_WEP_0x48 spr1e4
565 #define SPR_WEP_0x4a spr1e5
566 #define SPR_WEP_0x4c spr1e6
567 #define SPR_WEP_0x4e spr1e7
568 #define SPR_WEP_0x50 spr1e8
569 #define SPR_WEP_0x52 spr1e9
570 #define SPR_WEP_0x54 spr1ea
571 #define SPR_WEP_AES_Control spr1eb
572 #define SPR_WEP_0x58 spr1ec
573 #define SPR_WEP_0x5a spr1ed
574 #define SPR_WEP_0x5c spr1ee
575 #define SPR_WEP_0x5e spr1ef
576 #define SPR_PMQ_control_low spr1f0
577 #define SPR_PMQ_control_high spr1f1
578 #define SPR_PMQ_pat_0 spr1f2
579 #define SPR_PMQ_pat_1 spr1f3
580 #define SPR_PMQ_pat_2 spr1f4
581 #define SPR_PMQ_dat spr1f5
582 #define SPR_PMQ_dat_or spr1f6
583 #define SPR_PMQ_0x0e spr1f7
584 #define SPR_PMQ_pat_h0 spr1f8
585 #define SPR_PMQ_pat_h1 spr1f9
586 #define SPR_PMQ_pat_h2 spr1fa
587 #define SPR_PMQ_dat_h spr1fb
588 #define SPR_PMQ_0x18 spr1fc
589 #define SPR_PMQ_0x1a spr1fd
590 #define SPR_PMQ_0x1c spr1fe
591 #define SPR_PMQ_0x1e spr1ff
593 // New 802.11ac Registers; Source: d11.h 578947 2015-08-13 04:46:06Z
594 // http://github.com/tuapuikia/asuswrt-phantom/blob/master/release/src-rt-7.14.114.x/src/include/d11.h
596 #define SPR_AQM_Config spr200
597 #define SPR_AQM_FIFO_Def spr201
598 #define SPR_AQM_Max_IDX spr202
599 #define SPR_AQM_RCVD_BA0 spr203
600 #define SPR_AQM_RCVD_BA1 spr204
601 #define SPR_AQM_RCVD_BA2 spr205
602 #define SPR_AQM_RCVD_BA3 spr206
603 #define SPR_AQM_BASSN spr207
604 #define SPR_AQM_REFSN spr208
605 #define SPR_AQM_Max_Agg_Len_Low spr209
606 #define SPR_AQM_Max_Agg_Len_High spr20a
607 #define SPR_AQM_Agg_Params spr20b
608 #define SPR_AQM_Min_MPDU_Length spr20c
609 #define SPR_AQM_MAC_Adj_Length spr20d
610 #define SPR_AQM_Debug_Bus_Control spr20e
611 #define SPR_AQM_Agg_Stats spr210
612 #define SPR_AQM_Agg_Len_Low spr211
613 #define SPR_AQM_Agg_Len_High spr212
614 #define SPR_AQM_IDX_FIFO spr213
615 #define SPR_AQM_MPDU_Len_FIFO spr214
616 #define SPR_AQM_TX_Control_FIFO spr215
617 #define SPR_AQM_Upd_BA0 spr216
618 #define SPR_AQM_Upd_BA1 spr217
619 #define SPR_AQM_Upd_BA2 spr218
620 #define SPR_AQM_Upd_BA3 spr219
621 #define SPR_AQM_ACK_Control spr21a
622 #define SPR_AQM_Cons_Control spr21b
623 #define SPR_AQM_FIFO_Ready spr21c
624 #define SPR_AQM_Start_Loc spr21d
625 #define SPR_TDCCTL spr220
626 #define SPR_TDC_PLCP0 spr221
627 #define SPR_TDC_PLCP1 spr222
628 #define SPR_TDC_Frame_Length0 spr223
629 #define SPR_TDC_Frame_Length1 spr224
630 #define SPR_TDC_TX_Time spr225
631 #define SPR_TDC_VHT_Sig_B0 spr226
632 #define SPR_TDC_VHT_Sig_B1 spr227
633 #define SPR_TDC_VHT_L_Sig_Len spr228
634 #define SPR_TDC_VHT_N_Sym0 spr229
635 #define SPR_TDC_VHT_N_Sym1 spr22a
636 #define SPR_TDC_VHT_PSDU_Len0 spr22b
637 #define SPR_TDC_VHT_PSDU_Len1 spr22c
638 #define SPR_TDC_VHT_MAC_PAD spr22d
639 #define SPR_SHMDMA_Control spr230
640 #define SPR_SHMDMA_TXDC_Address spr231
641 #define SPR_SHMDMA_SHM_Address spr232
642 #define SPR_SHMDMA_Xfer_Cnt spr233
643 #define SPR_TXDC_Address spr234
644 #define SPR_TXDC_Data spr235
646 #define SPR_MHP_Status spr240
647 #define SPR_MHP_FC spr241
648 #define SPR_MHP_DUR spr242
649 #define SPR_MHP_SC spr243
650 #define SPR_MHP_QOS spr244
651 #define SPR_MHP_HTC_High spr245
652 #define SPR_MHP_HTC_Low spr246
653 #define SPR_MHP_Addr1_High spr247
654 #define SPR_MHP_Addr1_Mid spr248
655 #define SPR_MHP_Addr1_Low spr249
656 #define SPR_MHP_Addr2_High spr250
657 #define SPR_MHP_Addr2_Mid spr251
658 #define SPR_MHP_Addr2_Low spr252
659 #define SPR_MHP_Addr3_High spr253
660 #define SPR_MHP_Addr3_Mid spr254
661 #define SPR_MHP_Addr3_Low spr255
662 #define SPR_MHP_Addr4_High spr256
663 #define SPR_MHP_Addr4_Mid spr257
664 #define SPR_MHP_Addr4_Low spr258
665 #define SPR_MHP_CFG spr259
666 #define SPR_DAGG_CTL2 spr260
667 #define SPR_DAGG_BYTESLEFT spr261
668 #define SPR_DAGG_SH_OFFSET spr262
669 #define SPR_DAGG_STAT spr263
670 #define SPR_DAGG_LEN spr264
671 #define SPR_TXBA_Control spr265
672 #define SPR_TXBA_Data_Select spr266
673 #define SPR_TXBA_Data spr267
674 #define SPR_AMT_Control spr270
675 #define SPR_AMT_Status spr271
676 #define SPR_AMT_Limit spr272
677 #define SPR_AMT_Attr spr273
678 #define SPR_AMT_Match1 spr274
679 #define SPR_AMT_Match2 spr275
680 #define SPR_AMT_Table_Address spr276
681 #define SPR_AMT_Table_Data spr277
682 #define SPR_AMT_Table_Value spr278
683 #define SPR_AMT_Debug_Select spr279
684 #define SPR_ROE_Control spr280
685 #define SPR_ROE_Status spr281
686 #define SPR_ROE_IP_Checksum spr282
687 #define SPR_ROE_TCPUDP_Checksum spr283
688 #define SPR_PSO_Control spr290
689 #define SPR_PSO_RX_Words_Watermark spr291
690 #define SPR_PSO_RX_Cnt_Watermark spr292
691 #define SPR_OBFF_Control spr298
692 #define SPR_OBFF_RX_Words_Watermark spr299
693 #define SPR_OBFF_RX_Cnt_Watermark spr29a
695 #define SPR_TOE_Control spr300
696 #define SPR_TOE_Rst spr301
697 #define SPR_TOE_CSumNZ spr302
698 #define SPR_TX_Serial_Control spr320
699 #define SPR_TX_PLCP_Sig0 spr321
700 #define SPR_TX_PLCP_Sig1 spr322
701 #define SPR_TX_PLCP_HT_Sig0 spr323
702 #define SPR_TX_PLCP_HT_Sig1 spr324
703 #define SPR_TX_PLCP_HT_Sig2 spr325
704 #define SPR_TX_PLCP_VHT_SigB0 spr326
705 #define SPR_TX_PLCP_VHT_SigB1 spr327
706 #define SPR_MAC_Header_From_SHM_Length spr329
707 #define SPR_TX_PLCP_Length spr32a
708 #define SPR_TX_BF_Rpt_Length spr32c
709 #define SPR_TX_BF_Control spr330
710 #define SPR_Bfm_Rpt_Offset spr331
711 #define SPR_Bfm_Rpt_Length spr332
712 #define SPR_TX_BF_BfeRptRdCnt spr333
714 /* Named definitions for the Transmit Modify Engine MASK registers */
715 #define SPR_TME_M_PLCP0 SPR_TME_MASK0 /* PLCP header (low) */
716 #define SPR_TME_M_PLCP1 SPR_TME_MASK2 /* PLCP header (middle) */
717 #define SPR_TME_M_PLCP2 SPR_TME_MASK4 /* PLCP header (high) */
718 #define SPR_TME_M_FCTL SPR_TME_MASK6 /* Frame control */
719 #define SPR_TME_M_DURID SPR_TME_MASK8 /* Duration / ID */
720 #define SPR_TME_M_ADDR1_0 SPR_TME_MASK10 /* Address 1 (low) */
721 #define SPR_TME_M_ADDR1_1 SPR_TME_MASK12 /* Address 1 (middle) */
722 #define SPR_TME_M_ADDR1_2 SPR_TME_MASK14 /* Address 1 (high) */
723 #define SPR_TME_M_ADDR2_0 SPR_TME_MASK16 /* Address 2 (low) */
724 #define SPR_TME_M_ADDR2_1 SPR_TME_MASK18 /* Address 2 (middle) */
725 #define SPR_TME_M_ADDR2_2 SPR_TME_MASK20 /* Address 2 (high) */
726 #define SPR_TME_M_ADDR3_0 SPR_TME_MASK22 /* Address 3 (low) */
727 #define SPR_TME_M_ADDR3_1 SPR_TME_MASK24 /* Address 3 (middle) */
728 #define SPR_TME_M_ADDR3_2 SPR_TME_MASK26 /* Address 3 (high) */
729 #define SPR_TME_M_SEQ SPR_TME_MASK28 /* Sequence control */
730 #define SPR_TME_M_ADDR4_0 SPR_TME_MASK30 /* Address 4 (low) */
731 #define SPR_TME_M_ADDR4_1 SPR_TME_MASK32 /* Address 4 (middle) */
732 #define SPR_TME_M_ADDR4_2 SPR_TME_MASK34 /* Address 4 (high) */
734 /* Named definitions for the Transmit Modify Engine VALUE registers */
735 #define SPR_TME_V_PLCP0 SPR_TME_VAL0 /* PLCP header (low) */
736 #define SPR_TME_V_PLCP1 SPR_TME_VAL2 /* PLCP header (middle) */
737 #define SPR_TME_V_PLCP2 SPR_TME_VAL4 /* PLCP header (high) */
738 #define SPR_TME_V_FCTL SPR_TME_VAL6 /* Frame control */
739 #define SPR_TME_V_DURID SPR_TME_VAL8 /* Duration / ID */
740 #define SPR_TME_V_ADDR1_0 SPR_TME_VAL10 /* Address 1 (low) */
741 #define SPR_TME_V_ADDR1_1 SPR_TME_VAL12 /* Address 1 (middle) */
742 #define SPR_TME_V_ADDR1_2 SPR_TME_VAL14 /* Address 1 (high) */
743 #define SPR_TME_V_ADDR2_0 SPR_TME_VAL16 /* Address 2 (low) */
744 #define SPR_TME_V_ADDR2_1 SPR_TME_VAL18 /* Address 2 (middle) */
745 #define SPR_TME_V_ADDR2_2 SPR_TME_VAL20 /* Address 2 (high) */
746 #define SPR_TME_V_ADDR3_0 SPR_TME_VAL22 /* Address 3 (low) */
747 #define SPR_TME_V_ADDR3_1 SPR_TME_VAL24 /* Address 3 (middle) */
748 #define SPR_TME_V_ADDR3_2 SPR_TME_VAL26 /* Address 3 (high) */
749 #define SPR_TME_V_SEQ SPR_TME_VAL28 /* Sequence control */
750 #define SPR_TME_V_ADDR4_0 SPR_TME_VAL30 /* Address 4 (low) */
751 #define SPR_TME_V_ADDR4_1 SPR_TME_VAL32 /* Address 4 (middle) */
752 #define SPR_TME_V_ADDR4_2 SPR_TME_VAL34 /* Address 4 (high) */
755 /* Interrupts (SPR_MAC_IRQLO/HI) */
756 #define IRQLO_MAC_SUSPENDED 0x0001
757 #define IRQLO_BEACONTEMP_AVAIL 0x0002
758 #define IRQLO_TBTT_INDI 0x0004
759 #define IRQLO_BEACON_TX_OK 0x0008
760 #define IRQLO_BEACON_CANCEL 0x0010
761 #define IRQLO_ATIM_END 0x0020
762 #define IRQLO_PMQ 0x0040
763 #define IRQLO_UNDEFINED_0 0x0080
764 #define IRQLO_PIO_WORKAROUND 0x0100
765 #define IRQLO_MAC_TXERR 0x0200
766 #define IRQLO_UNDEFINED_2 0x0400
767 #define IRQLO_PHY_TXERR 0x0800
768 #define IRQLO_PMEVENT 0x1000
769 #define IRQLO_TIMER0 0x2000
770 #define IRQLO_TIMER1 0x4000
771 #define IRQLO_DMA 0x8000
772 #define IRQHI_TXFIFO_FLUSH_OK 0x0001
773 #define IRQHI_CCA_MEASURE_OK 0x0002
774 #define IRQHI_NOISESAMPLE_OK 0x0004
775 #define IRQHI_UNDEFINED_3 0x0008
776 #define IRQHI_UNDEFINED_4 0x0010
777 #define IRQHI_UNDEFINED_5 0x0020
778 #define IRQHI_UNDEFINED_6 0x0040
779 #define IRQHI_UNDEFINED_7 0x0080
780 #define IRQHI_UNDEFINED_8 0x0100
781 #define IRQHI_UNDEFINED_9 0x0200
782 #define IRQHI_UNDEFINED_10 0x0400
783 #define IRQHI_DEBUG 0x0800
784 #define IRQHI_RFKILL 0x1000
785 #define IRQHI_TX_OK 0x2000
786 #define IRQHI_PHY_G_CHANGED 0x4000
787 #define IRQHI_TIMEOUT 0x8000
790 /* MAC Control High bits */
791 #define MACCTL_BE 0 /* bit0: Big Endian mode */
792 #define MACCTL_INFRA 1 /* bit1: Infrastructure mode */
793 #define MACCTL_AP 2 /* bit2: AccessPoint mode */
794 #define MACCTL_RADIOLOCK 3 /* bit3: Radio lock */
795 #define MACCTL_BEACPROMISC 4 /* bit4: Beacon Promiscuous */
796 #define MACCTL_KEEP_BADPLCP 5 /* bit5: Keep frames with bad PLCP */
797 #define MACCTL_KEEP_CTL 6 /* bit6: Keep control frames */
798 #define MACCTL_KEEP_BAD 7 /* bit7: Keep bad frames (FCS) */
799 #define MACCTL_PROMISC 8 /* bit8: Promiscuous mode */
800 #define MACCTL_HWPS 9 /* bit9: Hardware Power Saving */
801 #define MACCTL_AWAKE 10 /* bit10: Device is awake */
802 #define MACCTL_CLOSEDNET 11 /* bit11: Closed net (no SSID bcast) */
803 #define MACCTL_TBTTHOLD 12 /* bit12: TBTT Hold */
804 #define MACCTL_DISCTXSTAT 13 /* bit13: Discard TX status */
805 #define MACCTL_DISCPMQ 14 /* bit14: Discard Power Management Queue */
806 #define MACCTL_GMODE 15 /* bit15: G Mode */
809 /* The FIFO queue numbers */
810 #define FIFO_BK 0 /* Background */
811 #define FIFO_BE 1 /* Best Effort */
812 #define FIFO_VI 2 /* Video */
813 #define FIFO_VO 3 /* Voice */
814 #define FIFO_MCAST 4 /* Broadcast / Multicast */
815 #define FIFO_ATIM 5 /* ATIM window info */
817 // 802.11 Frame Types; Source: mac_structures.h 578947 2015-08-13 04:46:06Z
818 // http://lxr.free-electrons.com/source/drivers/staging/winbond/mac_structures.h?v=2.6.32
819 //----- management : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7)
820 #define MAC_SUBTYPE_MNGMNT_ASSOC_REQUEST 0x00
821 #define MAC_SUBTYPE_MNGMNT_ASSOC_RESPONSE 0x10
822 #define MAC_SUBTYPE_MNGMNT_REASSOC_REQUEST 0x20
823 #define MAC_SUBTYPE_MNGMNT_REASSOC_RESPONSE 0x30
824 #define MAC_SUBTYPE_MNGMNT_PROBE_REQUEST 0x40
825 #define MAC_SUBTYPE_MNGMNT_PROBE_RESPONSE 0x50
826 #define MAC_SUBTYPE_MNGMNT_BEACON 0x80
827 #define MAC_SUBTYPE_MNGMNT_ATIM 0x90
828 #define MAC_SUBTYPE_MNGMNT_DISASSOCIATION 0xA0
829 #define MAC_SUBTYPE_MNGMNT_AUTHENTICATION 0xB0
830 #define MAC_SUBTYPE_MNGMNT_DEAUTHENTICATION 0xC0
831 //----- control : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7)
832 #define MAC_SUBTYPE_CONTROL_PSPOLL 0xA4
833 #define MAC_SUBTYPE_CONTROL_RTS 0xB4
834 #define MAC_SUBTYPE_CONTROL_CTS 0xC4
835 #define MAC_SUBTYPE_CONTROL_ACK 0xD4
836 #define MAC_SUBTYPE_CONTROL_CFEND 0xE4
837 #define MAC_SUBTYPE_CONTROL_CFEND_CFACK 0xF4
838 //----- data : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7)
839 #define MAC_SUBTYPE_DATA 0x08
840 #define MAC_SUBTYPE_DATA_CFACK 0x18
841 #define MAC_SUBTYPE_DATA_CFPOLL 0x28
842 #define MAC_SUBTYPE_DATA_CFACK_CFPOLL 0x38
843 #define MAC_SUBTYPE_DATA_NULL 0x48
844 #define MAC_SUBTYPE_DATA_CFACK_NULL 0x58
845 #define MAC_SUBTYPE_DATA_CFPOLL_NULL 0x68
846 #define MAC_SUBTYPE_DATA_CFACK_CFPOLL_NULL 0x78
849 #endif /* SPECIAL_PURPOSE_REGISTER_H_ */
851 // vim: syntax=b43 ts=8
projects / b43-tools.git / blob