Sun, 8 Aug 2021
When computer scientist Gordon Moore first formulated his thesis on the exponentially growing speed and power of integrated circuits in 1965, no one at the time could have predicted the prescience of his observations. Moore was the first to articulate the remarkable degree of consistency in the rate at which transistor density was increasing, with the number of transistors able to fit onto a single integrated circuit approximately doubling every 2 years. More than any other factor, it is this rate of exponential growth in the field of microprocessors that has fueled the rise of electronics. With the modern world now fully immersed in digital technology, demand for ever more powerful computing hardware shows no sign of abating.
After following the trajectory of progress established by Moore for nearly half a century, R&D departments in some of the world's largest semiconductor firms have begun to run up against the physical limits of transistor density.
For decades, chip manufacturers have adopted a fairly conventional approach to maximizing the computational potential of integrated circuits, with the goal being to fit as many transistors onto a single silicon wafer as possible, and thus far, the simple strategy has proven highly effective. Between 1978 and 2006, the SPECint computer performance benchmark standard recorded an exponentially rising rate of single-thread processor performance. However, once manufacturers began to exceed the transistor density threshold of roughly 5-7 nanometers in scale, strange subatomic forces begin to tamper with the flow of electric current running through the circuit.
One of the strangest, and most disruptive, is a phenomenon known as quantum tunneling, in which transistors are placed so close together that electrons are able to pass through the barriers, known as gate oxides, that separate them. This results in significant interference between neighboring transistors. Once integrated circuits reach this hard limit of transistor density, chip manufacturers have effectively reached the plateau of Moore's exponential growth curve, though incremental advances in transistor density can still be made by altering the types of metals used in the oxide gates to create a more stable barrier between transistors. Recent experiments have found promise in the use of other metals such as titanium and hafnium as alternatives to aluminum to form the basis of the oxide gate. However, the microprocessor industry has begun to recognize that the days of transistor density-driven growth have come to an end.
Intel, in particular, had for years been lagging behind other chip manufacturer's such as AMD and Samsung in its efforts to develop integrated circuits on the sub-7-nanometer scale. In their struggle to overcome the limitations of conventional integrated circuit technology, Intel researchers devised a unique strategy that involves building chips up rather than simply packing more transistors onto the same 2-dimensional silicon wafer. Known as the Foveros project, the new framework relies on building integrated circuits in a 3-dimensional lattice structure in which die are stacked on top of one another in a complex design that separates the processor into its constituent parts known as 'chiplets'. With the core processor secured on the base layer, the components most integral to performance, such as ASICs (Application-Specific Integrated Circuits), can be separated and then stacked upwards.
The 3-dimensional structure offers considerable scaling potential, as the copper wires that connect each layer are much shorter than those found in conventional 2-dimensional chips. This has the advantage of increasing signal propagation speed, while lowering power consumption by up to 100 times.
Intel is not alone, however, in their race to usher in this new paradigm of 3D-stacked semiconductors.
At the 2021 Computex technology conference, AMD CEO Lisa Su unveiled the company's own foray into the realm of 3-dimensional, stacked microprocessors. Dubbed, '3D V-Cache' technology, AMD claims that their proprietary chip-stacking architecture is far superior to Intel's, with an interconnect density over 15 times higher than Intel's highly anticipated Alder Lake line of 3D-stacked processors. AMD's latest attempt to challenge Intel was developed in partnership with TSMC, a Taiwanese semiconductor company and the largest producer of integrated chips by market capitalization.
We will have to wait and see whether continued advancement in 3-dimensional die stacking technology can be sustained in the long-term however, as scaling processors in 3 dimensions presents its own unique challenges. These include the need for longer, more costly test cycles due to increased complexity of the chip architecture, as well as greater difficulty in designing automated solutions for the 3D chip manufacturing process.
We have begun to enter uncharted territory in the realm of integrated circuits, however those who remain skeptical of our ability to continue pushing the envelope of microchip performance beyond the limits of Moore's law should note that computing speed and power were advancing at a near-exponential rate even before the transistor had been invented, although there is no indication that Gordon Moore was aware of this broader trend when he formulated his thesis on the exponential growth capabilities of the transistor. The earlier eras of vacuum tube and relay computers experienced their own exponential growth phases long before the transistor came onto the scene. Whether the advent of 3D stacking represents the latest paradigm shift to carry this exponential trend forward, or merely a temporary blip signaling the end of Moore's curve, no one can say. It will take many more iterations of 3-dimensional chip technology before manufacturers know for certain what lies ahead for the future of computing.
Copyright © 2021 Jason Self. See license.shtml for license conditions. Please copy and share.