GMP_VER=5.0.5
-GMP_URL=http://ftp.gnu.org/gnu/gmp/gmp-$(GMP_VER).tar.bz2
+GMP_URL=https://ftp.gnu.org/gnu/gmp/gmp-$(GMP_VER).tar.bz2
GMP_TAR=gmp-$(GMP_VER).tar.bz2
GMP_DIR=gmp-$(GMP_VER)
MPFR_VER=3.1.1
-MPFR_URL=http://ftp.gnu.org/gnu/mpfr/mpfr-$(MPFR_VER).tar.bz2
+MPFR_URL=https://ftp.gnu.org/gnu/mpfr/mpfr-$(MPFR_VER).tar.bz2
MPFR_TAR=mpfr-$(MPFR_VER).tar.bz2
MPFR_DIR=mpfr-$(MPFR_VER)
MPC_VER=1.0.1
-MPC_URL=http://ftp.gnu.org/gnu/mpc/mpc-$(MPC_VER).tar.gz
+MPC_URL=https://ftp.gnu.org/gnu/mpc/mpc-$(MPC_VER).tar.gz
MPC_TAR=mpc-$(MPC_VER).tar.gz
MPC_DIR=mpc-$(MPC_VER)
BINUTILS_VER=2.23.1
-BINUTILS_URL=http://ftp.gnu.org/gnu/binutils/binutils-$(BINUTILS_VER).tar.bz2
+BINUTILS_URL=https://ftp.gnu.org/gnu/binutils/binutils-$(BINUTILS_VER).tar.bz2
BINUTILS_TAR=binutils-$(BINUTILS_VER).tar.bz2
BINUTILS_DIR=binutils-$(BINUTILS_VER)
BINUTILS_PATCHES=local/patches/binutils.patch
GCC_VER=4.7.2
-GCC_URL=http://ftp.gnu.org/gnu/gcc/gcc-$(GCC_VER)/gcc-$(GCC_VER).tar.bz2
+GCC_URL=https://ftp.gnu.org/gnu/gcc/gcc-$(GCC_VER)/gcc-$(GCC_VER).tar.bz2
GCC_TAR=gcc-$(GCC_VER).tar.bz2
GCC_DIR=gcc-$(GCC_VER)
GCC_PATCHES=local/patches/gcc.patch
You're in for a treat.
+* Install the cmake build tool (http://www.cmake.org/). Major distributions have packages for this.
+
* You first have to build the toolchain.
* Linux:
magpie_fw_dev/target/buf_pool/buf_pool_static.c
magpie_fw_dev/target/cmnos/dbg_api.c
magpie_fw_dev/target/cmnos/cmnos_sflash.c
+ magpie_fw_dev/target/hif/usb_api_main_patch.c
wlan/ah.c
wlan/ah_osdep.c
wlan/ar5416Phy.c
IF(TARGET_K2)
SET(SOURCES ${SOURCES}
magpie_fw_dev/target/hif/k2_HIF_usb_patch.c
- magpie_fw_dev/target/hif/k2_fw_usb_api.c
+ magpie_fw_dev/target/hif/usb_api_k2_patch.c
)
SET(LIBS ${LIBS} hif)
ADD_DEFINITIONS(-DPROJECT_K2)
-DMAGPIE_MERLIN
)
SET(SOURCES ${SOURCES}
+ magpie_fw_dev/target/hif/usb_api_magpie_patch.c
magpie_fw_dev/target/rompatch/cmnos_clock_patch.c
- magpie_fw_dev/target/rompatch/usb_api_patch.c
magpie_fw_dev/target/rompatch/HIF_usb_patch.c
)
INCLUDE_DIRECTORIES(
+++ /dev/null
-/*
- * Copyright (c) 2013 Qualcomm Atheros, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted (subject to the limitations in the
- * disclaimer below) provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * * Neither the name of Qualcomm Atheros nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
- * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef USB_DEFS_H
-#define USB_DEFS_H
-
-#include "usb_table.h"
-#include "dt_defs.h"
-#include "reg_defs.h"
-
-#define CHECK_SWITCH_BY_BOOTCODE 1 //to be verified for ZD1215, OK for ZD1211
-#define VERIFY_CHECKSUM_BY_BOOTCODE 1
-
-/***********************************************************************/
-/* for SEEPROM Boot */
-/***********************************************************************/
-#define WLAN_BOOT_SIGNATURE (0x19710303)
-
-#define WLAN_SIGNATURE_ADDR (0x102000)
-
-#define cMAX_ADDR 0x10000
-
-#define cEEPROM_SIZE 0x800 // 2k word (4k byte)
-
-#define cRESERVE_LOAD_SPACE 0
-
-// start addr. of boot code
-#define cBOOT_CODE_ADDR (cMAX_ADDR - cEEPROM_SIZE) // 0xF800
-
-/************************** Register Addr Process *********************/
-#define mpADDR(addr) ((volatile uint16_t*) (addr))
-#define mADDR(addr) (*mpADDR(addr))
-#define muADDR(addr) ((uint16_t) (&(addr)))
-
-#define USB_BYTE_REG_WRITE(addr, val) HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val))
-#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3))
-//#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr))
-
-#define USB_HALF_WORD_REG_WRITE(addr, val) HAL_HALF_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr), (val))
-#define USB_HALF_WORD_REG_READ(addr) HAL_HALF_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr))
-
-#define USB_WORD_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val))
-#define USB_WORD_REG_READ(addr) HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr))
-
-
-/************************** Register Deinition ***************************/
-//#define USB_BASE_ADDR_SOC 0x8000
-
-//#define SOC_Reg mpADDR(USB_BASE_ADDR_SOC)
-
-#define cSOC_USB_OFST (0x100)
-
-#define ZM_CBUS_FIFO_SIZE_OFFSET (cSOC_USB_OFST) //OFFSET 0
-
-#define cSOC_CBUS_CTL_OFFSET 0xF0
-
-#define ZM_FUSB_BASE USB_CTRL_BASE_ADDRESS
-
-#define ZM_MAIN_CTRL_OFFSET 0x00
-#define ZM_DEVICE_ADDRESS_OFFSET 0x01
-#define ZM_TEST_OFFSET 0x02
-#define ZM_PHY_TEST_SELECT_OFFSET 0x08
-#define ZM_VDR_SPECIFIC_MODE_OFFSET 0x0A
-#define ZM_CX_CONFIG_STATUS_OFFSET 0x0B
-#define ZM_EP0_DATA1_OFFSET 0x0C
-#define ZM_EP0_DATA2_OFFSET 0x0D
-#define ZM_EP0_DATA_OFFSET 0x0C
-
-#define ZM_INTR_MASK_BYTE_0_OFFSET 0x11
-#define ZM_INTR_MASK_BYTE_1_OFFSET 0x12
-#define ZM_INTR_MASK_BYTE_2_OFFSET 0x13
-#define ZM_INTR_MASK_BYTE_3_OFFSET 0x14
-#define ZM_INTR_MASK_BYTE_4_OFFSET 0x15
-#define ZM_INTR_MASK_BYTE_5_OFFSET 0x16
-#define ZM_INTR_MASK_BYTE_6_OFFSET 0x17
-#define ZM_INTR_MASK_BYTE_7_OFFSET 0x18
-
-#define ZM_INTR_GROUP_OFFSET 0x20
-#define ZM_INTR_SOURCE_0_OFFSET 0x21
-#define ZM_INTR_SOURCE_1_OFFSET 0x22
-#define ZM_INTR_SOURCE_2_OFFSET 0x23
-#define ZM_INTR_SOURCE_3_OFFSET 0x24
-#define ZM_INTR_SOURCE_4_OFFSET 0x25
-#define ZM_INTR_SOURCE_5_OFFSET 0x26
-#define ZM_INTR_SOURCE_6_OFFSET 0x27
-#define ZM_INTR_SOURCE_7_OFFSET 0x28
-
-#define ZM_EP_IN_MAX_SIZE_HIGH_OFFSET 0x3F
-#define ZM_EP_IN_MAX_SIZE_LOW_OFFSET 0x3E
-
-#define ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET 0x5F
-#define ZM_EP_OUT_MAX_SIZE_LOW_OFFSET 0x5E
-
-#define ZM_EP3_BYTE_COUNT_HIGH_OFFSET 0xAE
-#define ZM_EP3_BYTE_COUNT_LOW_OFFSET 0xBE
-#define ZM_EP4_BYTE_COUNT_HIGH_OFFSET 0xAF
-#define ZM_EP4_BYTE_COUNT_LOW_OFFSET 0xBF
-
-#define ZM_EP3_DATA_OFFSET 0xF8
-#define ZM_EP4_DATA_OFFSET 0xFC
-
-#define ZM_SOC_USB_MODE_CTRL_OFFSET 0x108
-#define ZM_SOC_USB_MAX_AGGREGATE_OFFSET 0x110
-#define ZM_SOC_USB_TIME_CTRL_OFFSET 0x114
-
-#define ZM_ADDR_CONV 0x0
-
-#define ZM_CBUS_FIFO_SIZE_REG (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_CBUS_CTRL_REG (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_MAIN_CTRL_REG (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_DEVICE_ADDRESS_REG (ZM_DEVICE_ADDRESS_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_TEST_REG (ZM_TEST_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_PHY_TEST_SELECT_REG (ZM_PHY_TEST_SELECT_OFFSET^ZM_ADDR_CONV)))
-
-#define ZM_CX_CONFIG_STATUS_REG (ZM_CX_CONFIG_STATUS_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_EP0_DATA1_REG (ZM_EP0_DATA1_OFFSET^ZM_ADDR_CONV)))
-
-#define ZM_EP0_DATA2_REG (ZM_EP0_DATA2_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_EP0_DATA_REG (ZM_EP0_DATA_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_0_REG (ZM_INTR_MASK_BYTE_0_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_1_REG (ZM_INTR_MASK_BYTE_1_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_2_REG (ZM_INTR_MASK_BYTE_2_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_3_REG (ZM_INTR_MASK_BYTE_3_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_4_REG (ZM_INTR_MASK_BYTE_4_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_5_REG (ZM_INTR_MASK_BYTE_5_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_6_REG (ZM_INTR_MASK_BYTE_6_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_7_REG (ZM_INTR_MASK_BYTE_7_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_0_REG (ZM_INTR_SOURCE_0_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_1_REG (ZM_INTR_SOURCE_1_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_2_REG (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_3_REG (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_4_REG (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_5_REG (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_6_REG (ZM_INTR_SOURCE_6_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_7_REG (ZM_INTR_SOURCE_7_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_GROUP_REG (ZM_INTR_GROUP_OFFSET^ZM_ADDR_CONV)))
-
-#define ZM_EP3_BYTE_COUNT_HIGH_REG (ZM_EP3_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_EP3_BYTE_COUNT_LOW_REG (ZM_EP3_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_EP4_BYTE_COUNT_HIGH_REG (ZM_EP4_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_EP4_BYTE_COUNT_LOW_REG (ZM_EP4_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_EP3_DATA_REG (ZM_EP3_DATA_OFFSET)
-
-#define ZM_EP4_DATA_REG (ZM_EP4_DATA_OFFSET)
-
-#define ZM_SOC_USB_MODE_CTRL_REG (ZM_SOC_USB_MODE_CTRL_OFFSET)
-
-#define ZM_SOC_USB_MAX_AGGREGATE_REG (ZM_SOC_USB_MAX_AGGREGATE_OFFSET)
-
-#define ZM_SOC_USB_TIME_CTRL_REG (ZM_SOC_USB_TIME_CTRL_OFFSET)
-
-#define bmHIGH_SPEED BIT6
-#define bmCWR_BUF_END BIT1
-
-#define mUsbEP0DataRd1() (USB_BYTE_REG_READ(ZM_EP0_DATA1_OFFSET))
-//#define mUsbEP0DataRd2() ZM_EP0_DATA2_REG
-//#define mUsbEP0DataRd3() ZM_EP0_DATA3_REG
-//#define mUsbEP0DataRd4() ZM_EP0_DATA4_REG
-#define mUsbEP0DataWr1(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA1_OFFSET, data))
-#define mUsbEP0DataWr2(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA2_OFFSET, data))
-
-#define mGetByte0(data) ( data & 0xff )
-#define mGetByte1(data) ( (data >> 8) & 0xff )
-#define mGetByte2(data) ( (data >> 16) & 0xff )
-#define mGetByte3(data) ( (data >> 24) & 0xff )
-
-//#define mUsbHighSpeedST() (ZM_MAIN_CTRL_REG & BIT6)
-//#define mUsbCfgST() (ZM_DEVICE_ADDRESS_REG & BIT7)
-//#define mUsbApWrEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
-//#define mUsbApRdEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
-
-#define mUsbHighSpeedST() (USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET) & BIT6)
-#define mUsbCfgST() (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET) & BIT7)
-#define mUsbApWrEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
-#define mUsbApRdEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
-
-#define mUsbRmWkupST() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
- USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT0)
-#define mUsbRmWkupClr() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
- USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0)
-#define mUsbRmWkupSet() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
- USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0)
-
-#define mUsbGlobIntEnable() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
- USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2)
-
-#define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
- USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f)
-#define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
- USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)|0xc0)
-#define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
- USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf)
-#define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
- USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0)
-// USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0x40)
-
-#define mUSB_EP3_XFER_DONE() USB_BYTE_REG_WRITE(ZM_EP3_BYTE_COUNT_HIGH_OFFSET, \
- USB_BYTE_REG_READ(ZM_EP3_BYTE_COUNT_HIGH_OFFSET)|0x08)
-
-
-
-#define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512
-#define HS_C1_I0_A0_EP1_bInterval 00
-
-#define HS_C1_I0_A0_EP_NUMBER 0x06
-#define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
-#define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH)
-#define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH)
-
-#define HS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + HS_C1_INTERFACE_LENGTH)
-#define FS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + FS_C1_INTERFACE_LENGTH)
-
-#define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64
-//#define FS_C1_I0_A0_EP1_bInterval HS_C1_I0_A0_EP1_bInterval
-
-#define HS_CONFIGURATION_NUMBER 1
-#define FS_CONFIGURATION_NUMBER 1
-
-#define fDOUBLE_BUF 1
-#define fDOUBLE_BUF_IN 1
-
-#define fFLASH_DISK 0
-#define fENABLE_ISO 0
-
-#if (HS_CONFIGURATION_NUMBER >= 1)
- // Configuration 0X01
- #define HS_C1_INTERFACE_NUMBER 0x01
- #define HS_C1 0x01
- #define HS_C1_iConfiguration 0x00
- #define HS_C1_bmAttribute 0x80
- #if !(fFLASH_DISK && !fFLASH_BOOT)
- #define HS_C1_iMaxPower 0xFA
- #else
- #define HS_C1_iMaxPower 0x32
- #endif
-
- #if (HS_C1_INTERFACE_NUMBER >= 1)
- // Interface 0
- #define HS_C1_I0_ALT_NUMBER 0X01
- #if (HS_C1_I0_ALT_NUMBER >= 1)
- // AlternateSetting 0X00
- #define HS_C1_I0_A0_bInterfaceNumber 0X00
- #define HS_C1_I0_A0_bAlternateSetting 0X00
- //JWEI 2003/07/14
- //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
- #define HS_C1_I0_A0_EP_NUMBER 0x06
- //#else
- //#define HS_C1_I0_A0_EP_NUMBER 0X03
- //#endif
- #if !(fFLASH_DISK && !fFLASH_BOOT)
- #define HS_C1_I0_A0_bInterfaceClass 0XFF
- #define HS_C1_I0_A0_bInterfaceSubClass 0X00
- #define HS_C1_I0_A0_bInterfaceProtocol 0X00
- #else
- #define HS_C1_I0_A0_bInterfaceClass 0X08
- #define HS_C1_I0_A0_bInterfaceSubClass 0X06
- #define HS_C1_I0_A0_bInterfaceProtocol 0X50
- #endif
- #define HS_C1_I0_A0_iInterface 0X00
-
- #if (HS_C1_I0_A0_EP_NUMBER >= 1)
- //EP0X01
- #define HS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE
- //JWEI 2003/05/19
- #if fDOUBLE_BUF
- #define HS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK
- #else
- #define HS_C1_I0_A0_EP1_BLKNO SINGLE_BLK
- #endif
- #define HS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT
- #define HS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK
- //JWEI 2003/05/07
- #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512
- #define HS_C1_I0_A0_EP1_bInterval 00
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 2)
- //EP0X02
- #define HS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE
- //JWEI 2003/08/20
- #if fDOUBLE_BUF_IN
- #define HS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK
- #else
- #define HS_C1_I0_A0_EP2_BLKNO SINGLE_BLK
- #endif
- #define HS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN
- #define HS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK
- #define HS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_512
- #define HS_C1_I0_A0_EP2_bInterval 00
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 3)
- //EP0X03
- #define HS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE
- #define HS_C1_I0_A0_EP3_BLKNO SINGLE_BLK
- #define HS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN
- #define HS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT
- #define HS_C1_I0_A0_EP3_MAX_PACKET 0x0040
- #define HS_C1_I0_A0_EP3_bInterval 01
- #endif
- // Note: HS Bulk type require max pkt size = 512
- // ==> must use Interrupt type for max pkt size = 64
- #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
- //EP0X04
- #define HS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE
- #define HS_C1_I0_A0_EP4_BLKNO SINGLE_BLK
- #define HS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT
- #define HS_C1_I0_A0_EP4_TYPE TF_TYPE_INTERRUPT
- #define HS_C1_I0_A0_EP4_MAX_PACKET 0x0040
- #define HS_C1_I0_A0_EP4_bInterval 01
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 5)
- //EP0X04
- #define HS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE
- #if fDOUBLE_BUF
- #define HS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK
- #else
- #define HS_C1_I0_A0_EP5_BLKNO SINGLE_BLK
- #endif
- #define HS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT
- #define HS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK
- #define HS_C1_I0_A0_EP5_MAX_PACKET MX_PA_SZ_512
- #define HS_C1_I0_A0_EP5_bInterval 00
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 6)
- //EP0X04
- #define HS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE
- #if fDOUBLE_BUF
- #define HS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK
- #else
- #define HS_C1_I0_A0_EP6_BLKNO SINGLE_BLK
- #endif
- #define HS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT
- #define HS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK
- #define HS_C1_I0_A0_EP6_MAX_PACKET MX_PA_SZ_512
- #define HS_C1_I0_A0_EP6_bInterval 00
- #endif
- #endif
- #endif
-#endif
-
-#if (HS_CONFIGURATION_NUMBER >= 1)
- // Configuration 1
- #if (HS_C1_INTERFACE_NUMBER >= 1)
- // Interface 0
- #if (HS_C1_I0_ALT_NUMBER >= 1)
- // AlternateSetting 0
- #define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
- #if (HS_C1_I0_A0_EP_NUMBER >= 1)
- // EP1
- #define HS_C1_I0_A0_EP1_FIFO_START FIFO0
- #define HS_C1_I0_A0_EP1_FIFO_NO (HS_C1_I0_A0_EP1_BLKNO * HS_C1_I0_A0_EP1_BLKSIZE)
- #define HS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP1_BLKNO - 1) << 2) | HS_C1_I0_A0_EP1_TYPE)
- #define HS_C1_I0_A0_EP1_FIFO_MAP (((1 - HS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
- #define HS_C1_I0_A0_EP1_MAP (HS_C1_I0_A0_EP1_FIFO_START | (HS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP1_DIRECTION)))
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 2)
- // EP2
- #if fDOUBLE_BUF
- #define HS_C1_I0_A0_EP2_FIFO_START (HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO)
- #else
- #define HS_C1_I0_A0_EP2_FIFO_START FIFO2
- #endif
- #define HS_C1_I0_A0_EP2_FIFO_NO (HS_C1_I0_A0_EP2_BLKNO * HS_C1_I0_A0_EP2_BLKSIZE)
- #define HS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP2_BLKNO - 1) << 2) | HS_C1_I0_A0_EP2_TYPE)
- #define HS_C1_I0_A0_EP2_FIFO_MAP (((1 - HS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
- #define HS_C1_I0_A0_EP2_MAP (HS_C1_I0_A0_EP2_FIFO_START | (HS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP2_DIRECTION)))
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 3)
- // EP3
- //JWEI 2003/07/15
- // #define HS_C1_I0_A0_EP3_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
- #define HS_C1_I0_A0_EP3_FIFO_START FIFO14
- #define HS_C1_I0_A0_EP3_FIFO_NO (HS_C1_I0_A0_EP3_BLKNO * HS_C1_I0_A0_EP3_BLKSIZE)
- #define HS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP3_BLKNO - 1) << 2) | HS_C1_I0_A0_EP3_TYPE)
- #define HS_C1_I0_A0_EP3_FIFO_MAP (((1 - HS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
- #define HS_C1_I0_A0_EP3_MAP (HS_C1_I0_A0_EP3_FIFO_START | (HS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP3_DIRECTION)))
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
- // EP4
- #define HS_C1_I0_A0_EP4_FIFO_START (HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO)
- #define HS_C1_I0_A0_EP4_FIFO_NO (HS_C1_I0_A0_EP4_BLKNO * HS_C1_I0_A0_EP4_BLKSIZE)
- #define HS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP4_BLKNO - 1) << 2) | HS_C1_I0_A0_EP4_TYPE)
- #define HS_C1_I0_A0_EP4_FIFO_MAP (((1 - HS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
- #define HS_C1_I0_A0_EP4_MAP (HS_C1_I0_A0_EP4_FIFO_START | (HS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP4_DIRECTION)))
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 5)
- // EP5
- #define HS_C1_I0_A0_EP5_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
- #define HS_C1_I0_A0_EP5_FIFO_NO (HS_C1_I0_A0_EP5_BLKNO * HS_C1_I0_A0_EP5_BLKSIZE)
- #define HS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP5_BLKNO - 1) << 2) | HS_C1_I0_A0_EP5_TYPE)
- #define HS_C1_I0_A0_EP5_FIFO_MAP (((1 - HS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
- #define HS_C1_I0_A0_EP5_MAP (HS_C1_I0_A0_EP5_FIFO_START | (HS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP5_DIRECTION)))
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 6)
- // EP5
- #define HS_C1_I0_A0_EP6_FIFO_START (HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO)
- #define HS_C1_I0_A0_EP6_FIFO_NO (HS_C1_I0_A0_EP6_BLKNO * HS_C1_I0_A0_EP6_BLKSIZE)
- #define HS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP6_BLKNO - 1) << 2) | HS_C1_I0_A0_EP6_TYPE)
- #define HS_C1_I0_A0_EP6_FIFO_MAP (((1 - HS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
- #define HS_C1_I0_A0_EP6_MAP (HS_C1_I0_A0_EP6_FIFO_START | (HS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP6_DIRECTION)))
- #endif
- #endif
-
- #if (HS_C1_I0_ALT_NUMBER >= 2)
- // AlternateSetting 1
- #define HS_C1_I0_A1_EP_LENGTH (EP_LENGTH * HS_C1_I0_A1_EP_NUMBER)
- #if (HS_C1_I0_A1_EP_NUMBER >= 1)
- // EP1
- #define HS_C1_I0_A1_EP1_FIFO_START FIFO0
- #define HS_C1_I0_A1_EP1_FIFO_NO (HS_C1_I0_A1_EP1_BLKNO * HS_C1_I0_A1_EP1_BLKSIZE)
- #define HS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP1_BLKNO - 1) << 2) | HS_C1_I0_A1_EP1_TYPE)
- #define HS_C1_I0_A1_EP1_FIFO_MAP (((1 - HS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
- #define HS_C1_I0_A1_EP1_MAP (HS_C1_I0_A1_EP1_FIFO_START | (HS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP1_DIRECTION)))
- #endif
- #if (HS_C1_I0_A1_EP_NUMBER >= 2)
- // EP2
- #define HS_C1_I0_A1_EP2_FIFO_START (HS_C1_I0_A1_EP1_FIFO_START + HS_C1_I0_A1_EP1_FIFO_NO)
- #define HS_C1_I0_A1_EP2_FIFO_NO (HS_C1_I0_A1_EP2_BLKNO * HS_C1_I0_A1_EP2_BLKSIZE)
- #define HS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP2_BLKNO - 1) << 2) | HS_C1_I0_A1_EP2_TYPE)
- #define HS_C1_I0_A1_EP2_FIFO_MAP (((1 - HS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
- #define HS_C1_I0_A1_EP2_MAP (HS_C1_I0_A1_EP2_FIFO_START | (HS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP2_DIRECTION)))
- #endif
- #if (HS_C1_I0_A1_EP_NUMBER >= 3)
- // EP3
- #define HS_C1_I0_A1_EP3_FIFO_START (HS_C1_I0_A1_EP2_FIFO_START + HS_C1_I0_A1_EP2_FIFO_NO)
- #define HS_C1_I0_A1_EP3_FIFO_NO (HS_C1_I0_A1_EP3_BLKNO * HS_C1_I0_A1_EP3_BLKSIZE)
- #define HS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP3_BLKNO - 1) << 2) | HS_C1_I0_A1_EP3_TYPE)
- #define HS_C1_I0_A1_EP3_FIFO_MAP (((1 - HS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
- #define HS_C1_I0_A1_EP3_MAP (HS_C1_I0_A1_EP3_FIFO_START | (HS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP3_DIRECTION)))
- #endif
- #endif
-
- #if (HS_C1_I0_ALT_NUMBER == 1)
- #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH)
- #elif (HS_C1_I0_ALT_NUMBER == 2)
- #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH + HS_C1_I0_A1_EP_LENGTH)
- #endif
- #endif
-
- #if (HS_C1_INTERFACE_NUMBER >= 2)
- // Interface 1
- #if (HS_C1_I1_ALT_NUMBER >= 1)
- // AlternateSetting 0
- #define HS_C1_I1_A0_EP_LENGTH (EP_LENGTH * HS_C1_I1_A0_EP_NUMBER)
- #if (HS_C1_I1_A0_EP_NUMBER >= 1)
- // EP1
- #define HS_C1_I1_A0_EP1_FIFO_START FIFO0
- #define HS_C1_I1_A0_EP1_FIFO_NO (HS_C1_I1_A0_EP1_BLKNO * HS_C1_I1_A0_EP1_BLKSIZE)
- #define HS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP1_BLKNO - 1) << 2) | HS_C1_I1_A0_EP1_TYPE)
- #define HS_C1_I1_A0_EP1_FIFO_MAP (((1 - HS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
- #define HS_C1_I1_A0_EP1_MAP (HS_C1_I1_A0_EP1_FIFO_START | (HS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP1_DIRECTION)))
- #endif
- #if (HS_C1_I1_A0_EP_NUMBER >= 2)
- // EP2
- #define HS_C1_I1_A0_EP2_FIFO_START (HS_C1_I1_A0_EP1_FIFO_START + HS_C1_I1_A0_EP1_FIFO_NO)
- #define HS_C1_I1_A0_EP2_FIFO_NO (HS_C1_I1_A0_EP2_BLKNO * HS_C1_I1_A0_EP2_BLKSIZE)
- #define HS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP2_BLKNO - 1) << 2) | HS_C1_I1_A0_EP2_TYPE)
- #define HS_C1_I1_A0_EP2_FIFO_MAP (((1 - HS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
- #define HS_C1_I1_A0_EP2_MAP (HS_C1_I1_A0_EP2_FIFO_START | (HS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP2_DIRECTION)))
- #endif
- #if (HS_C1_I1_A0_EP_NUMBER >= 3)
- // EP3
- #define HS_C1_I1_A0_EP3_FIFO_START (HS_C1_I1_A0_EP2_FIFO_START + HS_C1_I1_A0_EP2_FIFO_NO)
- #define HS_C1_I1_A0_EP3_FIFO_NO (HS_C1_I1_A0_EP3_BLKNO * HS_C1_I1_A0_EP3_BLKSIZE)
- #define HS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP3_BLKNO - 1) << 2) | HS_C1_I1_A0_EP3_TYPE)
- #define HS_C1_I1_A0_EP3_FIFO_MAP (((1 - HS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
- #define HS_C1_I1_A0_EP3_MAP (HS_C1_I1_A0_EP3_FIFO_START | (HS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP3_DIRECTION)))
- #endif
- #endif
-
- #if (HS_C1_I1_ALT_NUMBER >= 2)
- // AlternateSetting 1
- #define HS_C1_I1_A1_EP_LENGTH (EP_LENGTH * HS_C1_I1_A1_EP_NUMBER)
- #if (HS_C1_I1_A1_EP_NUMBER >= 1)
- // EP1
- #define HS_C1_I1_A1_EP1_FIFO_START FIFO0
- #define HS_C1_I1_A1_EP1_FIFO_NO (HS_C1_I1_A1_EP1_BLKNO * HS_C1_I1_A1_EP1_BLKSIZE)
- #define HS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP1_BLKNO - 1) << 2) | HS_C1_I1_A1_EP1_TYPE)
- #define HS_C1_I1_A1_EP1_FIFO_MAP (((1 - HS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
- #define HS_C1_I1_A1_EP1_MAP (HS_C1_I1_A1_EP1_FIFO_START | (HS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP1_DIRECTION)))
- #endif
- #if (HS_C1_I1_A1_EP_NUMBER >= 2)
- // EP2
- #define HS_C1_I1_A1_EP2_FIFO_START (HS_C1_I1_A1_EP1_FIFO_START + HS_C1_I1_A1_EP1_FIFO_NO)
- #define HS_C1_I1_A1_EP2_FIFO_NO (HS_C1_I1_A1_EP2_BLKNO * HS_C1_I1_A1_EP2_BLKSIZE)
- #define HS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP2_BLKNO - 1) << 2) | HS_C1_I1_A1_EP2_TYPE)
- #define HS_C1_I1_A1_EP2_FIFO_MAP (((1 - HS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
- #define HS_C1_I1_A1_EP2_MAP (HS_C1_I1_A1_EP2_FIFO_START | (HS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP2_DIRECTION)))
- #endif
- #if (HS_C1_I1_A1_EP_NUMBER >= 3)
- // EP3
- #define HS_C1_I1_A1_EP3_FIFO_START (HS_C1_I1_A1_EP2_FIFO_START + HS_C1_I1_A1_EP2_FIFO_NO)
- #define HS_C1_I1_A1_EP3_FIFO_NO (HS_C1_I1_A1_EP3_BLKNO * HS_C1_I1_A1_EP3_BLKSIZE)
- #define HS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP3_BLKNO - 1) << 2) | HS_C1_I1_A1_EP3_TYPE)
- #define HS_C1_I1_A1_EP3_FIFO_MAP (((1 - HS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
- #define HS_C1_I1_A1_EP3_MAP (HS_C1_I1_A1_EP3_FIFO_START | (HS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP3_DIRECTION)))
- #endif
- #endif
-
- #if (HS_C1_I1_ALT_NUMBER == 1)
- #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH)
- #elif (HS_C1_I1_ALT_NUMBER == 2)
- #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH + HS_C1_I1_A1_EP_LENGTH)
- #endif
- #endif
-
- #if (HS_C1_INTERFACE_NUMBER == 1)
- #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH)
- #elif (HS_C1_INTERFACE_NUMBER == 2)
- #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH + HS_C1_I1_ALT_LENGTH)
- #endif
-#endif
-
-#if (FS_CONFIGURATION_NUMBER >= 1)
- // Configuration 0X01
- #define FS_C1_INTERFACE_NUMBER 0X01
- #define FS_C1 0X01
- #define FS_C1_iConfiguration 0X00
- #define FS_C1_bmAttribute 0X80
- #define FS_C1_iMaxPower 0XFA
-
- #if (FS_C1_INTERFACE_NUMBER >= 1)
- // Interface 0
- #define FS_C1_I0_ALT_NUMBER 0X01
- #if (FS_C1_I0_ALT_NUMBER >= 1)
- // AlternateSetting 0X00
- #define FS_C1_I0_A0_bInterfaceNumber 0X00
- #define FS_C1_I0_A0_bAlternateSetting 0X00
- //JWEI 2003/07/14
- //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
- #define FS_C1_I0_A0_EP_NUMBER 0x05
- //#else
- //#define FS_C1_I0_A0_EP_NUMBER 0X03
- //#endif
- #if !(fFLASH_DISK && !fFLASH_BOOT)
- #define FS_C1_I0_A0_bInterfaceClass 0XFF
- #define FS_C1_I0_A0_bInterfaceSubClass 0X00
- #define FS_C1_I0_A0_bInterfaceProtocol 0X00
- #else
- #define FS_C1_I0_A0_bInterfaceClass 0X08
- #define FS_C1_I0_A0_bInterfaceSubClass 0X06
- #define FS_C1_I0_A0_bInterfaceProtocol 0X50
- #endif
- #define FS_C1_I0_A0_iInterface 0X00
-
- #if (FS_C1_I0_A0_EP_NUMBER >= 1)
- //EP0X01
- #define FS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE
- //JWEI 2003/05/19
- #if fDOUBLE_BUF
- #define FS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK
- #else
- #define FS_C1_I0_A0_EP1_BLKNO SINGLE_BLK
- #endif
- #define FS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT
- #define FS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK
- //JWEI 2003/05/07
- #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64
- #define FS_C1_I0_A0_EP1_bInterval 00
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 2)
- //EP0X02
- #define FS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE
- //JWEI 2003/08/20
- #if fDOUBLE_BUF_IN
- #define FS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK
- #else
- #define FS_C1_I0_A0_EP2_BLKNO SINGLE_BLK
- #endif
- #define FS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN
- #define FS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK
- #define FS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_64
- #define FS_C1_I0_A0_EP2_bInterval 00
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 3)
- //EP0X03
- #define FS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE
- #define FS_C1_I0_A0_EP3_BLKNO SINGLE_BLK
- #define FS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN
- #define FS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT
- #define FS_C1_I0_A0_EP3_MAX_PACKET 0x0040
- #define FS_C1_I0_A0_EP3_bInterval 01
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
- //EP0X04
- #define FS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE
- #define FS_C1_I0_A0_EP4_BLKNO SINGLE_BLK
- #define FS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT
- #define FS_C1_I0_A0_EP4_TYPE TF_TYPE_BULK
- #define FS_C1_I0_A0_EP4_MAX_PACKET 0x0040
- #define FS_C1_I0_A0_EP4_bInterval 00
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 5)
- //EP0X04
- #define FS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE
- #if fDOUBLE_BUF_IN
- #define FS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK
- #else
- #define FS_C1_I0_A0_EP5_BLKNO SINGLE_BLK
- #endif
- #define FS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT
- #define FS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK
- #define FS_C1_I0_A0_EP5_MAX_PACKET 0x0040
- #define FS_C1_I0_A0_EP5_bInterval 00
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 6)
- //EP0X04
- #define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE
- #if fDOUBLE_BUF_IN
- #define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK
- #else
- #define FS_C1_I0_A0_EP6_BLKNO SINGLE_BLK
- #endif
- #define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT
- #define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK
- #define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040
- #define FS_C1_I0_A0_EP6_bInterval 00
- #endif
- #endif
- #endif
-#endif
-
-#if (FS_CONFIGURATION_NUMBER >= 1)
- // Configuration 1
- #if (FS_C1_INTERFACE_NUMBER >= 1)
- // Interface 0
- #if (FS_C1_I0_ALT_NUMBER >= 1)
- // AlternateSetting 0
- #define FS_C1_I0_A0_EP_LENGTH (EP_LENGTH * FS_C1_I0_A0_EP_NUMBER)
- #if (FS_C1_I0_A0_EP_NUMBER >= 1)
- // EP1
- #define FS_C1_I0_A0_EP1_FIFO_START FIFO0
- #define FS_C1_I0_A0_EP1_FIFO_NO (FS_C1_I0_A0_EP1_BLKNO * FS_C1_I0_A0_EP1_BLKSIZE)
- #define FS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP1_BLKNO - 1) << 2) | FS_C1_I0_A0_EP1_TYPE)
- #define FS_C1_I0_A0_EP1_FIFO_MAP (((1 - FS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
- #define FS_C1_I0_A0_EP1_MAP (FS_C1_I0_A0_EP1_FIFO_START | (FS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP1_DIRECTION)))
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 2)
- // EP2
- #define FS_C1_I0_A0_EP2_FIFO_START (FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO)
- #define FS_C1_I0_A0_EP2_FIFO_NO (FS_C1_I0_A0_EP2_BLKNO * FS_C1_I0_A0_EP2_BLKSIZE)
- #define FS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP2_BLKNO - 1) << 2) | FS_C1_I0_A0_EP2_TYPE)
- #define FS_C1_I0_A0_EP2_FIFO_MAP (((1 - FS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
- #define FS_C1_I0_A0_EP2_MAP (FS_C1_I0_A0_EP2_FIFO_START | (FS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP2_DIRECTION)))
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 3)
- // EP3
- //JWEI 2003/07/15
- // #define FS_C1_I0_A0_EP3_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
- #define FS_C1_I0_A0_EP3_FIFO_START FIFO14
- #define FS_C1_I0_A0_EP3_FIFO_NO (FS_C1_I0_A0_EP3_BLKNO * FS_C1_I0_A0_EP3_BLKSIZE)
- #define FS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP3_BLKNO - 1) << 2) | FS_C1_I0_A0_EP3_TYPE)
- #define FS_C1_I0_A0_EP3_FIFO_MAP (((1 - FS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
- #define FS_C1_I0_A0_EP3_MAP (FS_C1_I0_A0_EP3_FIFO_START | (FS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP3_DIRECTION)))
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
- // EP4
- #define FS_C1_I0_A0_EP4_FIFO_START (FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO)
- #define FS_C1_I0_A0_EP4_FIFO_NO (FS_C1_I0_A0_EP4_BLKNO * FS_C1_I0_A0_EP4_BLKSIZE)
- #define FS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP4_BLKNO - 1) << 2) | FS_C1_I0_A0_EP4_TYPE)
- #define FS_C1_I0_A0_EP4_FIFO_MAP (((1 - FS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
- #define FS_C1_I0_A0_EP4_MAP (FS_C1_I0_A0_EP4_FIFO_START | (FS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP4_DIRECTION)))
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 5)
- // EP5
- #define FS_C1_I0_A0_EP5_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
- #define FS_C1_I0_A0_EP5_FIFO_NO (FS_C1_I0_A0_EP5_BLKNO * FS_C1_I0_A0_EP5_BLKSIZE)
- #define FS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP5_BLKNO - 1) << 2) | FS_C1_I0_A0_EP5_TYPE)
- #define FS_C1_I0_A0_EP5_FIFO_MAP (((1 - FS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
- #define FS_C1_I0_A0_EP5_MAP (FS_C1_I0_A0_EP5_FIFO_START | (FS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP5_DIRECTION)))
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 6)
- // EP5
- #define FS_C1_I0_A0_EP6_FIFO_START (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO)
- #define FS_C1_I0_A0_EP6_FIFO_NO (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE)
- #define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE)
- #define FS_C1_I0_A0_EP6_FIFO_MAP (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
- #define FS_C1_I0_A0_EP6_MAP (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION)))
- #endif
- #endif
-
- #if (FS_C1_I0_ALT_NUMBER >= 2)
- // AlternateSetting 1
- #define FS_C1_I0_A1_EP_LENGTH (EP_LENGTH * FS_C1_I0_A1_EP_NUMBER)
- #if (FS_C1_I0_A1_EP_NUMBER >= 1)
- // EP1
- #define FS_C1_I0_A1_EP1_FIFO_START FIFO0
- #define FS_C1_I0_A1_EP1_FIFO_NO (FS_C1_I0_A1_EP1_BLKNO * FS_C1_I0_A1_EP1_BLKSIZE)
- #define FS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP1_BLKNO - 1) << 2) | FS_C1_I0_A1_EP1_TYPE)
- #define FS_C1_I0_A1_EP1_FIFO_MAP (((1 - FS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
- #define FS_C1_I0_A1_EP1_MAP (FS_C1_I0_A1_EP1_FIFO_START | (FS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP1_DIRECTION)))
- #endif
- #if (FS_C1_I0_A1_EP_NUMBER >= 2)
- // EP2
- #define FS_C1_I0_A1_EP2_FIFO_START (FS_C1_I0_A1_EP1_FIFO_START + FS_C1_I0_A1_EP1_FIFO_NO)
- #define FS_C1_I0_A1_EP2_FIFO_NO (FS_C1_I0_A1_EP2_BLKNO * FS_C1_I0_A1_EP2_BLKSIZE)
- #define FS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP2_BLKNO - 1) << 2) | FS_C1_I0_A1_EP2_TYPE)
- #define FS_C1_I0_A1_EP2_FIFO_MAP (((1 - FS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
- #define FS_C1_I0_A1_EP2_MAP (FS_C1_I0_A1_EP2_FIFO_START | (FS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP2_DIRECTION)))
- #endif
- #if (FS_C1_I0_A1_EP_NUMBER >= 3)
- // EP3
- #define FS_C1_I0_A1_EP3_FIFO_START (FS_C1_I0_A1_EP2_FIFO_START + FS_C1_I0_A1_EP2_FIFO_NO)
- #define FS_C1_I0_A1_EP3_FIFO_NO (FS_C1_I0_A1_EP3_BLKNO * FS_C1_I0_A1_EP3_BLKSIZE)
- #define FS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP3_BLKNO - 1) << 2) | FS_C1_I0_A1_EP3_TYPE)
- #define FS_C1_I0_A1_EP3_FIFO_MAP (((1 - FS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
- #define FS_C1_I0_A1_EP3_MAP (FS_C1_I0_A1_EP3_FIFO_START | (FS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP3_DIRECTION)))
- #endif
- #endif
-
- #if (FS_C1_I0_ALT_NUMBER == 1)
- #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH)
- #elif (FS_C1_I0_ALT_NUMBER == 2)
- #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH + FS_C1_I0_A1_EP_LENGTH)
- #endif
- #endif
-
- #if (FS_C1_INTERFACE_NUMBER >= 2)
- // Interface 1
- #if (FS_C1_I1_ALT_NUMBER >= 1)
- // AlternateSetting 0
- #define FS_C1_I1_A0_EP_LENGTH (EP_LENGTH * FS_C1_I1_A0_EP_NUMBER)
- #if (FS_C1_I1_A0_EP_NUMBER >= 1)
- // EP1
- #define FS_C1_I1_A0_EP1_FIFO_START FIFO0
- #define FS_C1_I1_A0_EP1_FIFO_NO (FS_C1_I1_A0_EP1_BLKNO * FS_C1_I1_A0_EP1_BLKSIZE)
- #define FS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP1_BLKNO - 1) << 2) | FS_C1_I1_A0_EP1_TYPE)
- #define FS_C1_I1_A0_EP1_FIFO_MAP (((1 - FS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
- #define FS_C1_I1_A0_EP1_MAP (FS_C1_I1_A0_EP1_FIFO_START | (FS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP1_DIRECTION)))
- #endif
- #if (FS_C1_I1_A0_EP_NUMBER >= 2)
- // EP2
- #define FS_C1_I1_A0_EP2_FIFO_START (FS_C1_I1_A0_EP1_FIFO_START + FS_C1_I1_A0_EP1_FIFO_NO)
- #define FS_C1_I1_A0_EP2_FIFO_NO (FS_C1_I1_A0_EP2_BLKNO * FS_C1_I1_A0_EP2_BLKSIZE)
- #define FS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP2_BLKNO - 1) << 2) | FS_C1_I1_A0_EP2_TYPE)
- #define FS_C1_I1_A0_EP2_FIFO_MAP (((1 - FS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
- #define FS_C1_I1_A0_EP2_MAP (FS_C1_I1_A0_EP2_FIFO_START | (FS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP2_DIRECTION)))
- #endif
- #if (FS_C1_I1_A0_EP_NUMBER >= 3)
- // EP3
- #define FS_C1_I1_A0_EP3_FIFO_START (FS_C1_I1_A0_EP2_FIFO_START + FS_C1_I1_A0_EP2_FIFO_NO)
- #define FS_C1_I1_A0_EP3_FIFO_NO (FS_C1_I1_A0_EP3_BLKNO * FS_C1_I1_A0_EP3_BLKSIZE)
- #define FS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP3_BLKNO - 1) << 2) | FS_C1_I1_A0_EP3_TYPE)
- #define FS_C1_I1_A0_EP3_FIFO_MAP (((1 - FS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
- #define FS_C1_I1_A0_EP3_MAP (FS_C1_I1_A0_EP3_FIFO_START | (FS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP3_DIRECTION)))
- #endif
- #endif
-
- #if (FS_C1_I1_ALT_NUMBER >= 2)
- // AlternateSetting 1
- #define FS_C1_I1_A1_EP_LENGTH (EP_LENGTH * FS_C1_I1_A1_EP_NUMBER)
- #if (FS_C1_I1_A1_EP_NUMBER >= 1)
- // EP1
- #define FS_C1_I1_A1_EP1_FIFO_START FIFO0
- #define FS_C1_I1_A1_EP1_FIFO_NO (FS_C1_I1_A1_EP1_BLKNO * FS_C1_I1_A1_EP1_BLKSIZE)
- #define FS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP1_BLKNO - 1) << 2) | FS_C1_I1_A1_EP1_TYPE)
- #define FS_C1_I1_A1_EP1_FIFO_MAP (((1 - FS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
- #define FS_C1_I1_A1_EP1_MAP (FS_C1_I1_A1_EP1_FIFO_START | (FS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP1_DIRECTION)))
- #endif
- #if (FS_C1_I1_A1_EP_NUMBER >= 2)
- // EP2
- #define FS_C1_I1_A1_EP2_FIFO_START (FS_C1_I1_A1_EP1_FIFO_START + FS_C1_I1_A1_EP1_FIFO_NO)
- #define FS_C1_I1_A1_EP2_FIFO_NO (FS_C1_I1_A1_EP2_BLKNO * FS_C1_I1_A1_EP2_BLKSIZE)
- #define FS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP2_BLKNO - 1) << 2) | FS_C1_I1_A1_EP2_TYPE)
- #define FS_C1_I1_A1_EP2_FIFO_MAP (((1 - FS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
- #define FS_C1_I1_A1_EP2_MAP (FS_C1_I1_A1_EP2_FIFO_START | (FS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP2_DIRECTION)))
- #endif
- #if (FS_C1_I1_A1_EP_NUMBER >= 3)
- // EP3
- #define FS_C1_I1_A1_EP3_FIFO_START (FS_C1_I1_A1_EP2_FIFO_START + FS_C1_I1_A1_EP2_FIFO_NO)
- #define FS_C1_I1_A1_EP3_FIFO_NO (FS_C1_I1_A1_EP3_BLKNO * FS_C1_I1_A1_EP3_BLKSIZE)
- #define FS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP3_BLKNO - 1) << 2) | FS_C1_I1_A1_EP3_TYPE)
- #define FS_C1_I1_A1_EP3_FIFO_MAP (((1 - FS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
- #define FS_C1_I1_A1_EP3_MAP (FS_C1_I1_A1_EP3_FIFO_START | (FS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP3_DIRECTION)))
- #endif
- #endif
-
- #if (FS_C1_I1_ALT_NUMBER == 1)
- #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH)
- #elif (FS_C1_I1_ALT_NUMBER == 2)
- #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH + FS_C1_I1_A1_EP_LENGTH)
- #endif
- #endif
-
- #if (FS_C1_INTERFACE_NUMBER == 1)
- #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH)
- #elif (FS_C1_INTERFACE_NUMBER == 2)
- #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH + HS_FS_C1_I1_ALT_LENGTH)
- #endif
-#endif
-
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define USB_ENABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable
-
-#define USB_DISABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable
-
-#define USB_UP_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))) // upQ stream mode
-
-#define USB_UP_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3)) // upQ packet mode
-
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define USB_ENABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1)) // lp downstream DMA enable
-
-#define USB_DISABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))) // lp downstream DMA disable
-
-#define USB_LP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT6))) // lpQ packet mode
-
-#define USB_LP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6)) // lpQ stream mode
-
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable
-
-#define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable
-
-#define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7))) // hpQ packet mode
-
-#define USB_HP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7)) // hpQ stream mode
-
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable
-
-#define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable
-
-#define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10))) // hpQ packet mode
-
-#define USB_MP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10)) // hpQ stream mode
-
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define USB_ENABLE_UP_PACKET_MODE() USB_DISABLE_UP_DMA(); \
- USB_UP_PACKET_MODE(); \
- USB_ENABLE_UP_DMA();
-
-#define USB_ENABLE_LP_DN_PACKET_MODE() USB_DISABLE_LP_DN_DMA(); \
- USB_LP_DN_PACKET_MODE(); \
- USB_ENABLE_LP_DN_DMA()
-
-#define USB_ENABLE_MP_DN_PACKET_MODE() USB_DISABLE_MP_DN_DMA(); \
- USB_MP_DN_PACKET_MODE(); \
- USB_ENABLE_MP_DN_DMA();
-
-#define USB_ENABLE_HP_DN_PACKET_MODE() USB_DISABLE_HP_DN_DMA(); \
- USB_HP_DN_PACKET_MODE(); \
- USB_ENABLE_HP_DN_DMA();
-
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define USB_ENABLE_UP_STREAM_MODE() USB_DISABLE_UP_DMA(); \
- USB_UP_STREAM_MODE(); \
- USB_ENABLE_UP_DMA();
-
-#define USB_ENABLE_LP_DN_STREAM_MODE() USB_DISABLE_LP_DN_DMA(); \
- USB_LP_DN_STREAM_MODE(); \
- USB_ENABLE_LP_DN_DMA()
-
-#define USB_ENABLE_MP_DN_STREAM_MODE() USB_DISABLE_MP_DN_DMA(); \
- USB_MP_DN_STREAM_MODE(); \
- USB_ENABLE_MP_DN_DMA();
-
-#define USB_ENABLE_HP_DN_STREAM_MODE() USB_DISABLE_HP_DN_DMA(); \
- USB_HP_DN_STREAM_MODE(); \
- USB_ENABLE_HP_DN_DMA();
-
-#define USB_STREAM_HOST_BUF_SIZE(size) USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size)));
-#define USB_STREAM_TIMEOUT(time_cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt); // set stream mode timeout critirea
-#define USB_STREAM_AGG_PKT_CNT(cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea
-
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2013 Qualcomm Atheros, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted (subject to the limitations in the
- * disclaimer below) provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * * Neither the name of Qualcomm Atheros nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
- * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "usb_defs.h"
-#include "usb_type.h"
-#include "usb_pre.h"
-#include "usb_extr.h"
-#include "usb_std.h"
-#include "reg_defs.h"
-#include "athos_api.h"
-#include "usbfifo_api.h"
-
-
-#include "sys_cfg.h"
-
-typedef void (* USBFIFO_recv_command)(VBUF *cmd);
-void _fw_usb_suspend_reboot();
-
-extern Action eUsbCxFinishAction;
-extern CommandType eUsbCxCommand;
-extern BOOLEAN UsbChirpFinish;
-extern USB_FIFO_CONFIG usbFifoConf;
-
-USBFIFO_recv_command m_origUsbfifoRecvCmd = NULL;
-
-#if SYSTEM_MODULE_USB
-#define vUsb_ep0end(void) \
-{ \
- eUsbCxCommand = CMD_VOID; \
- USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); \
-}
-
-#define vUsb_ep0fail(void) USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04)
-
-#define vUsb_rst() \
-{ \
- USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
- (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT1)); \
- UsbChirpFinish = FALSE; \
-}
-
-#define vUsb_suspend() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
- (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT2))
-
-#define vUsb_resm() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
- (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT3))
-
-void _fw_usbfifo_recv_command(VBUF *buf)
-{
- A_UINT8 *cmd_data;
- A_UINT32 tmp;
-
- cmd_data = (A_UINT8 *)(buf->desc_list->buf_addr + buf->desc_list->data_offset);
- tmp = *((A_UINT32 *)cmd_data);
- if ( tmp == 0xFFFFFFFF ) {
- _fw_usb_suspend_reboot();
- } else {
- m_origUsbfifoRecvCmd(buf);
- }
-}
-
-void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig)
-{
- m_origUsbfifoRecvCmd = pConfig->recv_command;
-
- usbFifoConf.get_command_buf = pConfig->get_command_buf;
- usbFifoConf.recv_command = _fw_usbfifo_recv_command;
- usbFifoConf.get_event_buf = pConfig->get_event_buf;
- usbFifoConf.send_event_done = pConfig->send_event_done;
-}
-
-#define CHECK_SOF_LOOP_CNT 50
-
-void _fw_usb_suspend_reboot()
-{
- volatile uint32_t gpio_in = 0;
- volatile uint32_t pupd = 0;
- volatile uint32_t t = 0;
- volatile uint32_t sof_no=0,sof_no_new=0;
- /* Set GO_TO_SUSPEND bit to USB main control register */
- vUsb_suspend();
- A_PRINTF("!USB suspend\n\r");
-
- // keep the record of suspend
-#if defined(PROJECT_MAGPIE)
- *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = SUS_MAGIC_PATTERN;
-#elif defined(PROJECT_K2)
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
-#endif /* #if defined(PROJECT_MAGPIE) */
-
- /* Reset USB FIFO */
- A_USB_RESET_FIFO();
-
- /* Turn off power */
- A_USB_POWER_OFF();
-
- DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1000;
-
- // reset ep3/ep4 fifo in case there is data which might affect resuming
-// HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
-// HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10));
-
- {
- // config gpio to input before goto suspend
-
- //disable JTAG/ICE
- //jtag = HAL_WORD_REG_READ(0x10004054);
- //HAL_WORD_REG_WRITE(0x10004054, (jtag|BIT17));
-
- //disable SPI
- //spi = HAL_WORD_REG_READ(0x50040);
- //HAL_WORD_REG_WRITE(0x50040, (spi&~(BIT8)));
-
- //set all GPIO to input
- gpio_in = HAL_WORD_REG_READ(0x1000404c);
- HAL_WORD_REG_WRITE(0x1000404c, 0x0);
-
- //set PU/PD for all GPIO except two UART pins
- pupd = HAL_WORD_REG_READ(0x10004088);
- HAL_WORD_REG_WRITE(0x10004088, 0xA982AA6A);
- }
-
- sof_no= HAL_WORD_REG_READ(0x10004);
- for (t = 0; t < CHECK_SOF_LOOP_CNT; t++)
- {
- A_DELAY_USECS(1000); //delay 1ms
- sof_no_new = HAL_WORD_REG_READ(0x10004);
-
- if(sof_no_new == sof_no)
- break;
-
- sof_no = sof_no_new;
- }
-
- /*
- * Reset "printf" module patch point(RAM to ROM) when K2 warm start or suspend,
- * which fixed the error issue cause by redownload another different firmware.
- */
- _indir_tbl.cmnos.printf._printf = save_cmnos_printf;
-
- ///////////////////////////////////////////////////////////////
- // setting the go suspend here, power down right away...
- if (t != CHECK_SOF_LOOP_CNT) // not time out
- HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8));
- ///////////////////////////////////////////////////////////////
-
- DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1100;
-
-#if 0 // pll unstable, h/w bug?
- HAL_WORD_REG_WRITE(0x50040, (0x300|6|(1>>1)<<12));
- A_UART_HWINIT((40*1000*1000)/1, 19200);
-#endif
- {
- // restore gpio setting
- //HAL_WORD_REG_WRITE(0x10004054, jtag);
- //HAL_WORD_REG_WRITE(0x50040, spi);
- HAL_WORD_REG_WRITE(0x1000404c, gpio_in);
- HAL_WORD_REG_WRITE(0x10004088, pupd);
- }
- DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1200;
-
- {
- // since we still need to touch mac_base address after resuming back, so that
- // reset mac can't be done in ResetFifo function, move to here...
- // whole mac control reset.... (bit1)
- HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT1) );
- HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0));
- HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 );
- A_DELAY_USECS(1000);
- }
-
- //A_PRINTF("reg(0x10020)=(%x)\n", HAL_WORD_REG_READ(0x10020));
- // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!!
- mUSB_STATUS_IN_INT_DISABLE();
-
- MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
- MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
- MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
- MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
-
- if (((DEBUG_SYSTEM_STATE&~(0x0000ffff))>>16 == 0x5342)) {
- /* UART_SEL and SPI_SEL */
- HAL_WORD_REG_WRITE(0x50040, (0x300|0|(1>>1)<<12));
- }
-
- /* Jump to boot code */
- A_USB_JUMP_BOOT();
-
-}
-
-/*
- * -- patch usb_fw_task --
- * . usb zero length interrupt should not clear by s/w, h/w will handle that
- * . complete suspend handle, configure gpio, turn off related function,
- * slow down the pll for stable issue
- */
-void _fw_usb_fw_task(void)
-{
- register uint8_t usb_interrupt_level1;
- register uint8_t usb_interrupt_level2;
-
- usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET);
-#if 0 // these endpoints are handled by DMA
- if (usb_interrupt_level1 & BIT5) //Group Byte 5
- {
- vUsb_Data_In();
- }
-#endif
- if (usb_interrupt_level1 & BIT4)
- {
- usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_4_OFFSET);
- if( usb_interrupt_level2 & BIT6)
- A_USB_REG_OUT();//vUsb_Reg_Out();
- }
-
- if (usb_interrupt_level1 & BIT6)
- {
- //zfGenWatchDogEvent();
- usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_6_OFFSET);
- if( usb_interrupt_level2 & BIT6)
- A_USB_STATUS_IN();//vUsb_Status_In();
- }
-
- if (usb_interrupt_level1 & BIT0) //Group Byte 0
- {
- //usb_interrupt_level2 = ZM_INTR_SOURCE_0_REG;
- usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET);
-
- // refer to FUSB200, p 48, offset:21H, bit7 description, should clear the command abort interrupt first!?
- if (usb_interrupt_level2 & BIT7)
- {
- //ZM_INTR_SOURCE_0_REG &= 0x7f; // Handle command abort
- USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)& ~BIT7));
- A_PRINTF("![SOURCE_0] bit7 on\n\r");
- }
-
- if (usb_interrupt_level2 & BIT1)
- {
- //A_PRINTF("![USB] ep0 IN in \n\r");
- A_USB_EP0_TX(); // USB EP0 tx interrupt
- }
- if (usb_interrupt_level2 & BIT2)
- {
- //A_PRINTF("![USB] ep0 OUT in\n\r");
- A_USB_EP0_RX(); // USB EP0 rx interrupt
- }
- if (usb_interrupt_level2 & BIT0)
- {
- //A_PRINTF("![USB] ep0 SETUP in\n\r");
- A_USB_EP0_SETUP();
- //vWriteUSBFakeData();
- }
-// else if (usb_interrupt_level2 & BIT3)
- if (usb_interrupt_level2 & BIT3)
- {
- vUsb_ep0end();
-// A_PRINTF("![SOURCE_0] ep0 CMD_END\n\r");
- }
- if (usb_interrupt_level2 & BIT4)
- {
- vUsb_ep0fail();
-// A_PRINTF("![SOURCE_0] ep0 CMD_FAIL\n\r");
- }
- if (eUsbCxFinishAction == ACT_STALL)
- {
- // set CX_STL to stall Endpoint0 & will also clear FIFO0
- USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
-// A_PRINTF("![USB] ZM_CX_CONFIG_STATUS_REG = 0x04\n\r");
- }
- else if (eUsbCxFinishAction == ACT_DONE)
- {
- // set CX_DONE to indicate the transmistion of control frame
- USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
- }
- eUsbCxFinishAction = ACT_IDLE;
- }
-
- if (usb_interrupt_level1 & BIT7) //Group Byte 7
- {
- //usb_interrupt_level2 = ZM_INTR_SOURCE_7_REG;
- usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET);
-
-#if 0
- if (usb_interrupt_level2 & BIT7)
- {
- vUsb_Data_Out0Byte();
-// A_PRINTF("![SOURCE_7] bit7 on, clear it\n\r");
- }
- if (usb_interrupt_level2 & BIT6)
- {
- vUsb_Data_In0Byte();
-// A_PRINTF("![SOURCE_7] bit6 on, clear it\n\r");
- }
-#endif
-
- if (usb_interrupt_level2 & BIT1)
- {
- vUsb_rst();
- //USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~0x2));
- A_PRINTF("!USB reset\n\r");
-// A_PRINTF("![0x1012c]: %\n\r", USB_WORD_REG_READ(0x12c));
- }
- if (usb_interrupt_level2 & BIT2)
- {
- // TBD: the suspend resume code should put here, Ryan, 07/18
- //
- // issue, jump back to rom code and what peripherals should we reset here?
- //
- _fw_usb_suspend_reboot();
- }
- if (usb_interrupt_level2 & BIT3)
- {
- vUsb_resm();
- A_PRINTF("!USB resume\n\r");
- }
- }
-
-}
-
-
-void _fw_usb_reset_fifo(void)
-{
- volatile uint32_t *reg_data;
-
- HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
- HAL_BYTE_REG_WRITE(0x100af, (HAL_BYTE_REG_READ(0x100af)|0x10));
-
- // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!!
- mUSB_STATUS_IN_INT_DISABLE();
-
- // update magic pattern to indicate this is a suspend
- // k2: MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR
- // magpie: MAGPIE_REG_RST_STATUS_ADDR
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
-
- /*
- * Before USB suspend, USB DMA must be reset(refer to Otus)
- * Otus runs the following statements only
- * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0|BIT2 );
- * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 );
- * K2 must run the following statements additionally
- * reg_data = (A_UINT32 *)(USB_CTRL_BASE_ADDRESS + 0x118);
- * *reg_data = 0x00000000;
- * *reg_data = 0x00000001;
- * because of Hardware bug in K2
- */
- reg_data = (uint32_t *)(USB_CTRL_BASE_ADDRESS + 0x118);
- *reg_data = 0x00000000;
-
- // reset both usb(bit2)/wlan(bit1) dma
- HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT2) );
- HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0));
- HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 );
-
- *reg_data = 0x00000001;
-
- /* MAC warem reset */
- //reg_data = (uint32_t *)(K2_REG_MAC_BASE_ADDR + 0x7000);
- //*reg_data = 0x00000001;
-
- //A_DELAY_USECS(1);
-
- //*reg_data = 0x00000000;
-
- //while (*reg_data) ;
-
- A_PRINTF("\n change clock to 22 and go to suspend now!");
-
- /* UART_SEL */
- HAL_WORD_REG_WRITE(0x50040, (0x200|0|(1>>1)<<12));
- A_UART_HWINIT((22*1000*1000), 19200);
-}
-
-void cold_reboot(void)
-{
- A_PRINTF("Cold reboot initiated.");
-#if defined(PROJECT_MAGPIE)
- HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, 0);
-#elif defined(PROJECT_K2)
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, 0);
-#endif /* #if defined(PROJECT_MAGPIE) */
- A_USB_JUMP_BOOT();
-}
-
-/*
- * -- support more than 64 bytes command on ep4 --
- */
-void vUsb_Reg_Out_patch(void)
-{
- uint16_t usbfifolen;
- uint16_t ii;
- uint32_t ep4_data;
- static volatile uint32_t *regaddr; // = (volatile uint32_t *) ZM_CMD_BUFFER;
- static uint16_t cmdLen;
- static VBUF *buf;
- BOOLEAN cmd_is_last = FALSE;
- static BOOLEAN cmd_is_new = TRUE;
-
- // get the size of this transcation
- usbfifolen = USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_LOW_OFFSET);
- if (usbfifolen > 0x40) {
- A_PRINTF("EP4 FIFO Bug? Buffer is too big: %x\n", usbfifolen);
- cold_reboot();
- }
-
- // check is command is new
- if( cmd_is_new ){
-
- buf = usbFifoConf.get_command_buf();
- cmdLen = 0;
-
- if( !buf )
- goto ERR;
-
- // copy free, assignment buffer of the address
- regaddr = (uint32_t *)buf->desc_list->buf_addr;
-
- cmd_is_new = FALSE;
- }
-
- // just in case, suppose should not happen
- if( !buf )
- goto ERR;
-
- // if size is smaller, this is the last command!
- //
- // zero-length supposed should be set through 0x27/bit7->0x19/bit4, not here
- //
- if( usbfifolen<bUSB_EP_MAX_PKT_SIZE_64 ) {
- cmd_is_last = TRUE;
- }
-
- // accumulate the size
- cmdLen += usbfifolen;
- if (cmdLen > buf->desc_list->buf_size) {
- A_PRINTF("Data length on EP4 FIFO is bigger as allocated buffer data!"
- " Drop it!\n");
- goto ERR;
- }
-
- // round it to alignment
- if(usbfifolen % 4)
- usbfifolen = (usbfifolen >> 2) + 1;
- else
- usbfifolen = usbfifolen >> 2;
-
-// A_PRINTF("copy data out from fifo to - %p\n\r", regaddr);
- // retrieve the data from fifo
- for(ii = 0; ii < usbfifolen; ii++)
- {
- ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out
- *regaddr = ep4_data;
- regaddr++;
- }
-
- // if this is the last command, callback to HTC
- if ( cmd_is_last )
- {
- buf->desc_list->next_desc = NULL;
- buf->desc_list->data_offset = 0;
- buf->desc_list->data_size = cmdLen;
- buf->desc_list->control = 0;
- buf->next_buf = NULL;
- buf->buf_length = cmdLen;
-
- usbFifoConf.recv_command(buf);
-
- cmd_is_new = TRUE;
- }
-
- goto DONE;
-ERR:
-// we might get no command buffer here?
-// but if we return here, the ep4 fifo will be lock out,
-// so that we still read them out but just drop it ?
- for(ii = 0; ii < usbfifolen; ii++)
- {
- ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out
- }
-
-DONE:
- //mUSB_STATUS_IN_INT_ENABLE();
- ;
-}
-
-
-
-/*
- * -- usb1.1 ep6 fix --
- */
-extern uint16_t u8UsbConfigValue;
-extern uint16_t u8UsbInterfaceValue;
-extern uint16_t u8UsbInterfaceAlternateSetting;
-extern SetupPacket ControlCmd;
-extern void vUsbClrEPx(void);
-
-void vUSBFIFO_EP6Cfg_FS_patch(void)
-{
-#if (FS_C1_I0_A0_EP_NUMBER >= 6)
- int i;
-
- //EP0X06
- mUsbEPMap(EP6, FS_C1_I0_A0_EP6_MAP);
- mUsbFIFOMap(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_MAP);
- mUsbFIFOConfig(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_CONFIG);
-
- for(i = FS_C1_I0_A0_EP6_FIFO_START + 1 ;
- i < FS_C1_I0_A0_EP6_FIFO_START + FS_C1_I0_A0_EP6_FIFO_NO ; i ++)
- {
- mUsbFIFOConfig(i, (FS_C1_I0_A0_EP6_FIFO_CONFIG & (~BIT7)) );
- }
-
- mUsbEPMxPtSzHigh(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff));
- mUsbEPMxPtSzLow(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff));
- mUsbEPinHighBandSet(EP6 , FS_C1_I0_A0_EP6_DIRECTION, FS_C1_I0_A0_EP6_MAX_PACKET);
-#endif
-}
-
-void vUsbFIFO_EPxCfg_FS_patch(void)
-{
- switch (u8UsbConfigValue)
- {
- #if (FS_CONFIGURATION_NUMBER >= 1)
- // Configuration 0X01
- case 0X01:
- switch (u8UsbInterfaceValue)
- {
- #if (FS_C1_INTERFACE_NUMBER >= 1)
- // Interface 0
- case 0:
- switch (u8UsbInterfaceAlternateSetting)
- {
-
- #if (FS_C1_I0_ALT_NUMBER >= 1)
- // AlternateSetting 0
- case 0:
-
- // snapped....
-
- // patch up this ep6_fs config
- vUSBFIFO_EP6Cfg_FS_patch();
-
- break;
-
- #endif
- default:
- break;
- }
- break;
- #endif
- default:
- break;
- }
- break;
- #endif
- default:
- break;
- }
- //mCHECK_STACK();
-}
-
-
-BOOLEAN bSet_configuration_patch(void)
-{
- //A_PRINTF("bSet_configuration...\n\r");
-
- bSet_configuration();
-
- if (mLOW_BYTE(mDEV_REQ_VALUE()) == 0)
- {
- // snapped....
- ;
- }
- else
- {
- if (mUsbHighSpeedST()) // First judge HS or FS??
- {
- // snapped....
- ;
- }
- else
- {
- // snapped....
- vUsbFIFO_EPxCfg_FS_patch();
- }
-
- // snapped....
- }
-
- eUsbCxFinishAction = ACT_DONE;
- return TRUE;
-}
-
-
-/*
- * -- support more than 64 bytes command on ep3 --
- */
-void vUsb_Status_In_patch(void)
-{
- uint16_t count;
- uint16_t remainder;
- u16_t RegBufLen;
- BOOLEAN cmdEnd = FALSE;
-
- static u16_t mBufLen;
- static VBUF *evntbuf = NULL;
- static volatile u32_t *regaddr;
- static BOOLEAN cmd_is_new = TRUE;
-
- if( cmd_is_new )
- {
- evntbuf = usbFifoConf.get_event_buf();
- if ( evntbuf != NULL )
- {
- regaddr = (u32_t *)VBUF_GET_DATA_ADDR(evntbuf);
- mBufLen = evntbuf->buf_length;
- }
- else
- {
- mUSB_STATUS_IN_INT_DISABLE();
- goto ERR_DONE;
- }
-
- }
-
-// if( mBufLen>bUSB_EP_MAX_PKT_SIZE_64 )
-// A_PRINTF("EP3 send %d bytes to host \n", mBufLen);
-
-// while(1)
- {
- if( mBufLen > bUSB_EP_MAX_PKT_SIZE_64 ) {
- RegBufLen = bUSB_EP_MAX_PKT_SIZE_64;
- mBufLen -= bUSB_EP_MAX_PKT_SIZE_64;
- }
- // TODO: 64 byes... controller supposed will take care of zero-length?
- else {
- RegBufLen = mBufLen;
- cmdEnd = TRUE;
- }
-
- /* INT use EP3 */
- for(count = 0; count < (RegBufLen / 4); count++)
- {
- USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
- regaddr++;
- }
-
- remainder = RegBufLen % 4;
-
- if (remainder)
- {
- switch(remainder)
- {
- case 3:
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
- break;
- case 2:
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
- break;
- case 1:
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
- break;
- }
-
- USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
-
- // Restore CBus FIFO size to word size
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
- }
-
- mUSB_EP3_XFER_DONE();
-
-// if( mBufLen<=bUSB_EP_MAX_PKT_SIZE_64 )
-// break;
- }
-
- if ( evntbuf != NULL && cmdEnd )
- {
- usbFifoConf.send_event_done(evntbuf);
- cmd_is_new = TRUE;
- }
-
-ERR_DONE:
- ;
-}
-
-extern uint16_t *u8UsbDeviceDescriptor;
-extern uint16_t *u8ConfigDescriptorEX;
-extern uint16_t *pu8DescriptorEX;
-extern uint16_t u16TxRxCounter;
-extern BOOLEAN bGet_descriptor(void);
-
-uint16_t DeviceDescriptorPatch[9];
-uint16_t ConfigDescriptorPatch[30];
-
-
-#define BCD_DEVICE 6
-#define BCD_DEVICE_FW_SIGNATURE 0xffff
-#define EP3_TRANSFER_TYPE_OFFSET 17
-#define EP3_INT_INTERVAL 19
-#define EP4_TRANSFER_TYPE_OFFSET 21
-#define EP4_INT_INTERVAL 22
-
-BOOLEAN bGet_descriptor_patch(void)
-{
- int i;
- switch (mDEV_REQ_VALUE_HIGH()) {
- case 1:
- ath_hal_memcpy(DeviceDescriptorPatch,
- u8UsbDeviceDescriptor, sizeof(DeviceDescriptorPatch));
-
- DeviceDescriptorPatch[BCD_DEVICE] = BCD_DEVICE_FW_SIGNATURE;
-
- pu8DescriptorEX = DeviceDescriptorPatch;
- u16TxRxCounter = mTABLE_LEN(DeviceDescriptorPatch[0]);
- break;
- case 2:
- /* Copy ConfigDescriptor */
- ath_hal_memcpy(ConfigDescriptorPatch,
- u8ConfigDescriptorEX, sizeof(ConfigDescriptorPatch));
-
- /* place holder for EPx patches */
-
- switch (mDEV_REQ_VALUE_LOW())
- {
- case 0x00: // configuration no: 0
- pu8DescriptorEX = ConfigDescriptorPatch;
- u16TxRxCounter = ConfigDescriptorPatch[1];
- //u16TxRxCounter = 46;
- break;
- default:
- return FALSE;
- }
- break;
- default:
- return bGet_descriptor();
- }
-
- if (u16TxRxCounter > mDEV_REQ_LENGTH())
- u16TxRxCounter = mDEV_REQ_LENGTH();
-
- A_USB_EP0_TX_DATA();
- return TRUE;
-}
-
-extern BOOLEAN bStandardCommand(void);
-
-BOOLEAN bStandardCommand_patch(void)
-{
- if (mDEV_REQ_REQ() == USB_SET_CONFIGURATION) {
- A_USB_SET_CONFIG();
-
-#if ENABLE_SWAP_DATA_MODE
- // SWAP FUNCTION should be enabled while DMA engine is not working,
- // the best place to enable it is before we trigger the DMA
- MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
- MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
-
- #if SYSTEM_MODULE_HP_EP5
- MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
- #endif
-
- #if SYSTEM_MODULE_HP_EP6
- MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
- #endif
-
-#endif //ENABLE_SWAP_DATA_MODE
- return TRUE;
- }
- else {
- return bStandardCommand();
- }
-}
-
-#endif
-
-
--- /dev/null
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Qualcomm Atheros nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "usb_defs.h"
+#include "usb_type.h"
+#include "usb_pre.h"
+#include "usb_extr.h"
+#include "usb_std.h"
+#include "reg_defs.h"
+#include "athos_api.h"
+#include "usbfifo_api.h"
+
+
+#include "sys_cfg.h"
+
+void _fw_usb_suspend_reboot();
+
+extern Action eUsbCxFinishAction;
+extern CommandType eUsbCxCommand;
+extern BOOLEAN UsbChirpFinish;
+extern USB_FIFO_CONFIG usbFifoConf;
+
+#if SYSTEM_MODULE_USB
+#define vUsb_ep0end(void) \
+{ \
+ eUsbCxCommand = CMD_VOID; \
+ USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); \
+}
+
+#define vUsb_ep0fail(void) USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04)
+
+#define vUsb_rst() \
+{ \
+ USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
+ (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT1)); \
+ UsbChirpFinish = FALSE; \
+}
+
+#define vUsb_suspend() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
+ (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT2))
+
+#define vUsb_resm() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
+ (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT3))
+
+#define CHECK_SOF_LOOP_CNT 50
+
+void _fw_usb_suspend_reboot()
+{
+ volatile uint32_t gpio_in = 0;
+ volatile uint32_t pupd = 0;
+ volatile uint32_t t = 0;
+ volatile uint32_t sof_no=0,sof_no_new=0;
+ /* Set GO_TO_SUSPEND bit to USB main control register */
+ vUsb_suspend();
+ A_PRINTF("!USB suspend\n\r");
+
+ /* keep the record of suspend */
+#if defined(PROJECT_MAGPIE)
+ *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = SUS_MAGIC_PATTERN;
+#elif defined(PROJECT_K2)
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
+#endif /* #if defined(PROJECT_MAGPIE) */
+
+ /* Reset USB FIFO */
+ A_USB_RESET_FIFO();
+
+ /* Turn off power */
+ A_USB_POWER_OFF();
+
+ DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1000;
+
+ /* reset ep3/ep4 fifo in case there
+ * is data which might affect resuming */
+// HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
+// HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10));
+
+ {
+ /* config gpio to input before goto suspend */
+
+ /* disable JTAG/ICE */
+ //jtag = HAL_WORD_REG_READ(0x10004054);
+ //HAL_WORD_REG_WRITE(0x10004054, (jtag|BIT17));
+
+ /* disable SPI */
+ //spi = HAL_WORD_REG_READ(0x50040);
+ //HAL_WORD_REG_WRITE(0x50040, (spi&~(BIT8)));
+
+ /* set all GPIO to input */
+ gpio_in = HAL_WORD_REG_READ(0x1000404c);
+ HAL_WORD_REG_WRITE(0x1000404c, 0x0);
+
+ /* set PU/PD for all GPIO except two UART pins */
+ pupd = HAL_WORD_REG_READ(0x10004088);
+ HAL_WORD_REG_WRITE(0x10004088, 0xA982AA6A);
+ }
+
+ sof_no= HAL_WORD_REG_READ(0x10004);
+ for (t = 0; t < CHECK_SOF_LOOP_CNT; t++)
+ {
+ A_DELAY_USECS(1000); /* delay 1ms */
+ sof_no_new = HAL_WORD_REG_READ(0x10004);
+
+ if(sof_no_new == sof_no)
+ break;
+ sof_no = sof_no_new;
+ }
+
+ /*
+ * Reset "printf" module patch point(RAM to ROM)
+ * when K2 warm start or suspend,
+ * which fixed the error issue cause by redownload
+ * another different firmware.
+ */
+ _indir_tbl.cmnos.printf._printf = save_cmnos_printf;
+
+ /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+ * setting the go suspend here, power down right away!!!
+ */
+ if (t != CHECK_SOF_LOOP_CNT) /* not time out */
+ HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8));
+
+ DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1100;
+
+#if 0 /* pll unstable, h/w bug? */
+ HAL_WORD_REG_WRITE(0x50040, (0x300|6|(1>>1)<<12));
+ A_UART_HWINIT((40*1000*1000)/1, 19200);
+#endif
+ /* restore gpio setting */
+ //HAL_WORD_REG_WRITE(0x10004054, jtag);
+ //HAL_WORD_REG_WRITE(0x50040, spi);
+ HAL_WORD_REG_WRITE(0x1000404c, gpio_in);
+ HAL_WORD_REG_WRITE(0x10004088, pupd);
+
+ DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1200;
+
+ /* since we still need to touch mac_base address after resuming back,
+ * so that reset mac can't be done in ResetFifo function,
+ * move to here... whole mac control reset.... (bit1)
+ */
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT1));
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR,
+ (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0));
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+ A_DELAY_USECS(1000);
+
+ //A_PRINTF("reg(0x10020)=(%x)\n", HAL_WORD_REG_READ(0x10020));
+ /* disable ep3 int enable, so that resume back won't
+ * send wdt magic pattern out!!! */
+ mUSB_STATUS_IN_INT_DISABLE();
+
+ MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
+ MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
+ MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
+ MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
+
+ if (((DEBUG_SYSTEM_STATE&~(0x0000ffff))>>16 == 0x5342)) {
+ /* UART_SEL and SPI_SEL */
+ HAL_WORD_REG_WRITE(0x50040, (0x300|0|(1>>1)<<12));
+ }
+
+ /* Jump to boot code */
+ A_USB_JUMP_BOOT();
+}
+
+/*
+ * patch usb_fw_task
+ * usb zero length interrupt should not clear by s/w, h/w will handle that
+ * complete suspend handle, configure gpio, turn off related function,
+ * slow down the pll for stable issue
+ */
+void _fw_usb_fw_task(void)
+{
+ register uint8_t usb_interrupt_level1;
+ register uint8_t usb_interrupt_level2;
+
+ usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET);
+#if 0 /* these endpoints are handled by DMA */
+ if (usb_interrupt_level1 & BIT5)
+ {
+ vUsb_Data_In();
+ }
+#endif
+ if (usb_interrupt_level1 & BIT4) {
+ usb_interrupt_level2 =
+ USB_BYTE_REG_READ(ZM_INTR_SOURCE_4_OFFSET);
+
+ if(usb_interrupt_level2 & BIT6)
+ A_USB_REG_OUT(); /* vUsb_Reg_Out() */
+ }
+
+ if (usb_interrupt_level1 & BIT6) {
+ /* zfGenWatchDogEvent(); ?? */
+ usb_interrupt_level2 =
+ USB_BYTE_REG_READ(ZM_INTR_SOURCE_6_OFFSET);
+ if(usb_interrupt_level2 & BIT6)
+ A_USB_STATUS_IN(); /* vUsb_Status_In() */
+ }
+
+ if (usb_interrupt_level1 & BIT0) {
+ usb_interrupt_level2 =
+ USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET);
+
+ /* refer to FUSB200, p 48, offset:21H, bit7 description,
+ * should clear the command abort interrupt first!?
+ */
+ if (usb_interrupt_level2 & BIT7) {
+ /* Handle command abort */
+ USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET,
+ (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)
+ & ~BIT7));
+ A_PRINTF("![SOURCE_0] bit7 on\n\r");
+ }
+
+ if (usb_interrupt_level2 & BIT1)
+ A_USB_EP0_TX(); /* USB EP0 tx interrupt */
+
+ if (usb_interrupt_level2 & BIT2)
+ A_USB_EP0_RX(); /* USB EP0 rx interrupt */
+
+ if (usb_interrupt_level2 & BIT0) {
+ A_USB_EP0_SETUP();
+ /* vWriteUSBFakeData() */
+ }
+
+ if (usb_interrupt_level2 & BIT3)
+ vUsb_ep0end();
+
+ if (usb_interrupt_level2 & BIT4)
+ vUsb_ep0fail();
+
+ if (eUsbCxFinishAction == ACT_STALL) {
+ /* set CX_STL to stall Endpoint0 &
+ * will also clear FIFO0 */
+ USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
+ } else if (eUsbCxFinishAction == ACT_DONE) {
+ /* set CX_DONE to indicate the transmistion
+ * of control frame */
+ USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
+ }
+ eUsbCxFinishAction = ACT_IDLE;
+ }
+
+ if (usb_interrupt_level1 & BIT7) {
+ usb_interrupt_level2 =
+ USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET);
+
+#if 0
+ if (usb_interrupt_level2 & BIT7)
+ vUsb_Data_Out0Byte();
+
+ if (usb_interrupt_level2 & BIT6)
+ vUsb_Data_In0Byte();
+#endif
+
+ if (usb_interrupt_level2 & BIT1) {
+ vUsb_rst();
+ A_PRINTF("!USB reset\n\r");
+// A_PRINTF("![0x1012c]: %\n\r", USB_WORD_REG_READ(0x12c));
+ }
+ if (usb_interrupt_level2 & BIT2) {
+ /* TBD: the suspend resume code should put here,
+ * Ryan, 07/18
+ * issue, jump back to rom code and what peripherals
+ * should we reset here? */
+ _fw_usb_suspend_reboot();
+ }
+ if (usb_interrupt_level2 & BIT3) {
+ vUsb_resm();
+ A_PRINTF("!USB resume\n\r");
+ }
+ }
+}
+
+
+void _fw_usb_reset_fifo(void)
+{
+ volatile uint32_t *reg_data;
+
+ HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
+ HAL_BYTE_REG_WRITE(0x100af, (HAL_BYTE_REG_READ(0x100af)|0x10));
+
+ /* disable ep3 int enable, so that resume back won't
+ * send wdt magic pattern out!!!
+ */
+ mUSB_STATUS_IN_INT_DISABLE();
+
+ /* update magic pattern to indicate this is a suspend
+ * k2: MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR
+ * magpie: MAGPIE_REG_RST_STATUS_ADDR
+ */
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
+
+ /*
+ * Before USB suspend, USB DMA must be reset(refer to Otus)
+ * Otus runs the following statements only
+ * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0|BIT2 );
+ * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 );
+ * K2 must run the following statements additionally
+ * reg_data = (A_UINT32 *)(USB_CTRL_BASE_ADDRESS + 0x118);
+ * *reg_data = 0x00000000;
+ * *reg_data = 0x00000001;
+ * because of Hardware bug in K2
+ */
+ USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0);
+
+ /* reset both usb(bit2)/wlan(bit1) dma */
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT2));
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR,
+ (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0));
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+
+ USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0);
+
+ /* MAC warem reset */
+ //reg_data = (uint32_t *)(K2_REG_MAC_BASE_ADDR + 0x7000);
+ //*reg_data = 0x00000001;
+
+ //A_DELAY_USECS(1);
+
+ //*reg_data = 0x00000000;
+
+ //while (*reg_data) ;
+
+ A_PRINTF("\n change clock to 22 and go to suspend now!");
+
+ /* UART_SEL */
+ HAL_WORD_REG_WRITE(0x50040, (0x200|0|(1>>1)<<12));
+ A_UART_HWINIT((22*1000*1000), 19200);
+}
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Qualcomm Atheros nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "usb_defs.h"
+#include "usb_type.h"
+#include "usb_pre.h"
+#include "usb_extr.h"
+#include "usb_std.h"
+#include "reg_defs.h"
+#include "athos_api.h"
+#include "usbfifo_api.h"
+
+#include "sys_cfg.h"
+
+#define measure_time 0
+#define measure_time_pll 10000000
+
+extern Action eUsbCxFinishAction;
+extern CommandType eUsbCxCommand;
+extern BOOLEAN UsbChirpFinish;
+extern USB_FIFO_CONFIG usbFifoConf;
+extern uint16_t *pu8DescriptorEX;
+extern uint16_t u16TxRxCounter;
+
+void zfTurnOffPower_patch(void);
+
+static void _fw_reset_dma_fifo();
+static void _fw_restore_dma_fifo();
+static void _fw_power_on();
+static void _fw_power_off();
+
+BOOLEAN bEepromExist = TRUE;
+BOOLEAN bJumptoFlash = FALSE;
+
+void _fw_usb_suspend_reboot()
+{
+ /* reset usb/wlan dma */
+ _fw_reset_dma_fifo();
+
+ /* restore gpio setting and usb/wlan dma state */
+ _fw_restore_dma_fifo();
+
+ /* set clock to bypass mode - 40Mhz from XTAL */
+ HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4));
+
+ A_DELAY_USECS(100); /* wait for stable */
+
+ HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));
+
+ A_DELAY_USECS(100); /* wait for stable */
+ A_UART_HWINIT((40*1000*1000), 19200);
+
+ A_CLOCK_INIT(40);
+
+ if (!bEepromExist) { /* jump to flash boot (eeprom data in flash) */
+ bJumptoFlash = TRUE;
+ A_PRINTF("Jump to Flash BOOT\n");
+ app_start();
+ } else {
+ A_PRINTF("receive the suspend command...\n");
+ /* reboot..... */
+ A_USB_JUMP_BOOT();
+ }
+
+}
+
+#define PCI_RC_RESET_BIT BIT6
+#define PCI_RC_PHY_RESET_BIT BIT7
+#define PCI_RC_PLL_RESET_BIT BIT8
+#define PCI_RC_PHY_SHIFT_RESET_BIT BIT10
+
+/*
+ * -- urn_off_merlin --
+ * . values suggested from Lalit
+ *
+ */
+static void turn_off_merlin()
+{
+ volatile uint32_t default_data[9];
+ uint32_t i=0;
+
+ if(1)
+ {
+ A_PRINTF("turn_off_merlin_ep_start ......\n");
+ A_DELAY_USECS(measure_time);
+ default_data[0] = 0x9248fd00;
+ default_data[1] = 0x24924924;
+ default_data[2] = 0xa8000019;
+ default_data[3] = 0x17160820;
+ default_data[4] = 0x25980560;
+ default_data[5] = 0xc1c00000;
+ default_data[6] = 0x1aaabe40;
+ default_data[7] = 0xbe105554;
+ default_data[8] = 0x00043007;
+
+ for(i=0; i<9; i++)
+ {
+ A_DELAY_USECS(10);
+
+ HAL_WORD_REG_WRITE( 0x10ff4040, default_data[i]);
+ }
+ A_DELAY_USECS(10);
+ HAL_WORD_REG_WRITE(0x10ff4044, BIT0);
+ A_PRINTF("turn_off_merlin_ep_end ......\n");
+ }
+}
+
+/*
+ * -- turn_off_phy --
+ *
+ * . write shift register to both pcie ep and rc
+ * .
+ */
+
+static void turn_off_phy()
+{
+
+ volatile uint32_t default_data[9];
+ volatile uint32_t read_data = 0;
+ uint32_t i=0;
+
+ default_data[0] = 0x9248fd00;
+ default_data[1] = 0x24924924;
+ default_data[2] = 0xa8000019;
+ default_data[3] = 0x17160820;
+ default_data[4] = 0x25980560;
+ default_data[5] = 0xc1c00000;
+ default_data[6] = 0x1aaabe40;
+ default_data[7] = 0xbe105554;
+ default_data[8] = 0x00043007;
+
+ for(i=0; i<9; i++)
+ {
+ // check for the done bit to be set
+
+ while (1)
+ {
+ read_data=HAL_WORD_REG_READ(0x40028);
+ if( read_data & BIT31 )
+ break;
+ }
+
+ A_DELAY_USECS(1);
+
+ HAL_WORD_REG_WRITE( 0x40024, default_data[i]);
+ }
+ HAL_WORD_REG_WRITE(0x40028, BIT0);
+}
+
+static void turn_off_phy_rc()
+{
+
+ volatile uint32_t default_data[9];
+ volatile uint32_t read_data = 0;
+ uint32_t i=0;
+
+ A_PRINTF("turn_off_phy_rc\n");
+
+ default_data[0] = 0x9248fd00;
+ default_data[1] = 0x24924924;
+ default_data[2] = 0xa8000019;
+ default_data[3] = 0x13160820;//PwdClk1MHz=0
+ default_data[4] = 0x25980560;
+ default_data[5] = 0xc1c00000;
+ default_data[6] = 0x1aaabe40;
+ default_data[7] = 0xbe105554;
+ default_data[8] = 0x00043007;
+
+ for(i=0; i<9; i++)
+ {
+ // check for the done bit to be set
+
+ while (1)
+ {
+ read_data=HAL_WORD_REG_READ(0x40028);
+ if( read_data & BIT31 )
+ break;
+ }
+
+ A_DELAY_USECS(1);
+
+ HAL_WORD_REG_WRITE( 0x40024, default_data[i]);
+ }
+ HAL_WORD_REG_WRITE(0x40028, BIT0);
+}
+
+volatile uint32_t gpio_func = 0x0;
+volatile uint32_t gpio = 0x0;
+
+/*
+ * -- patch zfTurnOffPower --
+ *
+ * . set suspend counter to non-zero value
+ * .
+ */
+void zfTurnOffPower_patch(void)
+{
+ A_PRINTF("+++ goto suspend ......\n");
+
+ // setting the go suspend here, power down right away...
+ HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8));
+
+ A_DELAY_USECS(100);
+
+ // TURN OFF ETH PLL
+ _fw_power_off();
+
+ //32clk wait for External ETH PLL stable
+ A_DELAY_USECS(100);
+
+ HAL_WORD_REG_WRITE(0x52000, 0x70303);//read back 0x703f7
+ HAL_WORD_REG_WRITE(0x52008, 0x0e91c);//read back 0x1e948
+
+ HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
+ (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(BIT0))); //0x56030
+ // wake up, and turn on cpu, eth, pcie and usb pll
+ _fw_power_on();
+ // restore gpio and other settings
+ _fw_restore_dma_fifo();
+
+ // clear suspend..................
+ HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
+ (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)&(~BIT0)));
+ HAL_WORD_REG_WRITE(0x52028, HAL_WORD_REG_READ(0x52028)&(~(BIT8|BIT12|BIT16)));
+}
+
+/*
+ * -- patch zfResetUSBFIFO_patch --
+ *
+ * . clear ep3/ep4 fifo
+ * . set suspend magic pattern
+ * . reset pcie ep phy
+ * . reset pcie rc phy
+ * . turn off pcie pll
+ * . reset all pcie/gmac related registers
+ * . reset usb dma
+ */
+void zfResetUSBFIFO_patch(void)
+{
+ A_PRINTF("0x9808 0x%x ......\n", HAL_WORD_REG_READ(0x10ff9808));
+ A_PRINTF("0x7890 0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890));
+ A_PRINTF("0x7890 0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890));
+ A_PRINTF("0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
+ _fw_reset_dma_fifo();
+}
+
+static void _fw_reset_dma_fifo()
+{
+ HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
+ HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10));
+ A_PRINTF("_fw_reset_dma_fifo\n");
+
+ // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!!
+ mUSB_STATUS_IN_INT_DISABLE();
+
+ // update magic pattern to indicate this is a suspend
+ HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, SUS_MAGIC_PATTERN);
+
+ A_PRINTF("org 0x4048 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048));
+ A_PRINTF("org 0x404C 0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C));
+ A_PRINTF("org 0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
+
+ HAL_WORD_REG_WRITE(0x10ff4088,0xaaa6a);//1010.1010.1010.0110.1010 for UB94
+ HAL_WORD_REG_WRITE(0x10ff404C,0x0);
+
+ A_DELAY_USECS(1000);
+ A_PRINTF("0x4048 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048));
+ A_PRINTF("0x404C 0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C));
+ A_PRINTF("0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
+
+ // turn off merlin
+ turn_off_merlin();
+ // pcie ep
+ A_PRINTF("turn_off_magpie_ep_start ......\n");
+ A_DELAY_USECS(measure_time);
+ HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)|BIT0|(1<<1)));
+ turn_off_phy();
+ HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&~(BIT0|(1<<1))));
+ A_PRINTF("turn_off_magpie_ep_end ......\n");
+
+ // pcie rc
+ A_PRINTF("turn_off_magpie_rc_start ......\n");
+ A_DELAY_USECS(measure_time);
+ HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&(~BIT0)));
+ turn_off_phy_rc();
+ A_PRINTF("turn_off_magpie_rc_end ......down\n");
+ A_DELAY_USECS(measure_time);
+
+ A_PRINTF("0x4001C %p ......\n", HAL_WORD_REG_READ(0x4001c));
+ A_PRINTF("0x40040 %p ......\n", HAL_WORD_REG_READ(0x40040));
+
+ // turn off pcie_pll - power down (bit16)
+ A_PRINTF(" before pwd PCIE PLL CFG:0x5601C %p ......\n", HAL_WORD_REG_READ(0x5601C));
+ HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)|(BIT18)));
+ A_PRINTF(" after pwd PCIE PLL CFG:0x5601C %p ......\n", HAL_WORD_REG_READ(0x5601C));
+
+ /* set everything to reset state?, requested by Oligo */
+ HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)|(BIT13|BIT12|BIT11|BIT9|BIT7|BIT6));
+
+ HAL_WORD_REG_WRITE(0x5C000, 0);
+
+ A_DELAY_USECS(10);
+
+ /* reset usb DMA controller */
+ USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0);
+
+ HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT4)));
+ A_DELAY_USECS(5);
+ HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~BIT4)));
+
+ USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0);
+}
+
+static void _fw_power_off()
+{
+ /*
+ * 1. set CPU bypass
+ * 2. turn off CPU PLL
+ * 3. turn off ETH PLL
+ * 4. disable ETH PLL bypass and update
+ * 4.1 set suspend timeout
+ * 5. set SUSPEND_ENABLE
+ */
+
+ HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4)); //0x56004
+
+ A_DELAY_USECS(100); // wait for stable
+
+ HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));//0x56000
+
+ A_DELAY_USECS(100); // wait for stable
+
+ A_UART_HWINIT((40*1000*1000), 19200);
+ A_CLOCK_INIT(40);
+
+ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR,
+ (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)|(BIT16))); //0x5600c
+
+ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,
+ (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)|(BIT4|BIT0))); //0x56010
+
+ HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
+ (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(0x10<<8))); //0x56030
+}
+
+static void _fw_power_on()
+{
+ /*
+ * 1. turn on CPU PLL
+ * 2. disable CPU bypass
+ * 3. turn on ETH PLL
+ * 4. disable ETH PLL bypass and update
+ * 5. turn on pcie pll
+ */
+
+ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR,
+ (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)&(~BIT16)));
+
+ // deassert eth_pll bypass mode and trigger update bit
+ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,
+ (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)&(~(BIT4|BIT0))));
+}
+
+#define CMD_PCI_RC_RESET_ON() HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \
+ (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)| \
+ (PCI_RC_PHY_SHIFT_RESET_BIT|PCI_RC_PLL_RESET_BIT|PCI_RC_PHY_RESET_BIT|PCI_RC_RESET_BIT)))
+
+static void _fw_restore_dma_fifo(void)
+{
+ HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)&(~(BIT18))));
+
+ // reset pcie_rc shift
+ HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~(BIT10|BIT8|BIT7))));
+ A_DELAY_USECS(1);
+ HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT10|BIT8|BIT7)));
+
+ // reset pci_rc phy
+ CMD_PCI_RC_RESET_ON();
+ A_DELAY_USECS(20);
+
+ // enable dma swap function
+ MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
+ MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
+ MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
+ MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
+}
--- /dev/null
+/* shared patches for k2 and magpie */
+
+#include "usb_defs.h"
+#include "usb_type.h"
+#include "usb_pre.h"
+#include "usb_extr.h"
+#include "usb_std.h"
+#include "reg_defs.h"
+#include "athos_api.h"
+#include "usbfifo_api.h"
+
+#include "sys_cfg.h"
+
+#define USB_EP4_MAX_PKT_SIZE bUSB_EP_MAX_PKT_SIZE_64
+#define USB_EP3_MAX_PKT_SIZE bUSB_EP_MAX_PKT_SIZE_64
+
+extern USB_FIFO_CONFIG usbFifoConf;
+extern Action eUsbCxFinishAction;
+extern void _fw_usb_suspend_reboot();
+
+typedef void (* USBFIFO_recv_command)(VBUF *cmd);
+USBFIFO_recv_command m_origUsbfifoRecvCmd = NULL;
+
+void _fw_usbfifo_recv_command(VBUF *buf)
+{
+ uint8_t *cmd_data;
+ uint32_t tmp;
+
+ cmd_data = (uint8_t *)(buf->desc_list->buf_addr +
+ buf->desc_list->data_offset);
+ tmp = *((uint32_t *)cmd_data);
+ if (tmp == 0xFFFFFFFF)
+ _fw_usb_suspend_reboot();
+ else
+ m_origUsbfifoRecvCmd(buf);
+}
+
+void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig)
+{
+ m_origUsbfifoRecvCmd = pConfig->recv_command;
+
+ usbFifoConf.get_command_buf = pConfig->get_command_buf;
+ usbFifoConf.recv_command = _fw_usbfifo_recv_command;
+ usbFifoConf.get_event_buf = pConfig->get_event_buf;
+ usbFifoConf.send_event_done = pConfig->send_event_done;
+}
+
+void cold_reboot(void)
+{
+ A_PRINTF("Cold reboot initiated.");
+#if defined(PROJECT_MAGPIE)
+ HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, 0);
+#elif defined(PROJECT_K2)
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, 0);
+#endif /* #if defined(PROJECT_MAGPIE) */
+ A_USB_JUMP_BOOT();
+}
+
+/*
+ * support more than 64 bytes command on ep3
+ */
+void usb_status_in_patch(void)
+{
+ uint16_t count;
+ uint16_t remainder;
+ uint16_t reg_buf_len;
+ static uint16_t buf_len;
+ static VBUF *evntbuf = NULL;
+ static volatile uint32_t *regaddr;
+ static BOOLEAN cmd_is_new = TRUE;
+ BOOLEAN cmd_end = FALSE;
+
+ if (cmd_is_new) {
+ evntbuf = usbFifoConf.get_event_buf();
+ if (evntbuf != NULL) {
+ regaddr = (uint32_t *)VBUF_GET_DATA_ADDR(evntbuf);
+ buf_len = evntbuf->buf_length;
+ } else {
+ mUSB_STATUS_IN_INT_DISABLE();
+ return;
+ }
+
+ cmd_is_new = FALSE;
+ }
+
+ if (buf_len > USB_EP3_MAX_PKT_SIZE) {
+ reg_buf_len = USB_EP3_MAX_PKT_SIZE;
+ buf_len -= USB_EP3_MAX_PKT_SIZE;
+ }
+ /* TODO: 64 bytes...
+ * controller supposed will take care of zero-length? */
+ else {
+ reg_buf_len = buf_len;
+ cmd_end = TRUE;
+ }
+
+ /* INT use EP3 */
+ for (count = 0; count < (reg_buf_len / 4); count++)
+ {
+ USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
+ regaddr++;
+ }
+
+ remainder = reg_buf_len % 4;
+
+ if (remainder) {
+ switch(remainder) {
+ case 3:
+ USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
+ break;
+ case 2:
+ USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
+ break;
+ case 1:
+ USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
+ break;
+ }
+
+ USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
+
+ /* Restore CBus FIFO size to word size */
+ USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
+ }
+
+ mUSB_EP3_XFER_DONE();
+
+ if (evntbuf != NULL && cmd_end) {
+ usbFifoConf.send_event_done(evntbuf);
+ cmd_is_new = TRUE;
+ }
+}
+
+/*
+ * support more than 64 bytes command on ep4
+ */
+void usb_reg_out_patch(void)
+{
+ uint16_t usbfifolen;
+ uint16_t ii;
+ uint32_t ep4_data;
+ static volatile uint32_t *regaddr;
+ static uint16_t cmd_len;
+ static VBUF *buf;
+ BOOLEAN cmd_is_last = FALSE;
+ static BOOLEAN cmd_is_new = TRUE;
+
+ /* get the size of this transcation */
+ usbfifolen = USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_LOW_OFFSET);
+
+ if (usbfifolen > USB_EP4_MAX_PKT_SIZE) {
+ A_PRINTF("EP4 FIFO Bug? Buffer is too big: %x\n", usbfifolen);
+ cold_reboot();
+ }
+
+ /* check is command is new */
+ if(cmd_is_new) {
+
+ buf = usbFifoConf.get_command_buf();
+ cmd_len = 0;
+
+ if(!buf) {
+ A_PRINTF("%s: Filed to get new buffer.\n", __func__);
+ goto err;
+ }
+
+ /* copy free, assignment buffer of the address */
+ regaddr = (uint32_t *)buf->desc_list->buf_addr;
+
+ cmd_is_new = FALSE;
+ }
+
+ /* just in case, suppose should not happen */
+ if(!buf)
+ goto err;
+
+ /* if size is smaller, this is the last command!
+ * zero-length supposed should be set through 0x27/bit7->0x19/bit4, not here
+ */
+ if(usbfifolen < USB_EP4_MAX_PKT_SIZE)
+ cmd_is_last = TRUE;
+
+ /* accumulate the size */
+ cmd_len += usbfifolen;
+
+ if (cmd_len > buf->desc_list->buf_size) {
+ A_PRINTF("%s: Data length on EP4 FIFO is bigger as "
+ "allocated buffer data! Drop it!\n", __func__);
+ goto err;
+ }
+
+ /* round it to alignment */
+ if(usbfifolen % 4)
+ usbfifolen = (usbfifolen >> 2) + 1;
+ else
+ usbfifolen = usbfifolen >> 2;
+
+ /* retrieve the data from fifo */
+ for(ii = 0; ii < usbfifolen; ii++) {
+ /* read fifo data out */
+ ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET);
+ *regaddr = ep4_data;
+ regaddr++;
+ }
+
+ /* if this is the last command, callback to HTC */
+ if (cmd_is_last) {
+ buf->desc_list->next_desc = NULL;
+ buf->desc_list->data_offset = 0;
+ buf->desc_list->data_size = cmd_len;
+ buf->desc_list->control = 0;
+ buf->next_buf = NULL;
+ buf->buf_length = cmd_len;
+
+ usbFifoConf.recv_command(buf);
+
+ cmd_is_new = TRUE;
+ }
+
+ goto done;
+err:
+ /* we might get no command buffer here?
+ * but if we return here, the ep4 fifo will be lock out,
+ * so that we still read them out but just drop it? */
+ for(ii = 0; ii < usbfifolen; ii++)
+ ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET);
+
+done:
+ /* mUSB_STATUS_IN_INT_ENABLE(); */
+ ;
+}
+
+/*
+ * usb1.1 ep6 fix
+ * TODO:
+ * - theoretically ep6 configured same way as ep1
+ * so, if there are some problems we should have it
+ * there too.
+ * - do we really need support usb1.1?
+ */
+extern uint16_t u8UsbConfigValue;
+extern uint16_t u8UsbInterfaceValue;
+extern uint16_t u8UsbInterfaceAlternateSetting;
+extern SetupPacket ControlCmd;
+extern void vUsbClrEPx(void);
+
+#undef FS_C1_I0_A0_EP_NUMBER
+#define FS_C1_I0_A0_EP_NUMBER 6
+
+#define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE
+#define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK
+#define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT
+#define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK
+#define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040
+#define FS_C1_I0_A0_EP6_bInterval 0
+
+/* EP6 */
+#define FS_C1_I0_A0_EP6_FIFO_START \
+ (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO)
+#define FS_C1_I0_A0_EP6_FIFO_NO \
+ (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE)
+#define FS_C1_I0_A0_EP6_FIFO_CONFIG \
+ (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | \
+ ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE)
+#define FS_C1_I0_A0_EP6_FIFO_MAP \
+ (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
+#define FS_C1_I0_A0_EP6_MAP \
+ (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | \
+ (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION)))
+
+void vUSBFIFO_EP6Cfg_FS_patch(void)
+{
+#if (FS_C1_I0_A0_EP_NUMBER >= 6)
+ int i;
+
+ /* EP0X06 */
+ mUsbEPMap(EP6, FS_C1_I0_A0_EP6_MAP);
+ mUsbFIFOMap(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_MAP);
+ mUsbFIFOConfig(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_CONFIG);
+
+ for(i = FS_C1_I0_A0_EP6_FIFO_START + 1 ;
+ i < FS_C1_I0_A0_EP6_FIFO_START + FS_C1_I0_A0_EP6_FIFO_NO ; i ++)
+ {
+ mUsbFIFOConfig(i, (FS_C1_I0_A0_EP6_FIFO_CONFIG & (~BIT7)) );
+ }
+
+ mUsbEPMxPtSzHigh(EP6, FS_C1_I0_A0_EP6_DIRECTION,
+ (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff));
+ mUsbEPMxPtSzLow(EP6, FS_C1_I0_A0_EP6_DIRECTION,
+ (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff));
+ mUsbEPinHighBandSet(EP6, FS_C1_I0_A0_EP6_DIRECTION,
+ FS_C1_I0_A0_EP6_MAX_PACKET);
+#endif
+}
+
+void vUsbFIFO_EPxCfg_FS_patch(void)
+{
+ switch (u8UsbConfigValue)
+ {
+#if (FS_CONFIGURATION_NUMBER >= 1)
+ /* Configuration 0X01 */
+ case 0X01:
+ switch (u8UsbInterfaceValue)
+ {
+#if (FS_C1_INTERFACE_NUMBER >= 1)
+ /* Interface 0 */
+ case 0:
+ switch (u8UsbInterfaceAlternateSetting)
+ {
+
+#if (FS_C1_I0_ALT_NUMBER >= 1)
+ /* AlternateSetting 0 */
+ case 0:
+
+ /* snapped.... */
+
+ /* patch up this ep6_fs config */
+ vUSBFIFO_EP6Cfg_FS_patch();
+
+ break;
+
+#endif
+ default:
+ break;
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+ /* mCHECK_STACK(); */
+}
+
+BOOLEAN bSet_configuration_patch(void)
+{
+ /* do some defaul configuration */
+ bSet_configuration();
+
+ /* overwrite defaul FIFO configuration for FullSpeed USB */
+ if ((mLOW_BYTE(mDEV_REQ_VALUE()) != 0) && !mUsbHighSpeedST())
+ vUsbFIFO_EPxCfg_FS_patch();
+
+ eUsbCxFinishAction = ACT_DONE;
+ return TRUE;
+}
+
+extern BOOLEAN bStandardCommand(void);
+
+BOOLEAN bStandardCommand_patch(void)
+{
+ if (mDEV_REQ_REQ() == USB_SET_CONFIGURATION) {
+ A_USB_SET_CONFIG();
+
+#if ENABLE_SWAP_DATA_MODE
+ /* SWAP FUNCTION should be enabled while DMA engine
+ * is not working, the best place to enable it
+ * is before we trigger the DMA */
+ MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
+ MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
+
+#if SYSTEM_MODULE_HP_EP5
+ MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
+#endif
+
+#if SYSTEM_MODULE_HP_EP6
+ MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
+#endif
+
+#endif /* ENABLE_SWAP_DATA_MODE */
+ return TRUE;
+ } else
+ return bStandardCommand();
+}
+
+/*
+ * usb descriptor patch
+ */
+
+extern uint16_t *u8ConfigDescriptorEX;
+extern uint16_t *pu8DescriptorEX;
+extern uint16_t u16TxRxCounter;
+extern SetupPacket ControlCmd;
+extern uint16_t *u8UsbDeviceDescriptor;
+extern BOOLEAN bGet_descriptor(void);
+
+uint16_t ConfigDescriptorPatch[30];
+uint16_t UsbDeviceDescriptorPatch[9];
+
+#define BCD_DEVICE_OFFSET 6
+#define BCD_DEVICE_FW_SIGNATURE 0xffff
+#define VENDOR_ID_OFFSET 4
+#define PRODUCT_ID_OFFSET 5
+
+#define EP3_TRANSFER_TYPE_OFFSET 17
+#define EP3_INT_INTERVAL 19
+#define EP4_TRANSFER_TYPE_OFFSET 21
+#define EP4_INT_INTERVAL 22
+
+BOOLEAN bGet_descriptor_patch(void)
+{
+ if (mDEV_REQ_VALUE_HIGH() == 1)
+ {
+ uint8_t *p = (uint8_t *)u8UsbDeviceDescriptor;
+
+ /* Copy Usb Device Descriptor */
+ ath_hal_memcpy(UsbDeviceDescriptorPatch, p,
+ sizeof(UsbDeviceDescriptorPatch));
+
+ /* Change bcdDevice. we need it to detect if FW
+ * was uploaded. */
+ UsbDeviceDescriptorPatch[BCD_DEVICE_OFFSET] =
+ BCD_DEVICE_FW_SIGNATURE;
+
+ pu8DescriptorEX = UsbDeviceDescriptorPatch;
+ u16TxRxCounter = mTABLE_LEN(u8UsbDeviceDescriptor[0]);
+
+ if (u16TxRxCounter > mDEV_REQ_LENGTH())
+ u16TxRxCounter = mDEV_REQ_LENGTH();
+
+ A_USB_EP0_TX_DATA();
+
+ return TRUE;
+ } else if (mDEV_REQ_VALUE_HIGH() == 2) {
+ uint8_t *p = (uint8_t *)u8ConfigDescriptorEX;
+
+ /* Copy ConfigDescriptor */
+ ath_hal_memcpy(ConfigDescriptorPatch, p,
+ sizeof(ConfigDescriptorPatch));
+
+ /* place holder for EPx patches */
+
+ if (mDEV_REQ_VALUE_LOW() == 0) {
+ /* configuration no: 0 */
+ pu8DescriptorEX = ConfigDescriptorPatch;
+ u16TxRxCounter = ConfigDescriptorPatch[1];
+ } else
+ return FALSE;
+
+ if (u16TxRxCounter > mDEV_REQ_LENGTH())
+ u16TxRxCounter = mDEV_REQ_LENGTH();
+
+ A_USB_EP0_TX_DATA();
+ return TRUE;
+ } else
+ return bGet_descriptor();
+}
+
+++ /dev/null
-/*
- * Copyright (c) 2013 Qualcomm Atheros, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted (subject to the limitations in the
- * disclaimer below) provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * * Neither the name of Qualcomm Atheros nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
- * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef USB_DEFS_H
-#define USB_DEFS_H
-
-#include "usb_table.h"
-#include "dt_defs.h"
-#include "reg_defs.h"
-
-#define CHECK_SWITCH_BY_BOOTCODE 1 //to be verified for ZD1215, OK for ZD1211
-#define VERIFY_CHECKSUM_BY_BOOTCODE 1
-
-/***********************************************************************/
-/* for SEEPROM Boot */
-/***********************************************************************/
-#define WLAN_BOOT_SIGNATURE (0x19710303)
-
-#define WLAN_SIGNATURE_ADDR (0x102000)
-
-#define cMAX_ADDR 0x10000
-
-#define cEEPROM_SIZE 0x800 // 2k word (4k byte)
-
-#define cRESERVE_LOAD_SPACE 0
-
-// start addr. of boot code
-#define cBOOT_CODE_ADDR (cMAX_ADDR - cEEPROM_SIZE) // 0xF800
-
-/************************** Register Addr Process *********************/
-#define mpADDR(addr) ((volatile uint16_t*) (addr))
-#define mADDR(addr) (*mpADDR(addr))
-#define muADDR(addr) ((uint16_t) (&(addr)))
-
-#define USB_BYTE_REG_WRITE(addr, val) HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val))
-#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3))
-//#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr))
-
-#define USB_HALF_WORD_REG_WRITE(addr, val) HAL_HALF_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr), (val))
-#define USB_HALF_WORD_REG_READ(addr) HAL_HALF_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr))
-
-#define USB_WORD_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val))
-#define USB_WORD_REG_READ(addr) HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr))
-
-
-/************************** Register Deinition ***************************/
-//#define USB_BASE_ADDR_SOC 0x8000
-
-//#define SOC_Reg mpADDR(USB_BASE_ADDR_SOC)
-
-#define cSOC_USB_OFST (0x100)
-
-#define ZM_CBUS_FIFO_SIZE_OFFSET (cSOC_USB_OFST) //OFFSET 0
-
-#define cSOC_CBUS_CTL_OFFSET 0xF0
-
-#define ZM_FUSB_BASE USB_CTRL_BASE_ADDRESS
-
-#define ZM_MAIN_CTRL_OFFSET 0x00
-#define ZM_DEVICE_ADDRESS_OFFSET 0x01
-#define ZM_TEST_OFFSET 0x02
-#define ZM_PHY_TEST_SELECT_OFFSET 0x08
-#define ZM_VDR_SPECIFIC_MODE_OFFSET 0x0A
-#define ZM_CX_CONFIG_STATUS_OFFSET 0x0B
-#define ZM_EP0_DATA1_OFFSET 0x0C
-#define ZM_EP0_DATA2_OFFSET 0x0D
-#define ZM_EP0_DATA_OFFSET 0x0C
-
-#define ZM_INTR_MASK_BYTE_0_OFFSET 0x11
-#define ZM_INTR_MASK_BYTE_1_OFFSET 0x12
-#define ZM_INTR_MASK_BYTE_2_OFFSET 0x13
-#define ZM_INTR_MASK_BYTE_3_OFFSET 0x14
-#define ZM_INTR_MASK_BYTE_4_OFFSET 0x15
-#define ZM_INTR_MASK_BYTE_5_OFFSET 0x16
-#define ZM_INTR_MASK_BYTE_6_OFFSET 0x17
-#define ZM_INTR_MASK_BYTE_7_OFFSET 0x18
-
-#define ZM_INTR_GROUP_OFFSET 0x20
-#define ZM_INTR_SOURCE_0_OFFSET 0x21
-#define ZM_INTR_SOURCE_1_OFFSET 0x22
-#define ZM_INTR_SOURCE_2_OFFSET 0x23
-#define ZM_INTR_SOURCE_3_OFFSET 0x24
-#define ZM_INTR_SOURCE_4_OFFSET 0x25
-#define ZM_INTR_SOURCE_5_OFFSET 0x26
-#define ZM_INTR_SOURCE_6_OFFSET 0x27
-#define ZM_INTR_SOURCE_7_OFFSET 0x28
-
-#define ZM_EP_IN_MAX_SIZE_HIGH_OFFSET 0x3F
-#define ZM_EP_IN_MAX_SIZE_LOW_OFFSET 0x3E
-
-#define ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET 0x5F
-#define ZM_EP_OUT_MAX_SIZE_LOW_OFFSET 0x5E
-
-#define ZM_EP3_BYTE_COUNT_HIGH_OFFSET 0xAE
-#define ZM_EP3_BYTE_COUNT_LOW_OFFSET 0xBE
-#define ZM_EP4_BYTE_COUNT_HIGH_OFFSET 0xAF
-#define ZM_EP4_BYTE_COUNT_LOW_OFFSET 0xBF
-
-#define ZM_EP3_DATA_OFFSET 0xF8
-#define ZM_EP4_DATA_OFFSET 0xFC
-
-#define ZM_SOC_USB_MODE_CTRL_OFFSET 0x108
-#define ZM_SOC_USB_MAX_AGGREGATE_OFFSET 0x110
-#define ZM_SOC_USB_TIME_CTRL_OFFSET 0x114
-
-#define ZM_ADDR_CONV 0x0
-
-#define ZM_CBUS_FIFO_SIZE_REG (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_CBUS_CTRL_REG (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_MAIN_CTRL_REG (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_DEVICE_ADDRESS_REG (ZM_DEVICE_ADDRESS_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_TEST_REG (ZM_TEST_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_PHY_TEST_SELECT_REG (ZM_PHY_TEST_SELECT_OFFSET^ZM_ADDR_CONV)))
-
-#define ZM_CX_CONFIG_STATUS_REG (ZM_CX_CONFIG_STATUS_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_EP0_DATA1_REG (ZM_EP0_DATA1_OFFSET^ZM_ADDR_CONV)))
-
-#define ZM_EP0_DATA2_REG (ZM_EP0_DATA2_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_EP0_DATA_REG (ZM_EP0_DATA_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_0_REG (ZM_INTR_MASK_BYTE_0_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_1_REG (ZM_INTR_MASK_BYTE_1_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_2_REG (ZM_INTR_MASK_BYTE_2_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_3_REG (ZM_INTR_MASK_BYTE_3_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_4_REG (ZM_INTR_MASK_BYTE_4_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_5_REG (ZM_INTR_MASK_BYTE_5_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_6_REG (ZM_INTR_MASK_BYTE_6_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_MASK_BYTE_7_REG (ZM_INTR_MASK_BYTE_7_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_0_REG (ZM_INTR_SOURCE_0_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_1_REG (ZM_INTR_SOURCE_1_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_2_REG (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_3_REG (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_4_REG (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_5_REG (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_6_REG (ZM_INTR_SOURCE_6_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_SOURCE_7_REG (ZM_INTR_SOURCE_7_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_INTR_GROUP_REG (ZM_INTR_GROUP_OFFSET^ZM_ADDR_CONV)))
-
-#define ZM_EP3_BYTE_COUNT_HIGH_REG (ZM_EP3_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_EP3_BYTE_COUNT_LOW_REG (ZM_EP3_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_EP4_BYTE_COUNT_HIGH_REG (ZM_EP4_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_EP4_BYTE_COUNT_LOW_REG (ZM_EP4_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
-
-#define ZM_EP3_DATA_REG (ZM_EP3_DATA_OFFSET)
-
-#define ZM_EP4_DATA_REG (ZM_EP4_DATA_OFFSET)
-
-#define ZM_SOC_USB_MODE_CTRL_REG (ZM_SOC_USB_MODE_CTRL_OFFSET)
-
-#define ZM_SOC_USB_MAX_AGGREGATE_REG (ZM_SOC_USB_MAX_AGGREGATE_OFFSET)
-
-#define ZM_SOC_USB_TIME_CTRL_REG (ZM_SOC_USB_TIME_CTRL_OFFSET)
-
-#define bmHIGH_SPEED BIT6
-#define bmCWR_BUF_END BIT1
-
-#define mUsbEP0DataRd1() (USB_BYTE_REG_READ(ZM_EP0_DATA1_OFFSET))
-//#define mUsbEP0DataRd2() ZM_EP0_DATA2_REG
-//#define mUsbEP0DataRd3() ZM_EP0_DATA3_REG
-//#define mUsbEP0DataRd4() ZM_EP0_DATA4_REG
-#define mUsbEP0DataWr1(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA1_OFFSET, data))
-#define mUsbEP0DataWr2(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA2_OFFSET, data))
-
-#define mGetByte0(data) ( data & 0xff )
-#define mGetByte1(data) ( (data >> 8) & 0xff )
-#define mGetByte2(data) ( (data >> 16) & 0xff )
-#define mGetByte3(data) ( (data >> 24) & 0xff )
-
-//#define mUsbHighSpeedST() (ZM_MAIN_CTRL_REG & BIT6)
-//#define mUsbCfgST() (ZM_DEVICE_ADDRESS_REG & BIT7)
-//#define mUsbApWrEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
-//#define mUsbApRdEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
-
-#define mUsbHighSpeedST() (USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET) & BIT6)
-#define mUsbCfgST() (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET) & BIT7)
-#define mUsbApWrEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
-#define mUsbApRdEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
-
-#define mUsbRmWkupST() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
- USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT0)
-#define mUsbRmWkupClr() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
- USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0)
-#define mUsbRmWkupSet() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
- USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0)
-
-#define mUsbGlobIntEnable() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
- USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2)
-
-#define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
- USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f)
-#define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
- USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)|0xc0)
-#define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
- USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf)
-#define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
- USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0)
-// USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0x40)
-
-#define mUSB_EP3_XFER_DONE() USB_BYTE_REG_WRITE(ZM_EP3_BYTE_COUNT_HIGH_OFFSET, \
- USB_BYTE_REG_READ(ZM_EP3_BYTE_COUNT_HIGH_OFFSET)|0x08)
-
-
-
-#define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512
-#define HS_C1_I0_A0_EP1_bInterval 00
-
-#define HS_C1_I0_A0_EP_NUMBER 0x06
-#define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
-#define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH)
-#define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH)
-
-#define HS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + HS_C1_INTERFACE_LENGTH)
-#define FS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + FS_C1_INTERFACE_LENGTH)
-
-#define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64
-//#define FS_C1_I0_A0_EP1_bInterval HS_C1_I0_A0_EP1_bInterval
-
-#define HS_CONFIGURATION_NUMBER 1
-#define FS_CONFIGURATION_NUMBER 1
-
-#define fDOUBLE_BUF 1
-#define fDOUBLE_BUF_IN 1
-
-#define fFLASH_DISK 0
-#define fENABLE_ISO 0
-
-#if (HS_CONFIGURATION_NUMBER >= 1)
- // Configuration 0X01
- #define HS_C1_INTERFACE_NUMBER 0x01
- #define HS_C1 0x01
- #define HS_C1_iConfiguration 0x00
- #define HS_C1_bmAttribute 0x80
- #if !(fFLASH_DISK && !fFLASH_BOOT)
- #define HS_C1_iMaxPower 0xFA
- #else
- #define HS_C1_iMaxPower 0x32
- #endif
-
- #if (HS_C1_INTERFACE_NUMBER >= 1)
- // Interface 0
- #define HS_C1_I0_ALT_NUMBER 0X01
- #if (HS_C1_I0_ALT_NUMBER >= 1)
- // AlternateSetting 0X00
- #define HS_C1_I0_A0_bInterfaceNumber 0X00
- #define HS_C1_I0_A0_bAlternateSetting 0X00
- //JWEI 2003/07/14
- //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
- #define HS_C1_I0_A0_EP_NUMBER 0x06
- //#else
- //#define HS_C1_I0_A0_EP_NUMBER 0X03
- //#endif
- #if !(fFLASH_DISK && !fFLASH_BOOT)
- #define HS_C1_I0_A0_bInterfaceClass 0XFF
- #define HS_C1_I0_A0_bInterfaceSubClass 0X00
- #define HS_C1_I0_A0_bInterfaceProtocol 0X00
- #else
- #define HS_C1_I0_A0_bInterfaceClass 0X08
- #define HS_C1_I0_A0_bInterfaceSubClass 0X06
- #define HS_C1_I0_A0_bInterfaceProtocol 0X50
- #endif
- #define HS_C1_I0_A0_iInterface 0X00
-
- #if (HS_C1_I0_A0_EP_NUMBER >= 1)
- //EP0X01
- #define HS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE
- //JWEI 2003/05/19
- #if fDOUBLE_BUF
- #define HS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK
- #else
- #define HS_C1_I0_A0_EP1_BLKNO SINGLE_BLK
- #endif
- #define HS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT
- #define HS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK
- //JWEI 2003/05/07
- #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512
- #define HS_C1_I0_A0_EP1_bInterval 00
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 2)
- //EP0X02
- #define HS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE
- //JWEI 2003/08/20
- #if fDOUBLE_BUF_IN
- #define HS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK
- #else
- #define HS_C1_I0_A0_EP2_BLKNO SINGLE_BLK
- #endif
- #define HS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN
- #define HS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK
- #define HS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_512
- #define HS_C1_I0_A0_EP2_bInterval 00
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 3)
- //EP0X03
- #define HS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE
- #define HS_C1_I0_A0_EP3_BLKNO SINGLE_BLK
- #define HS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN
- #define HS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT
- #define HS_C1_I0_A0_EP3_MAX_PACKET 0x0040
- #define HS_C1_I0_A0_EP3_bInterval 01
- #endif
- // Note: HS Bulk type require max pkt size = 512
- // ==> must use Interrupt type for max pkt size = 64
- #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
- //EP0X04
- #define HS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE
- #define HS_C1_I0_A0_EP4_BLKNO SINGLE_BLK
- #define HS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT
- #define HS_C1_I0_A0_EP4_TYPE TF_TYPE_INTERRUPT
- #define HS_C1_I0_A0_EP4_MAX_PACKET 0x0040
- #define HS_C1_I0_A0_EP4_bInterval 01
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 5)
- //EP0X04
- #define HS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE
- #if fDOUBLE_BUF
- #define HS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK
- #else
- #define HS_C1_I0_A0_EP5_BLKNO SINGLE_BLK
- #endif
- #define HS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT
- #define HS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK
- #define HS_C1_I0_A0_EP5_MAX_PACKET MX_PA_SZ_512
- #define HS_C1_I0_A0_EP5_bInterval 00
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 6)
- //EP0X04
- #define HS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE
- #if fDOUBLE_BUF
- #define HS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK
- #else
- #define HS_C1_I0_A0_EP6_BLKNO SINGLE_BLK
- #endif
- #define HS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT
- #define HS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK
- #define HS_C1_I0_A0_EP6_MAX_PACKET MX_PA_SZ_512
- #define HS_C1_I0_A0_EP6_bInterval 00
- #endif
- #endif
- #endif
-#endif
-
-#if (HS_CONFIGURATION_NUMBER >= 1)
- // Configuration 1
- #if (HS_C1_INTERFACE_NUMBER >= 1)
- // Interface 0
- #if (HS_C1_I0_ALT_NUMBER >= 1)
- // AlternateSetting 0
- #define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
- #if (HS_C1_I0_A0_EP_NUMBER >= 1)
- // EP1
- #define HS_C1_I0_A0_EP1_FIFO_START FIFO0
- #define HS_C1_I0_A0_EP1_FIFO_NO (HS_C1_I0_A0_EP1_BLKNO * HS_C1_I0_A0_EP1_BLKSIZE)
- #define HS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP1_BLKNO - 1) << 2) | HS_C1_I0_A0_EP1_TYPE)
- #define HS_C1_I0_A0_EP1_FIFO_MAP (((1 - HS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
- #define HS_C1_I0_A0_EP1_MAP (HS_C1_I0_A0_EP1_FIFO_START | (HS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP1_DIRECTION)))
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 2)
- // EP2
- #if fDOUBLE_BUF
- #define HS_C1_I0_A0_EP2_FIFO_START (HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO)
- #else
- #define HS_C1_I0_A0_EP2_FIFO_START FIFO2
- #endif
- #define HS_C1_I0_A0_EP2_FIFO_NO (HS_C1_I0_A0_EP2_BLKNO * HS_C1_I0_A0_EP2_BLKSIZE)
- #define HS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP2_BLKNO - 1) << 2) | HS_C1_I0_A0_EP2_TYPE)
- #define HS_C1_I0_A0_EP2_FIFO_MAP (((1 - HS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
- #define HS_C1_I0_A0_EP2_MAP (HS_C1_I0_A0_EP2_FIFO_START | (HS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP2_DIRECTION)))
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 3)
- // EP3
- //JWEI 2003/07/15
- // #define HS_C1_I0_A0_EP3_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
- #define HS_C1_I0_A0_EP3_FIFO_START FIFO14
- #define HS_C1_I0_A0_EP3_FIFO_NO (HS_C1_I0_A0_EP3_BLKNO * HS_C1_I0_A0_EP3_BLKSIZE)
- #define HS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP3_BLKNO - 1) << 2) | HS_C1_I0_A0_EP3_TYPE)
- #define HS_C1_I0_A0_EP3_FIFO_MAP (((1 - HS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
- #define HS_C1_I0_A0_EP3_MAP (HS_C1_I0_A0_EP3_FIFO_START | (HS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP3_DIRECTION)))
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
- // EP4
- #define HS_C1_I0_A0_EP4_FIFO_START (HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO)
- #define HS_C1_I0_A0_EP4_FIFO_NO (HS_C1_I0_A0_EP4_BLKNO * HS_C1_I0_A0_EP4_BLKSIZE)
- #define HS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP4_BLKNO - 1) << 2) | HS_C1_I0_A0_EP4_TYPE)
- #define HS_C1_I0_A0_EP4_FIFO_MAP (((1 - HS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
- #define HS_C1_I0_A0_EP4_MAP (HS_C1_I0_A0_EP4_FIFO_START | (HS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP4_DIRECTION)))
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 5)
- // EP5
- #define HS_C1_I0_A0_EP5_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
- #define HS_C1_I0_A0_EP5_FIFO_NO (HS_C1_I0_A0_EP5_BLKNO * HS_C1_I0_A0_EP5_BLKSIZE)
- #define HS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP5_BLKNO - 1) << 2) | HS_C1_I0_A0_EP5_TYPE)
- #define HS_C1_I0_A0_EP5_FIFO_MAP (((1 - HS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
- #define HS_C1_I0_A0_EP5_MAP (HS_C1_I0_A0_EP5_FIFO_START | (HS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP5_DIRECTION)))
- #endif
- #if (HS_C1_I0_A0_EP_NUMBER >= 6)
- // EP5
- #define HS_C1_I0_A0_EP6_FIFO_START (HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO)
- #define HS_C1_I0_A0_EP6_FIFO_NO (HS_C1_I0_A0_EP6_BLKNO * HS_C1_I0_A0_EP6_BLKSIZE)
- #define HS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP6_BLKNO - 1) << 2) | HS_C1_I0_A0_EP6_TYPE)
- #define HS_C1_I0_A0_EP6_FIFO_MAP (((1 - HS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
- #define HS_C1_I0_A0_EP6_MAP (HS_C1_I0_A0_EP6_FIFO_START | (HS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP6_DIRECTION)))
- #endif
- #endif
-
- #if (HS_C1_I0_ALT_NUMBER >= 2)
- // AlternateSetting 1
- #define HS_C1_I0_A1_EP_LENGTH (EP_LENGTH * HS_C1_I0_A1_EP_NUMBER)
- #if (HS_C1_I0_A1_EP_NUMBER >= 1)
- // EP1
- #define HS_C1_I0_A1_EP1_FIFO_START FIFO0
- #define HS_C1_I0_A1_EP1_FIFO_NO (HS_C1_I0_A1_EP1_BLKNO * HS_C1_I0_A1_EP1_BLKSIZE)
- #define HS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP1_BLKNO - 1) << 2) | HS_C1_I0_A1_EP1_TYPE)
- #define HS_C1_I0_A1_EP1_FIFO_MAP (((1 - HS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
- #define HS_C1_I0_A1_EP1_MAP (HS_C1_I0_A1_EP1_FIFO_START | (HS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP1_DIRECTION)))
- #endif
- #if (HS_C1_I0_A1_EP_NUMBER >= 2)
- // EP2
- #define HS_C1_I0_A1_EP2_FIFO_START (HS_C1_I0_A1_EP1_FIFO_START + HS_C1_I0_A1_EP1_FIFO_NO)
- #define HS_C1_I0_A1_EP2_FIFO_NO (HS_C1_I0_A1_EP2_BLKNO * HS_C1_I0_A1_EP2_BLKSIZE)
- #define HS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP2_BLKNO - 1) << 2) | HS_C1_I0_A1_EP2_TYPE)
- #define HS_C1_I0_A1_EP2_FIFO_MAP (((1 - HS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
- #define HS_C1_I0_A1_EP2_MAP (HS_C1_I0_A1_EP2_FIFO_START | (HS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP2_DIRECTION)))
- #endif
- #if (HS_C1_I0_A1_EP_NUMBER >= 3)
- // EP3
- #define HS_C1_I0_A1_EP3_FIFO_START (HS_C1_I0_A1_EP2_FIFO_START + HS_C1_I0_A1_EP2_FIFO_NO)
- #define HS_C1_I0_A1_EP3_FIFO_NO (HS_C1_I0_A1_EP3_BLKNO * HS_C1_I0_A1_EP3_BLKSIZE)
- #define HS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP3_BLKNO - 1) << 2) | HS_C1_I0_A1_EP3_TYPE)
- #define HS_C1_I0_A1_EP3_FIFO_MAP (((1 - HS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
- #define HS_C1_I0_A1_EP3_MAP (HS_C1_I0_A1_EP3_FIFO_START | (HS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP3_DIRECTION)))
- #endif
- #endif
-
- #if (HS_C1_I0_ALT_NUMBER == 1)
- #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH)
- #elif (HS_C1_I0_ALT_NUMBER == 2)
- #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH + HS_C1_I0_A1_EP_LENGTH)
- #endif
- #endif
-
- #if (HS_C1_INTERFACE_NUMBER >= 2)
- // Interface 1
- #if (HS_C1_I1_ALT_NUMBER >= 1)
- // AlternateSetting 0
- #define HS_C1_I1_A0_EP_LENGTH (EP_LENGTH * HS_C1_I1_A0_EP_NUMBER)
- #if (HS_C1_I1_A0_EP_NUMBER >= 1)
- // EP1
- #define HS_C1_I1_A0_EP1_FIFO_START FIFO0
- #define HS_C1_I1_A0_EP1_FIFO_NO (HS_C1_I1_A0_EP1_BLKNO * HS_C1_I1_A0_EP1_BLKSIZE)
- #define HS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP1_BLKNO - 1) << 2) | HS_C1_I1_A0_EP1_TYPE)
- #define HS_C1_I1_A0_EP1_FIFO_MAP (((1 - HS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
- #define HS_C1_I1_A0_EP1_MAP (HS_C1_I1_A0_EP1_FIFO_START | (HS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP1_DIRECTION)))
- #endif
- #if (HS_C1_I1_A0_EP_NUMBER >= 2)
- // EP2
- #define HS_C1_I1_A0_EP2_FIFO_START (HS_C1_I1_A0_EP1_FIFO_START + HS_C1_I1_A0_EP1_FIFO_NO)
- #define HS_C1_I1_A0_EP2_FIFO_NO (HS_C1_I1_A0_EP2_BLKNO * HS_C1_I1_A0_EP2_BLKSIZE)
- #define HS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP2_BLKNO - 1) << 2) | HS_C1_I1_A0_EP2_TYPE)
- #define HS_C1_I1_A0_EP2_FIFO_MAP (((1 - HS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
- #define HS_C1_I1_A0_EP2_MAP (HS_C1_I1_A0_EP2_FIFO_START | (HS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP2_DIRECTION)))
- #endif
- #if (HS_C1_I1_A0_EP_NUMBER >= 3)
- // EP3
- #define HS_C1_I1_A0_EP3_FIFO_START (HS_C1_I1_A0_EP2_FIFO_START + HS_C1_I1_A0_EP2_FIFO_NO)
- #define HS_C1_I1_A0_EP3_FIFO_NO (HS_C1_I1_A0_EP3_BLKNO * HS_C1_I1_A0_EP3_BLKSIZE)
- #define HS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP3_BLKNO - 1) << 2) | HS_C1_I1_A0_EP3_TYPE)
- #define HS_C1_I1_A0_EP3_FIFO_MAP (((1 - HS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
- #define HS_C1_I1_A0_EP3_MAP (HS_C1_I1_A0_EP3_FIFO_START | (HS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP3_DIRECTION)))
- #endif
- #endif
-
- #if (HS_C1_I1_ALT_NUMBER >= 2)
- // AlternateSetting 1
- #define HS_C1_I1_A1_EP_LENGTH (EP_LENGTH * HS_C1_I1_A1_EP_NUMBER)
- #if (HS_C1_I1_A1_EP_NUMBER >= 1)
- // EP1
- #define HS_C1_I1_A1_EP1_FIFO_START FIFO0
- #define HS_C1_I1_A1_EP1_FIFO_NO (HS_C1_I1_A1_EP1_BLKNO * HS_C1_I1_A1_EP1_BLKSIZE)
- #define HS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP1_BLKNO - 1) << 2) | HS_C1_I1_A1_EP1_TYPE)
- #define HS_C1_I1_A1_EP1_FIFO_MAP (((1 - HS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
- #define HS_C1_I1_A1_EP1_MAP (HS_C1_I1_A1_EP1_FIFO_START | (HS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP1_DIRECTION)))
- #endif
- #if (HS_C1_I1_A1_EP_NUMBER >= 2)
- // EP2
- #define HS_C1_I1_A1_EP2_FIFO_START (HS_C1_I1_A1_EP1_FIFO_START + HS_C1_I1_A1_EP1_FIFO_NO)
- #define HS_C1_I1_A1_EP2_FIFO_NO (HS_C1_I1_A1_EP2_BLKNO * HS_C1_I1_A1_EP2_BLKSIZE)
- #define HS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP2_BLKNO - 1) << 2) | HS_C1_I1_A1_EP2_TYPE)
- #define HS_C1_I1_A1_EP2_FIFO_MAP (((1 - HS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
- #define HS_C1_I1_A1_EP2_MAP (HS_C1_I1_A1_EP2_FIFO_START | (HS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP2_DIRECTION)))
- #endif
- #if (HS_C1_I1_A1_EP_NUMBER >= 3)
- // EP3
- #define HS_C1_I1_A1_EP3_FIFO_START (HS_C1_I1_A1_EP2_FIFO_START + HS_C1_I1_A1_EP2_FIFO_NO)
- #define HS_C1_I1_A1_EP3_FIFO_NO (HS_C1_I1_A1_EP3_BLKNO * HS_C1_I1_A1_EP3_BLKSIZE)
- #define HS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP3_BLKNO - 1) << 2) | HS_C1_I1_A1_EP3_TYPE)
- #define HS_C1_I1_A1_EP3_FIFO_MAP (((1 - HS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
- #define HS_C1_I1_A1_EP3_MAP (HS_C1_I1_A1_EP3_FIFO_START | (HS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP3_DIRECTION)))
- #endif
- #endif
-
- #if (HS_C1_I1_ALT_NUMBER == 1)
- #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH)
- #elif (HS_C1_I1_ALT_NUMBER == 2)
- #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH + HS_C1_I1_A1_EP_LENGTH)
- #endif
- #endif
-
- #if (HS_C1_INTERFACE_NUMBER == 1)
- #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH)
- #elif (HS_C1_INTERFACE_NUMBER == 2)
- #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH + HS_C1_I1_ALT_LENGTH)
- #endif
-#endif
-
-#if (FS_CONFIGURATION_NUMBER >= 1)
- // Configuration 0X01
- #define FS_C1_INTERFACE_NUMBER 0X01
- #define FS_C1 0X01
- #define FS_C1_iConfiguration 0X00
- #define FS_C1_bmAttribute 0X80
- #define FS_C1_iMaxPower 0XFA
-
- #if (FS_C1_INTERFACE_NUMBER >= 1)
- // Interface 0
- #define FS_C1_I0_ALT_NUMBER 0X01
- #if (FS_C1_I0_ALT_NUMBER >= 1)
- // AlternateSetting 0X00
- #define FS_C1_I0_A0_bInterfaceNumber 0X00
- #define FS_C1_I0_A0_bAlternateSetting 0X00
- //JWEI 2003/07/14
- //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
- #define FS_C1_I0_A0_EP_NUMBER 0x05
- //#else
- //#define FS_C1_I0_A0_EP_NUMBER 0X03
- //#endif
- #if !(fFLASH_DISK && !fFLASH_BOOT)
- #define FS_C1_I0_A0_bInterfaceClass 0XFF
- #define FS_C1_I0_A0_bInterfaceSubClass 0X00
- #define FS_C1_I0_A0_bInterfaceProtocol 0X00
- #else
- #define FS_C1_I0_A0_bInterfaceClass 0X08
- #define FS_C1_I0_A0_bInterfaceSubClass 0X06
- #define FS_C1_I0_A0_bInterfaceProtocol 0X50
- #endif
- #define FS_C1_I0_A0_iInterface 0X00
-
- #if (FS_C1_I0_A0_EP_NUMBER >= 1)
- //EP0X01
- #define FS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE
- //JWEI 2003/05/19
- #if fDOUBLE_BUF
- #define FS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK
- #else
- #define FS_C1_I0_A0_EP1_BLKNO SINGLE_BLK
- #endif
- #define FS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT
- #define FS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK
- //JWEI 2003/05/07
- #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64
- #define FS_C1_I0_A0_EP1_bInterval 00
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 2)
- //EP0X02
- #define FS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE
- //JWEI 2003/08/20
- #if fDOUBLE_BUF_IN
- #define FS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK
- #else
- #define FS_C1_I0_A0_EP2_BLKNO SINGLE_BLK
- #endif
- #define FS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN
- #define FS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK
- #define FS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_64
- #define FS_C1_I0_A0_EP2_bInterval 00
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 3)
- //EP0X03
- #define FS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE
- #define FS_C1_I0_A0_EP3_BLKNO SINGLE_BLK
- #define FS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN
- #define FS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT
- #define FS_C1_I0_A0_EP3_MAX_PACKET 0x0040
- #define FS_C1_I0_A0_EP3_bInterval 01
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
- //EP0X04
- #define FS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE
- #define FS_C1_I0_A0_EP4_BLKNO SINGLE_BLK
- #define FS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT
- #define FS_C1_I0_A0_EP4_TYPE TF_TYPE_BULK
- #define FS_C1_I0_A0_EP4_MAX_PACKET 0x0040
- #define FS_C1_I0_A0_EP4_bInterval 00
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 5)
- //EP0X04
- #define FS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE
- #if fDOUBLE_BUF_IN
- #define FS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK
- #else
- #define FS_C1_I0_A0_EP5_BLKNO SINGLE_BLK
- #endif
- #define FS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT
- #define FS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK
- #define FS_C1_I0_A0_EP5_MAX_PACKET 0x0040
- #define FS_C1_I0_A0_EP5_bInterval 00
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 6)
- //EP0X04
- #define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE
- #if fDOUBLE_BUF_IN
- #define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK
- #else
- #define FS_C1_I0_A0_EP6_BLKNO SINGLE_BLK
- #endif
- #define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT
- #define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK
- #define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040
- #define FS_C1_I0_A0_EP6_bInterval 00
- #endif
- #endif
- #endif
-#endif
-
-#if (FS_CONFIGURATION_NUMBER >= 1)
- // Configuration 1
- #if (FS_C1_INTERFACE_NUMBER >= 1)
- // Interface 0
- #if (FS_C1_I0_ALT_NUMBER >= 1)
- // AlternateSetting 0
- #define FS_C1_I0_A0_EP_LENGTH (EP_LENGTH * FS_C1_I0_A0_EP_NUMBER)
- #if (FS_C1_I0_A0_EP_NUMBER >= 1)
- // EP1
- #define FS_C1_I0_A0_EP1_FIFO_START FIFO0
- #define FS_C1_I0_A0_EP1_FIFO_NO (FS_C1_I0_A0_EP1_BLKNO * FS_C1_I0_A0_EP1_BLKSIZE)
- #define FS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP1_BLKNO - 1) << 2) | FS_C1_I0_A0_EP1_TYPE)
- #define FS_C1_I0_A0_EP1_FIFO_MAP (((1 - FS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
- #define FS_C1_I0_A0_EP1_MAP (FS_C1_I0_A0_EP1_FIFO_START | (FS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP1_DIRECTION)))
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 2)
- // EP2
- #define FS_C1_I0_A0_EP2_FIFO_START (FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO)
- #define FS_C1_I0_A0_EP2_FIFO_NO (FS_C1_I0_A0_EP2_BLKNO * FS_C1_I0_A0_EP2_BLKSIZE)
- #define FS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP2_BLKNO - 1) << 2) | FS_C1_I0_A0_EP2_TYPE)
- #define FS_C1_I0_A0_EP2_FIFO_MAP (((1 - FS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
- #define FS_C1_I0_A0_EP2_MAP (FS_C1_I0_A0_EP2_FIFO_START | (FS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP2_DIRECTION)))
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 3)
- // EP3
- //JWEI 2003/07/15
- // #define FS_C1_I0_A0_EP3_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
- #define FS_C1_I0_A0_EP3_FIFO_START FIFO14
- #define FS_C1_I0_A0_EP3_FIFO_NO (FS_C1_I0_A0_EP3_BLKNO * FS_C1_I0_A0_EP3_BLKSIZE)
- #define FS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP3_BLKNO - 1) << 2) | FS_C1_I0_A0_EP3_TYPE)
- #define FS_C1_I0_A0_EP3_FIFO_MAP (((1 - FS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
- #define FS_C1_I0_A0_EP3_MAP (FS_C1_I0_A0_EP3_FIFO_START | (FS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP3_DIRECTION)))
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
- // EP4
- #define FS_C1_I0_A0_EP4_FIFO_START (FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO)
- #define FS_C1_I0_A0_EP4_FIFO_NO (FS_C1_I0_A0_EP4_BLKNO * FS_C1_I0_A0_EP4_BLKSIZE)
- #define FS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP4_BLKNO - 1) << 2) | FS_C1_I0_A0_EP4_TYPE)
- #define FS_C1_I0_A0_EP4_FIFO_MAP (((1 - FS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
- #define FS_C1_I0_A0_EP4_MAP (FS_C1_I0_A0_EP4_FIFO_START | (FS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP4_DIRECTION)))
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 5)
- // EP5
- #define FS_C1_I0_A0_EP5_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
- #define FS_C1_I0_A0_EP5_FIFO_NO (FS_C1_I0_A0_EP5_BLKNO * FS_C1_I0_A0_EP5_BLKSIZE)
- #define FS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP5_BLKNO - 1) << 2) | FS_C1_I0_A0_EP5_TYPE)
- #define FS_C1_I0_A0_EP5_FIFO_MAP (((1 - FS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
- #define FS_C1_I0_A0_EP5_MAP (FS_C1_I0_A0_EP5_FIFO_START | (FS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP5_DIRECTION)))
- #endif
- #if (FS_C1_I0_A0_EP_NUMBER >= 6)
- // EP5
- #define FS_C1_I0_A0_EP6_FIFO_START (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO)
- #define FS_C1_I0_A0_EP6_FIFO_NO (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE)
- #define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE)
- #define FS_C1_I0_A0_EP6_FIFO_MAP (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
- #define FS_C1_I0_A0_EP6_MAP (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION)))
- #endif
- #endif
-
- #if (FS_C1_I0_ALT_NUMBER >= 2)
- // AlternateSetting 1
- #define FS_C1_I0_A1_EP_LENGTH (EP_LENGTH * FS_C1_I0_A1_EP_NUMBER)
- #if (FS_C1_I0_A1_EP_NUMBER >= 1)
- // EP1
- #define FS_C1_I0_A1_EP1_FIFO_START FIFO0
- #define FS_C1_I0_A1_EP1_FIFO_NO (FS_C1_I0_A1_EP1_BLKNO * FS_C1_I0_A1_EP1_BLKSIZE)
- #define FS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP1_BLKNO - 1) << 2) | FS_C1_I0_A1_EP1_TYPE)
- #define FS_C1_I0_A1_EP1_FIFO_MAP (((1 - FS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
- #define FS_C1_I0_A1_EP1_MAP (FS_C1_I0_A1_EP1_FIFO_START | (FS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP1_DIRECTION)))
- #endif
- #if (FS_C1_I0_A1_EP_NUMBER >= 2)
- // EP2
- #define FS_C1_I0_A1_EP2_FIFO_START (FS_C1_I0_A1_EP1_FIFO_START + FS_C1_I0_A1_EP1_FIFO_NO)
- #define FS_C1_I0_A1_EP2_FIFO_NO (FS_C1_I0_A1_EP2_BLKNO * FS_C1_I0_A1_EP2_BLKSIZE)
- #define FS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP2_BLKNO - 1) << 2) | FS_C1_I0_A1_EP2_TYPE)
- #define FS_C1_I0_A1_EP2_FIFO_MAP (((1 - FS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
- #define FS_C1_I0_A1_EP2_MAP (FS_C1_I0_A1_EP2_FIFO_START | (FS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP2_DIRECTION)))
- #endif
- #if (FS_C1_I0_A1_EP_NUMBER >= 3)
- // EP3
- #define FS_C1_I0_A1_EP3_FIFO_START (FS_C1_I0_A1_EP2_FIFO_START + FS_C1_I0_A1_EP2_FIFO_NO)
- #define FS_C1_I0_A1_EP3_FIFO_NO (FS_C1_I0_A1_EP3_BLKNO * FS_C1_I0_A1_EP3_BLKSIZE)
- #define FS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP3_BLKNO - 1) << 2) | FS_C1_I0_A1_EP3_TYPE)
- #define FS_C1_I0_A1_EP3_FIFO_MAP (((1 - FS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
- #define FS_C1_I0_A1_EP3_MAP (FS_C1_I0_A1_EP3_FIFO_START | (FS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP3_DIRECTION)))
- #endif
- #endif
-
- #if (FS_C1_I0_ALT_NUMBER == 1)
- #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH)
- #elif (FS_C1_I0_ALT_NUMBER == 2)
- #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH + FS_C1_I0_A1_EP_LENGTH)
- #endif
- #endif
-
- #if (FS_C1_INTERFACE_NUMBER >= 2)
- // Interface 1
- #if (FS_C1_I1_ALT_NUMBER >= 1)
- // AlternateSetting 0
- #define FS_C1_I1_A0_EP_LENGTH (EP_LENGTH * FS_C1_I1_A0_EP_NUMBER)
- #if (FS_C1_I1_A0_EP_NUMBER >= 1)
- // EP1
- #define FS_C1_I1_A0_EP1_FIFO_START FIFO0
- #define FS_C1_I1_A0_EP1_FIFO_NO (FS_C1_I1_A0_EP1_BLKNO * FS_C1_I1_A0_EP1_BLKSIZE)
- #define FS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP1_BLKNO - 1) << 2) | FS_C1_I1_A0_EP1_TYPE)
- #define FS_C1_I1_A0_EP1_FIFO_MAP (((1 - FS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
- #define FS_C1_I1_A0_EP1_MAP (FS_C1_I1_A0_EP1_FIFO_START | (FS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP1_DIRECTION)))
- #endif
- #if (FS_C1_I1_A0_EP_NUMBER >= 2)
- // EP2
- #define FS_C1_I1_A0_EP2_FIFO_START (FS_C1_I1_A0_EP1_FIFO_START + FS_C1_I1_A0_EP1_FIFO_NO)
- #define FS_C1_I1_A0_EP2_FIFO_NO (FS_C1_I1_A0_EP2_BLKNO * FS_C1_I1_A0_EP2_BLKSIZE)
- #define FS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP2_BLKNO - 1) << 2) | FS_C1_I1_A0_EP2_TYPE)
- #define FS_C1_I1_A0_EP2_FIFO_MAP (((1 - FS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
- #define FS_C1_I1_A0_EP2_MAP (FS_C1_I1_A0_EP2_FIFO_START | (FS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP2_DIRECTION)))
- #endif
- #if (FS_C1_I1_A0_EP_NUMBER >= 3)
- // EP3
- #define FS_C1_I1_A0_EP3_FIFO_START (FS_C1_I1_A0_EP2_FIFO_START + FS_C1_I1_A0_EP2_FIFO_NO)
- #define FS_C1_I1_A0_EP3_FIFO_NO (FS_C1_I1_A0_EP3_BLKNO * FS_C1_I1_A0_EP3_BLKSIZE)
- #define FS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP3_BLKNO - 1) << 2) | FS_C1_I1_A0_EP3_TYPE)
- #define FS_C1_I1_A0_EP3_FIFO_MAP (((1 - FS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
- #define FS_C1_I1_A0_EP3_MAP (FS_C1_I1_A0_EP3_FIFO_START | (FS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP3_DIRECTION)))
- #endif
- #endif
-
- #if (FS_C1_I1_ALT_NUMBER >= 2)
- // AlternateSetting 1
- #define FS_C1_I1_A1_EP_LENGTH (EP_LENGTH * FS_C1_I1_A1_EP_NUMBER)
- #if (FS_C1_I1_A1_EP_NUMBER >= 1)
- // EP1
- #define FS_C1_I1_A1_EP1_FIFO_START FIFO0
- #define FS_C1_I1_A1_EP1_FIFO_NO (FS_C1_I1_A1_EP1_BLKNO * FS_C1_I1_A1_EP1_BLKSIZE)
- #define FS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP1_BLKNO - 1) << 2) | FS_C1_I1_A1_EP1_TYPE)
- #define FS_C1_I1_A1_EP1_FIFO_MAP (((1 - FS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
- #define FS_C1_I1_A1_EP1_MAP (FS_C1_I1_A1_EP1_FIFO_START | (FS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP1_DIRECTION)))
- #endif
- #if (FS_C1_I1_A1_EP_NUMBER >= 2)
- // EP2
- #define FS_C1_I1_A1_EP2_FIFO_START (FS_C1_I1_A1_EP1_FIFO_START + FS_C1_I1_A1_EP1_FIFO_NO)
- #define FS_C1_I1_A1_EP2_FIFO_NO (FS_C1_I1_A1_EP2_BLKNO * FS_C1_I1_A1_EP2_BLKSIZE)
- #define FS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP2_BLKNO - 1) << 2) | FS_C1_I1_A1_EP2_TYPE)
- #define FS_C1_I1_A1_EP2_FIFO_MAP (((1 - FS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
- #define FS_C1_I1_A1_EP2_MAP (FS_C1_I1_A1_EP2_FIFO_START | (FS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP2_DIRECTION)))
- #endif
- #if (FS_C1_I1_A1_EP_NUMBER >= 3)
- // EP3
- #define FS_C1_I1_A1_EP3_FIFO_START (FS_C1_I1_A1_EP2_FIFO_START + FS_C1_I1_A1_EP2_FIFO_NO)
- #define FS_C1_I1_A1_EP3_FIFO_NO (FS_C1_I1_A1_EP3_BLKNO * FS_C1_I1_A1_EP3_BLKSIZE)
- #define FS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP3_BLKNO - 1) << 2) | FS_C1_I1_A1_EP3_TYPE)
- #define FS_C1_I1_A1_EP3_FIFO_MAP (((1 - FS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
- #define FS_C1_I1_A1_EP3_MAP (FS_C1_I1_A1_EP3_FIFO_START | (FS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP3_DIRECTION)))
- #endif
- #endif
-
- #if (FS_C1_I1_ALT_NUMBER == 1)
- #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH)
- #elif (FS_C1_I1_ALT_NUMBER == 2)
- #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH + FS_C1_I1_A1_EP_LENGTH)
- #endif
- #endif
-
- #if (FS_C1_INTERFACE_NUMBER == 1)
- #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH)
- #elif (FS_C1_INTERFACE_NUMBER == 2)
- #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH + HS_FS_C1_I1_ALT_LENGTH)
- #endif
-#endif
-
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define USB_ENABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable
-
-#define USB_DISABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable
-
-#define USB_UP_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))) // upQ stream mode
-
-#define USB_UP_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3)) // upQ packet mode
-
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define USB_ENABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1)) // lp downstream DMA enable
-
-#define USB_DISABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))) // lp downstream DMA disable
-
-#define USB_LP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT6))) // lpQ packet mode
-
-#define USB_LP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6)) // lpQ stream mode
-
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable
-
-#define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable
-
-#define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7))) // hpQ packet mode
-
-#define USB_HP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7)) // hpQ stream mode
-
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable
-
-#define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable
-
-#define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10))) // hpQ packet mode
-
-#define USB_MP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10)) // hpQ stream mode
-
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define USB_ENABLE_UP_PACKET_MODE() USB_DISABLE_UP_DMA(); \
- USB_UP_PACKET_MODE(); \
- USB_ENABLE_UP_DMA();
-
-#define USB_ENABLE_LP_DN_PACKET_MODE() USB_DISABLE_LP_DN_DMA(); \
- USB_LP_DN_PACKET_MODE(); \
- USB_ENABLE_LP_DN_DMA()
-
-#define USB_ENABLE_MP_DN_PACKET_MODE() USB_DISABLE_MP_DN_DMA(); \
- USB_MP_DN_PACKET_MODE(); \
- USB_ENABLE_MP_DN_DMA();
-
-#define USB_ENABLE_HP_DN_PACKET_MODE() USB_DISABLE_HP_DN_DMA(); \
- USB_HP_DN_PACKET_MODE(); \
- USB_ENABLE_HP_DN_DMA();
-
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define USB_ENABLE_UP_STREAM_MODE() USB_DISABLE_UP_DMA(); \
- USB_UP_STREAM_MODE(); \
- USB_ENABLE_UP_DMA();
-
-#define USB_ENABLE_LP_DN_STREAM_MODE() USB_DISABLE_LP_DN_DMA(); \
- USB_LP_DN_STREAM_MODE(); \
- USB_ENABLE_LP_DN_DMA()
-
-#define USB_ENABLE_MP_DN_STREAM_MODE() USB_DISABLE_MP_DN_DMA(); \
- USB_MP_DN_STREAM_MODE(); \
- USB_ENABLE_MP_DN_DMA();
-
-#define USB_ENABLE_HP_DN_STREAM_MODE() USB_DISABLE_HP_DN_DMA(); \
- USB_HP_DN_STREAM_MODE(); \
- USB_ENABLE_HP_DN_DMA();
-
-#define USB_STREAM_HOST_BUF_SIZE(size) USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size)));
-#define USB_STREAM_TIMEOUT(time_cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt); // set stream mode timeout critirea
-#define USB_STREAM_AGG_PKT_CNT(cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea
-
-#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Qualcomm Atheros nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef USB_DEFS_H
+#define USB_DEFS_H
+
+#include "usb_table.h"
+#include "dt_defs.h"
+#include "reg_defs.h"
+
+#define CHECK_SWITCH_BY_BOOTCODE 1 //to be verified for ZD1215, OK for ZD1211
+#define VERIFY_CHECKSUM_BY_BOOTCODE 1
+
+/***********************************************************************/
+/* for SEEPROM Boot */
+/***********************************************************************/
+#define WLAN_BOOT_SIGNATURE (0x19710303)
+
+#define WLAN_SIGNATURE_ADDR (0x102000)
+
+#define cMAX_ADDR 0x10000
+
+#define cEEPROM_SIZE 0x800 // 2k word (4k byte)
+
+#define cRESERVE_LOAD_SPACE 0
+
+// start addr. of boot code
+#define cBOOT_CODE_ADDR (cMAX_ADDR - cEEPROM_SIZE) // 0xF800
+
+/************************** Register Addr Process *********************/
+#define mpADDR(addr) ((volatile uint16_t*) (addr))
+#define mADDR(addr) (*mpADDR(addr))
+#define muADDR(addr) ((uint16_t) (&(addr)))
+
+#define USB_BYTE_REG_WRITE(addr, val) HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val))
+#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3))
+//#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr))
+
+#define USB_HALF_WORD_REG_WRITE(addr, val) HAL_HALF_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr), (val))
+#define USB_HALF_WORD_REG_READ(addr) HAL_HALF_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr))
+
+#define USB_WORD_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val))
+#define USB_WORD_REG_READ(addr) HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr))
+
+
+/************************** Register Deinition ***************************/
+//#define USB_BASE_ADDR_SOC 0x8000
+
+//#define SOC_Reg mpADDR(USB_BASE_ADDR_SOC)
+
+#define cSOC_USB_OFST (0x100)
+
+#define ZM_CBUS_FIFO_SIZE_OFFSET (cSOC_USB_OFST) //OFFSET 0
+
+#define cSOC_CBUS_CTL_OFFSET 0xF0
+
+#define ZM_FUSB_BASE USB_CTRL_BASE_ADDRESS
+
+#define ZM_MAIN_CTRL_OFFSET 0x00
+#define ZM_DEVICE_ADDRESS_OFFSET 0x01
+#define ZM_TEST_OFFSET 0x02
+#define ZM_PHY_TEST_SELECT_OFFSET 0x08
+#define ZM_VDR_SPECIFIC_MODE_OFFSET 0x0A
+#define ZM_CX_CONFIG_STATUS_OFFSET 0x0B
+#define ZM_EP0_DATA1_OFFSET 0x0C
+#define ZM_EP0_DATA2_OFFSET 0x0D
+#define ZM_EP0_DATA_OFFSET 0x0C
+
+#define ZM_INTR_MASK_BYTE_0_OFFSET 0x11
+#define ZM_INTR_MASK_BYTE_1_OFFSET 0x12
+#define ZM_INTR_MASK_BYTE_2_OFFSET 0x13
+#define ZM_INTR_MASK_BYTE_3_OFFSET 0x14
+#define ZM_INTR_MASK_BYTE_4_OFFSET 0x15
+#define ZM_INTR_MASK_BYTE_5_OFFSET 0x16
+#define ZM_INTR_MASK_BYTE_6_OFFSET 0x17
+#define ZM_INTR_MASK_BYTE_7_OFFSET 0x18
+
+#define ZM_INTR_GROUP_OFFSET 0x20
+#define ZM_INTR_SOURCE_0_OFFSET 0x21
+#define ZM_INTR_SOURCE_1_OFFSET 0x22
+#define ZM_INTR_SOURCE_2_OFFSET 0x23
+#define ZM_INTR_SOURCE_3_OFFSET 0x24
+#define ZM_INTR_SOURCE_4_OFFSET 0x25
+#define ZM_INTR_SOURCE_5_OFFSET 0x26
+#define ZM_INTR_SOURCE_6_OFFSET 0x27
+#define ZM_INTR_SOURCE_7_OFFSET 0x28
+
+#define ZM_EP_IN_MAX_SIZE_HIGH_OFFSET 0x3F
+#define ZM_EP_IN_MAX_SIZE_LOW_OFFSET 0x3E
+
+#define ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET 0x5F
+#define ZM_EP_OUT_MAX_SIZE_LOW_OFFSET 0x5E
+
+#define ZM_EP3_BYTE_COUNT_HIGH_OFFSET 0xAE
+#define ZM_EP3_BYTE_COUNT_LOW_OFFSET 0xBE
+#define ZM_EP4_BYTE_COUNT_HIGH_OFFSET 0xAF
+#define ZM_EP4_BYTE_COUNT_LOW_OFFSET 0xBF
+
+#define ZM_EP3_DATA_OFFSET 0xF8
+#define ZM_EP4_DATA_OFFSET 0xFC
+
+#define ZM_SOC_USB_MODE_CTRL_OFFSET 0x108
+#define ZM_SOC_USB_MAX_AGGREGATE_OFFSET 0x110
+#define ZM_SOC_USB_TIME_CTRL_OFFSET 0x114
+#define ZM_SOC_USB_DMA_RESET_OFFSET 0x118
+
+#define ZM_ADDR_CONV 0x0
+
+#define ZM_CBUS_FIFO_SIZE_REG (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_CBUS_CTRL_REG (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_MAIN_CTRL_REG (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_DEVICE_ADDRESS_REG (ZM_DEVICE_ADDRESS_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_TEST_REG (ZM_TEST_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_PHY_TEST_SELECT_REG (ZM_PHY_TEST_SELECT_OFFSET^ZM_ADDR_CONV)))
+
+#define ZM_CX_CONFIG_STATUS_REG (ZM_CX_CONFIG_STATUS_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_EP0_DATA1_REG (ZM_EP0_DATA1_OFFSET^ZM_ADDR_CONV)))
+
+#define ZM_EP0_DATA2_REG (ZM_EP0_DATA2_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_EP0_DATA_REG (ZM_EP0_DATA_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_MASK_BYTE_0_REG (ZM_INTR_MASK_BYTE_0_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_MASK_BYTE_1_REG (ZM_INTR_MASK_BYTE_1_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_MASK_BYTE_2_REG (ZM_INTR_MASK_BYTE_2_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_MASK_BYTE_3_REG (ZM_INTR_MASK_BYTE_3_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_MASK_BYTE_4_REG (ZM_INTR_MASK_BYTE_4_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_MASK_BYTE_5_REG (ZM_INTR_MASK_BYTE_5_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_MASK_BYTE_6_REG (ZM_INTR_MASK_BYTE_6_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_MASK_BYTE_7_REG (ZM_INTR_MASK_BYTE_7_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_SOURCE_0_REG (ZM_INTR_SOURCE_0_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_SOURCE_1_REG (ZM_INTR_SOURCE_1_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_SOURCE_2_REG (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_SOURCE_3_REG (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_SOURCE_4_REG (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_SOURCE_5_REG (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_SOURCE_6_REG (ZM_INTR_SOURCE_6_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_SOURCE_7_REG (ZM_INTR_SOURCE_7_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_INTR_GROUP_REG (ZM_INTR_GROUP_OFFSET^ZM_ADDR_CONV)))
+
+#define ZM_EP3_BYTE_COUNT_HIGH_REG (ZM_EP3_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_EP3_BYTE_COUNT_LOW_REG (ZM_EP3_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_EP4_BYTE_COUNT_HIGH_REG (ZM_EP4_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_EP4_BYTE_COUNT_LOW_REG (ZM_EP4_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
+
+#define ZM_EP3_DATA_REG (ZM_EP3_DATA_OFFSET)
+
+#define ZM_EP4_DATA_REG (ZM_EP4_DATA_OFFSET)
+
+#define ZM_SOC_USB_MODE_CTRL_REG (ZM_SOC_USB_MODE_CTRL_OFFSET)
+
+#define ZM_SOC_USB_MAX_AGGREGATE_REG (ZM_SOC_USB_MAX_AGGREGATE_OFFSET)
+
+#define ZM_SOC_USB_TIME_CTRL_REG (ZM_SOC_USB_TIME_CTRL_OFFSET)
+
+#define bmHIGH_SPEED BIT6
+#define bmCWR_BUF_END BIT1
+
+#define mUsbEP0DataRd1() (USB_BYTE_REG_READ(ZM_EP0_DATA1_OFFSET))
+//#define mUsbEP0DataRd2() ZM_EP0_DATA2_REG
+//#define mUsbEP0DataRd3() ZM_EP0_DATA3_REG
+//#define mUsbEP0DataRd4() ZM_EP0_DATA4_REG
+#define mUsbEP0DataWr1(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA1_OFFSET, data))
+#define mUsbEP0DataWr2(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA2_OFFSET, data))
+
+#define mGetByte0(data) ( data & 0xff )
+#define mGetByte1(data) ( (data >> 8) & 0xff )
+#define mGetByte2(data) ( (data >> 16) & 0xff )
+#define mGetByte3(data) ( (data >> 24) & 0xff )
+
+//#define mUsbHighSpeedST() (ZM_MAIN_CTRL_REG & BIT6)
+//#define mUsbCfgST() (ZM_DEVICE_ADDRESS_REG & BIT7)
+//#define mUsbApWrEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
+//#define mUsbApRdEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
+
+#define mUsbHighSpeedST() (USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET) & BIT6)
+#define mUsbCfgST() (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET) & BIT7)
+#define mUsbApWrEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
+#define mUsbApRdEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
+
+#define mUsbRmWkupST() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
+ USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT0)
+#define mUsbRmWkupClr() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
+ USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0)
+#define mUsbRmWkupSet() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
+ USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0)
+
+#define mUsbGlobIntEnable() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
+ USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2)
+
+#define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
+ USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f)
+#define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
+ USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)|0xc0)
+#define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
+ USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf)
+#define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
+ USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0)
+// USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0x40)
+
+#define mUSB_EP3_XFER_DONE() USB_BYTE_REG_WRITE(ZM_EP3_BYTE_COUNT_HIGH_OFFSET, \
+ USB_BYTE_REG_READ(ZM_EP3_BYTE_COUNT_HIGH_OFFSET)|0x08)
+
+
+
+#define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512
+#define HS_C1_I0_A0_EP1_bInterval 00
+
+#define HS_C1_I0_A0_EP_NUMBER 0x06
+#define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
+#define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH)
+#define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH)
+
+#define HS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + HS_C1_INTERFACE_LENGTH)
+#define FS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + FS_C1_INTERFACE_LENGTH)
+
+#define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64
+//#define FS_C1_I0_A0_EP1_bInterval HS_C1_I0_A0_EP1_bInterval
+
+#define HS_CONFIGURATION_NUMBER 1
+#define FS_CONFIGURATION_NUMBER 1
+
+#define fDOUBLE_BUF 1
+#define fDOUBLE_BUF_IN 1
+
+#define fFLASH_DISK 0
+#define fENABLE_ISO 0
+
+#if (HS_CONFIGURATION_NUMBER >= 1)
+ // Configuration 0X01
+ #define HS_C1_INTERFACE_NUMBER 0x01
+ #define HS_C1 0x01
+ #define HS_C1_iConfiguration 0x00
+ #define HS_C1_bmAttribute 0x80
+ #if !(fFLASH_DISK && !fFLASH_BOOT)
+ #define HS_C1_iMaxPower 0xFA
+ #else
+ #define HS_C1_iMaxPower 0x32
+ #endif
+
+ #if (HS_C1_INTERFACE_NUMBER >= 1)
+ // Interface 0
+ #define HS_C1_I0_ALT_NUMBER 0X01
+ #if (HS_C1_I0_ALT_NUMBER >= 1)
+ // AlternateSetting 0X00
+ #define HS_C1_I0_A0_bInterfaceNumber 0X00
+ #define HS_C1_I0_A0_bAlternateSetting 0X00
+ //JWEI 2003/07/14
+ //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
+ #define HS_C1_I0_A0_EP_NUMBER 0x06
+ //#else
+ //#define HS_C1_I0_A0_EP_NUMBER 0X03
+ //#endif
+ #if !(fFLASH_DISK && !fFLASH_BOOT)
+ #define HS_C1_I0_A0_bInterfaceClass 0XFF
+ #define HS_C1_I0_A0_bInterfaceSubClass 0X00
+ #define HS_C1_I0_A0_bInterfaceProtocol 0X00
+ #else
+ #define HS_C1_I0_A0_bInterfaceClass 0X08
+ #define HS_C1_I0_A0_bInterfaceSubClass 0X06
+ #define HS_C1_I0_A0_bInterfaceProtocol 0X50
+ #endif
+ #define HS_C1_I0_A0_iInterface 0X00
+
+ #if (HS_C1_I0_A0_EP_NUMBER >= 1)
+ //EP0X01
+ #define HS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE
+ //JWEI 2003/05/19
+ #if fDOUBLE_BUF
+ #define HS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK
+ #else
+ #define HS_C1_I0_A0_EP1_BLKNO SINGLE_BLK
+ #endif
+ #define HS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT
+ #define HS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK
+ //JWEI 2003/05/07
+ #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512
+ #define HS_C1_I0_A0_EP1_bInterval 00
+ #endif
+ #if (HS_C1_I0_A0_EP_NUMBER >= 2)
+ //EP0X02
+ #define HS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE
+ //JWEI 2003/08/20
+ #if fDOUBLE_BUF_IN
+ #define HS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK
+ #else
+ #define HS_C1_I0_A0_EP2_BLKNO SINGLE_BLK
+ #endif
+ #define HS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN
+ #define HS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK
+ #define HS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_512
+ #define HS_C1_I0_A0_EP2_bInterval 00
+ #endif
+ #if (HS_C1_I0_A0_EP_NUMBER >= 3)
+ //EP0X03
+ #define HS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE
+ #define HS_C1_I0_A0_EP3_BLKNO SINGLE_BLK
+ #define HS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN
+ #define HS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT
+ #define HS_C1_I0_A0_EP3_MAX_PACKET 0x0040
+ #define HS_C1_I0_A0_EP3_bInterval 01
+ #endif
+ // Note: HS Bulk type require max pkt size = 512
+ // ==> must use Interrupt type for max pkt size = 64
+ #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
+ //EP0X04
+ #define HS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE
+ #define HS_C1_I0_A0_EP4_BLKNO SINGLE_BLK
+ #define HS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT
+ #define HS_C1_I0_A0_EP4_TYPE TF_TYPE_INTERRUPT
+ #define HS_C1_I0_A0_EP4_MAX_PACKET 0x0040
+ #define HS_C1_I0_A0_EP4_bInterval 01
+ #endif
+ #if (HS_C1_I0_A0_EP_NUMBER >= 5)
+ //EP0X04
+ #define HS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE
+ #if fDOUBLE_BUF
+ #define HS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK
+ #else
+ #define HS_C1_I0_A0_EP5_BLKNO SINGLE_BLK
+ #endif
+ #define HS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT
+ #define HS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK
+ #define HS_C1_I0_A0_EP5_MAX_PACKET MX_PA_SZ_512
+ #define HS_C1_I0_A0_EP5_bInterval 00
+ #endif
+ #if (HS_C1_I0_A0_EP_NUMBER >= 6)
+ //EP0X04
+ #define HS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE
+ #if fDOUBLE_BUF
+ #define HS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK
+ #else
+ #define HS_C1_I0_A0_EP6_BLKNO SINGLE_BLK
+ #endif
+ #define HS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT
+ #define HS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK
+ #define HS_C1_I0_A0_EP6_MAX_PACKET MX_PA_SZ_512
+ #define HS_C1_I0_A0_EP6_bInterval 00
+ #endif
+ #endif
+ #endif
+#endif
+
+#if (HS_CONFIGURATION_NUMBER >= 1)
+ // Configuration 1
+ #if (HS_C1_INTERFACE_NUMBER >= 1)
+ // Interface 0
+ #if (HS_C1_I0_ALT_NUMBER >= 1)
+ // AlternateSetting 0
+ #define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
+ #if (HS_C1_I0_A0_EP_NUMBER >= 1)
+ // EP1
+ #define HS_C1_I0_A0_EP1_FIFO_START FIFO0
+ #define HS_C1_I0_A0_EP1_FIFO_NO (HS_C1_I0_A0_EP1_BLKNO * HS_C1_I0_A0_EP1_BLKSIZE)
+ #define HS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP1_BLKNO - 1) << 2) | HS_C1_I0_A0_EP1_TYPE)
+ #define HS_C1_I0_A0_EP1_FIFO_MAP (((1 - HS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
+ #define HS_C1_I0_A0_EP1_MAP (HS_C1_I0_A0_EP1_FIFO_START | (HS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP1_DIRECTION)))
+ #endif
+ #if (HS_C1_I0_A0_EP_NUMBER >= 2)
+ // EP2
+ #if fDOUBLE_BUF
+ #define HS_C1_I0_A0_EP2_FIFO_START (HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO)
+ #else
+ #define HS_C1_I0_A0_EP2_FIFO_START FIFO2
+ #endif
+ #define HS_C1_I0_A0_EP2_FIFO_NO (HS_C1_I0_A0_EP2_BLKNO * HS_C1_I0_A0_EP2_BLKSIZE)
+ #define HS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP2_BLKNO - 1) << 2) | HS_C1_I0_A0_EP2_TYPE)
+ #define HS_C1_I0_A0_EP2_FIFO_MAP (((1 - HS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
+ #define HS_C1_I0_A0_EP2_MAP (HS_C1_I0_A0_EP2_FIFO_START | (HS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP2_DIRECTION)))
+ #endif
+ #if (HS_C1_I0_A0_EP_NUMBER >= 3)
+ // EP3
+ //JWEI 2003/07/15
+ // #define HS_C1_I0_A0_EP3_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
+ #define HS_C1_I0_A0_EP3_FIFO_START FIFO14
+ #define HS_C1_I0_A0_EP3_FIFO_NO (HS_C1_I0_A0_EP3_BLKNO * HS_C1_I0_A0_EP3_BLKSIZE)
+ #define HS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP3_BLKNO - 1) << 2) | HS_C1_I0_A0_EP3_TYPE)
+ #define HS_C1_I0_A0_EP3_FIFO_MAP (((1 - HS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
+ #define HS_C1_I0_A0_EP3_MAP (HS_C1_I0_A0_EP3_FIFO_START | (HS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP3_DIRECTION)))
+ #endif
+ #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
+ // EP4
+ #define HS_C1_I0_A0_EP4_FIFO_START (HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO)
+ #define HS_C1_I0_A0_EP4_FIFO_NO (HS_C1_I0_A0_EP4_BLKNO * HS_C1_I0_A0_EP4_BLKSIZE)
+ #define HS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP4_BLKNO - 1) << 2) | HS_C1_I0_A0_EP4_TYPE)
+ #define HS_C1_I0_A0_EP4_FIFO_MAP (((1 - HS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
+ #define HS_C1_I0_A0_EP4_MAP (HS_C1_I0_A0_EP4_FIFO_START | (HS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP4_DIRECTION)))
+ #endif
+ #if (HS_C1_I0_A0_EP_NUMBER >= 5)
+ // EP5
+ #define HS_C1_I0_A0_EP5_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
+ #define HS_C1_I0_A0_EP5_FIFO_NO (HS_C1_I0_A0_EP5_BLKNO * HS_C1_I0_A0_EP5_BLKSIZE)
+ #define HS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP5_BLKNO - 1) << 2) | HS_C1_I0_A0_EP5_TYPE)
+ #define HS_C1_I0_A0_EP5_FIFO_MAP (((1 - HS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
+ #define HS_C1_I0_A0_EP5_MAP (HS_C1_I0_A0_EP5_FIFO_START | (HS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP5_DIRECTION)))
+ #endif
+ #if (HS_C1_I0_A0_EP_NUMBER >= 6)
+ // EP5
+ #define HS_C1_I0_A0_EP6_FIFO_START (HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO)
+ #define HS_C1_I0_A0_EP6_FIFO_NO (HS_C1_I0_A0_EP6_BLKNO * HS_C1_I0_A0_EP6_BLKSIZE)
+ #define HS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP6_BLKNO - 1) << 2) | HS_C1_I0_A0_EP6_TYPE)
+ #define HS_C1_I0_A0_EP6_FIFO_MAP (((1 - HS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
+ #define HS_C1_I0_A0_EP6_MAP (HS_C1_I0_A0_EP6_FIFO_START | (HS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP6_DIRECTION)))
+ #endif
+ #endif
+
+ #if (HS_C1_I0_ALT_NUMBER >= 2)
+ // AlternateSetting 1
+ #define HS_C1_I0_A1_EP_LENGTH (EP_LENGTH * HS_C1_I0_A1_EP_NUMBER)
+ #if (HS_C1_I0_A1_EP_NUMBER >= 1)
+ // EP1
+ #define HS_C1_I0_A1_EP1_FIFO_START FIFO0
+ #define HS_C1_I0_A1_EP1_FIFO_NO (HS_C1_I0_A1_EP1_BLKNO * HS_C1_I0_A1_EP1_BLKSIZE)
+ #define HS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP1_BLKNO - 1) << 2) | HS_C1_I0_A1_EP1_TYPE)
+ #define HS_C1_I0_A1_EP1_FIFO_MAP (((1 - HS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
+ #define HS_C1_I0_A1_EP1_MAP (HS_C1_I0_A1_EP1_FIFO_START | (HS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP1_DIRECTION)))
+ #endif
+ #if (HS_C1_I0_A1_EP_NUMBER >= 2)
+ // EP2
+ #define HS_C1_I0_A1_EP2_FIFO_START (HS_C1_I0_A1_EP1_FIFO_START + HS_C1_I0_A1_EP1_FIFO_NO)
+ #define HS_C1_I0_A1_EP2_FIFO_NO (HS_C1_I0_A1_EP2_BLKNO * HS_C1_I0_A1_EP2_BLKSIZE)
+ #define HS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP2_BLKNO - 1) << 2) | HS_C1_I0_A1_EP2_TYPE)
+ #define HS_C1_I0_A1_EP2_FIFO_MAP (((1 - HS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
+ #define HS_C1_I0_A1_EP2_MAP (HS_C1_I0_A1_EP2_FIFO_START | (HS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP2_DIRECTION)))
+ #endif
+ #if (HS_C1_I0_A1_EP_NUMBER >= 3)
+ // EP3
+ #define HS_C1_I0_A1_EP3_FIFO_START (HS_C1_I0_A1_EP2_FIFO_START + HS_C1_I0_A1_EP2_FIFO_NO)
+ #define HS_C1_I0_A1_EP3_FIFO_NO (HS_C1_I0_A1_EP3_BLKNO * HS_C1_I0_A1_EP3_BLKSIZE)
+ #define HS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP3_BLKNO - 1) << 2) | HS_C1_I0_A1_EP3_TYPE)
+ #define HS_C1_I0_A1_EP3_FIFO_MAP (((1 - HS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
+ #define HS_C1_I0_A1_EP3_MAP (HS_C1_I0_A1_EP3_FIFO_START | (HS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP3_DIRECTION)))
+ #endif
+ #endif
+
+ #if (HS_C1_I0_ALT_NUMBER == 1)
+ #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH)
+ #elif (HS_C1_I0_ALT_NUMBER == 2)
+ #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH + HS_C1_I0_A1_EP_LENGTH)
+ #endif
+ #endif
+
+ #if (HS_C1_INTERFACE_NUMBER >= 2)
+ // Interface 1
+ #if (HS_C1_I1_ALT_NUMBER >= 1)
+ // AlternateSetting 0
+ #define HS_C1_I1_A0_EP_LENGTH (EP_LENGTH * HS_C1_I1_A0_EP_NUMBER)
+ #if (HS_C1_I1_A0_EP_NUMBER >= 1)
+ // EP1
+ #define HS_C1_I1_A0_EP1_FIFO_START FIFO0
+ #define HS_C1_I1_A0_EP1_FIFO_NO (HS_C1_I1_A0_EP1_BLKNO * HS_C1_I1_A0_EP1_BLKSIZE)
+ #define HS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP1_BLKNO - 1) << 2) | HS_C1_I1_A0_EP1_TYPE)
+ #define HS_C1_I1_A0_EP1_FIFO_MAP (((1 - HS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
+ #define HS_C1_I1_A0_EP1_MAP (HS_C1_I1_A0_EP1_FIFO_START | (HS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP1_DIRECTION)))
+ #endif
+ #if (HS_C1_I1_A0_EP_NUMBER >= 2)
+ // EP2
+ #define HS_C1_I1_A0_EP2_FIFO_START (HS_C1_I1_A0_EP1_FIFO_START + HS_C1_I1_A0_EP1_FIFO_NO)
+ #define HS_C1_I1_A0_EP2_FIFO_NO (HS_C1_I1_A0_EP2_BLKNO * HS_C1_I1_A0_EP2_BLKSIZE)
+ #define HS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP2_BLKNO - 1) << 2) | HS_C1_I1_A0_EP2_TYPE)
+ #define HS_C1_I1_A0_EP2_FIFO_MAP (((1 - HS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
+ #define HS_C1_I1_A0_EP2_MAP (HS_C1_I1_A0_EP2_FIFO_START | (HS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP2_DIRECTION)))
+ #endif
+ #if (HS_C1_I1_A0_EP_NUMBER >= 3)
+ // EP3
+ #define HS_C1_I1_A0_EP3_FIFO_START (HS_C1_I1_A0_EP2_FIFO_START + HS_C1_I1_A0_EP2_FIFO_NO)
+ #define HS_C1_I1_A0_EP3_FIFO_NO (HS_C1_I1_A0_EP3_BLKNO * HS_C1_I1_A0_EP3_BLKSIZE)
+ #define HS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP3_BLKNO - 1) << 2) | HS_C1_I1_A0_EP3_TYPE)
+ #define HS_C1_I1_A0_EP3_FIFO_MAP (((1 - HS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
+ #define HS_C1_I1_A0_EP3_MAP (HS_C1_I1_A0_EP3_FIFO_START | (HS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP3_DIRECTION)))
+ #endif
+ #endif
+
+ #if (HS_C1_I1_ALT_NUMBER >= 2)
+ // AlternateSetting 1
+ #define HS_C1_I1_A1_EP_LENGTH (EP_LENGTH * HS_C1_I1_A1_EP_NUMBER)
+ #if (HS_C1_I1_A1_EP_NUMBER >= 1)
+ // EP1
+ #define HS_C1_I1_A1_EP1_FIFO_START FIFO0
+ #define HS_C1_I1_A1_EP1_FIFO_NO (HS_C1_I1_A1_EP1_BLKNO * HS_C1_I1_A1_EP1_BLKSIZE)
+ #define HS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP1_BLKNO - 1) << 2) | HS_C1_I1_A1_EP1_TYPE)
+ #define HS_C1_I1_A1_EP1_FIFO_MAP (((1 - HS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
+ #define HS_C1_I1_A1_EP1_MAP (HS_C1_I1_A1_EP1_FIFO_START | (HS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP1_DIRECTION)))
+ #endif
+ #if (HS_C1_I1_A1_EP_NUMBER >= 2)
+ // EP2
+ #define HS_C1_I1_A1_EP2_FIFO_START (HS_C1_I1_A1_EP1_FIFO_START + HS_C1_I1_A1_EP1_FIFO_NO)
+ #define HS_C1_I1_A1_EP2_FIFO_NO (HS_C1_I1_A1_EP2_BLKNO * HS_C1_I1_A1_EP2_BLKSIZE)
+ #define HS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP2_BLKNO - 1) << 2) | HS_C1_I1_A1_EP2_TYPE)
+ #define HS_C1_I1_A1_EP2_FIFO_MAP (((1 - HS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
+ #define HS_C1_I1_A1_EP2_MAP (HS_C1_I1_A1_EP2_FIFO_START | (HS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP2_DIRECTION)))
+ #endif
+ #if (HS_C1_I1_A1_EP_NUMBER >= 3)
+ // EP3
+ #define HS_C1_I1_A1_EP3_FIFO_START (HS_C1_I1_A1_EP2_FIFO_START + HS_C1_I1_A1_EP2_FIFO_NO)
+ #define HS_C1_I1_A1_EP3_FIFO_NO (HS_C1_I1_A1_EP3_BLKNO * HS_C1_I1_A1_EP3_BLKSIZE)
+ #define HS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP3_BLKNO - 1) << 2) | HS_C1_I1_A1_EP3_TYPE)
+ #define HS_C1_I1_A1_EP3_FIFO_MAP (((1 - HS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
+ #define HS_C1_I1_A1_EP3_MAP (HS_C1_I1_A1_EP3_FIFO_START | (HS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP3_DIRECTION)))
+ #endif
+ #endif
+
+ #if (HS_C1_I1_ALT_NUMBER == 1)
+ #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH)
+ #elif (HS_C1_I1_ALT_NUMBER == 2)
+ #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH + HS_C1_I1_A1_EP_LENGTH)
+ #endif
+ #endif
+
+ #if (HS_C1_INTERFACE_NUMBER == 1)
+ #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH)
+ #elif (HS_C1_INTERFACE_NUMBER == 2)
+ #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH + HS_C1_I1_ALT_LENGTH)
+ #endif
+#endif
+
+#if (FS_CONFIGURATION_NUMBER >= 1)
+ // Configuration 0X01
+ #define FS_C1_INTERFACE_NUMBER 0X01
+ #define FS_C1 0X01
+ #define FS_C1_iConfiguration 0X00
+ #define FS_C1_bmAttribute 0X80
+ #define FS_C1_iMaxPower 0XFA
+
+ #if (FS_C1_INTERFACE_NUMBER >= 1)
+ // Interface 0
+ #define FS_C1_I0_ALT_NUMBER 0X01
+ #if (FS_C1_I0_ALT_NUMBER >= 1)
+ // AlternateSetting 0X00
+ #define FS_C1_I0_A0_bInterfaceNumber 0X00
+ #define FS_C1_I0_A0_bAlternateSetting 0X00
+ //JWEI 2003/07/14
+ //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
+ #define FS_C1_I0_A0_EP_NUMBER 0x05
+ //#else
+ //#define FS_C1_I0_A0_EP_NUMBER 0X03
+ //#endif
+ #if !(fFLASH_DISK && !fFLASH_BOOT)
+ #define FS_C1_I0_A0_bInterfaceClass 0XFF
+ #define FS_C1_I0_A0_bInterfaceSubClass 0X00
+ #define FS_C1_I0_A0_bInterfaceProtocol 0X00
+ #else
+ #define FS_C1_I0_A0_bInterfaceClass 0X08
+ #define FS_C1_I0_A0_bInterfaceSubClass 0X06
+ #define FS_C1_I0_A0_bInterfaceProtocol 0X50
+ #endif
+ #define FS_C1_I0_A0_iInterface 0X00
+
+ #if (FS_C1_I0_A0_EP_NUMBER >= 1)
+ //EP0X01
+ #define FS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE
+ //JWEI 2003/05/19
+ #if fDOUBLE_BUF
+ #define FS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK
+ #else
+ #define FS_C1_I0_A0_EP1_BLKNO SINGLE_BLK
+ #endif
+ #define FS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT
+ #define FS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK
+ //JWEI 2003/05/07
+ #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64
+ #define FS_C1_I0_A0_EP1_bInterval 00
+ #endif
+ #if (FS_C1_I0_A0_EP_NUMBER >= 2)
+ //EP0X02
+ #define FS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE
+ //JWEI 2003/08/20
+ #if fDOUBLE_BUF_IN
+ #define FS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK
+ #else
+ #define FS_C1_I0_A0_EP2_BLKNO SINGLE_BLK
+ #endif
+ #define FS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN
+ #define FS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK
+ #define FS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_64
+ #define FS_C1_I0_A0_EP2_bInterval 00
+ #endif
+ #if (FS_C1_I0_A0_EP_NUMBER >= 3)
+ //EP0X03
+ #define FS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE
+ #define FS_C1_I0_A0_EP3_BLKNO SINGLE_BLK
+ #define FS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN
+ #define FS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT
+ #define FS_C1_I0_A0_EP3_MAX_PACKET 0x0040
+ #define FS_C1_I0_A0_EP3_bInterval 01
+ #endif
+ #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
+ //EP0X04
+ #define FS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE
+ #define FS_C1_I0_A0_EP4_BLKNO SINGLE_BLK
+ #define FS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT
+ #define FS_C1_I0_A0_EP4_TYPE TF_TYPE_BULK
+ #define FS_C1_I0_A0_EP4_MAX_PACKET 0x0040
+ #define FS_C1_I0_A0_EP4_bInterval 00
+ #endif
+ #if (FS_C1_I0_A0_EP_NUMBER >= 5)
+ //EP0X04
+ #define FS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE
+ #if fDOUBLE_BUF_IN
+ #define FS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK
+ #else
+ #define FS_C1_I0_A0_EP5_BLKNO SINGLE_BLK
+ #endif
+ #define FS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT
+ #define FS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK
+ #define FS_C1_I0_A0_EP5_MAX_PACKET 0x0040
+ #define FS_C1_I0_A0_EP5_bInterval 00
+ #endif
+ #if (FS_C1_I0_A0_EP_NUMBER >= 6)
+ //EP0X04
+ #define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE
+ #if fDOUBLE_BUF_IN
+ #define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK
+ #else
+ #define FS_C1_I0_A0_EP6_BLKNO SINGLE_BLK
+ #endif
+ #define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT
+ #define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK
+ #define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040
+ #define FS_C1_I0_A0_EP6_bInterval 00
+ #endif
+ #endif
+ #endif
+#endif
+
+#if (FS_CONFIGURATION_NUMBER >= 1)
+ // Configuration 1
+ #if (FS_C1_INTERFACE_NUMBER >= 1)
+ // Interface 0
+ #if (FS_C1_I0_ALT_NUMBER >= 1)
+ // AlternateSetting 0
+ #define FS_C1_I0_A0_EP_LENGTH (EP_LENGTH * FS_C1_I0_A0_EP_NUMBER)
+ #if (FS_C1_I0_A0_EP_NUMBER >= 1)
+ // EP1
+ #define FS_C1_I0_A0_EP1_FIFO_START FIFO0
+ #define FS_C1_I0_A0_EP1_FIFO_NO (FS_C1_I0_A0_EP1_BLKNO * FS_C1_I0_A0_EP1_BLKSIZE)
+ #define FS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP1_BLKNO - 1) << 2) | FS_C1_I0_A0_EP1_TYPE)
+ #define FS_C1_I0_A0_EP1_FIFO_MAP (((1 - FS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
+ #define FS_C1_I0_A0_EP1_MAP (FS_C1_I0_A0_EP1_FIFO_START | (FS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP1_DIRECTION)))
+ #endif
+ #if (FS_C1_I0_A0_EP_NUMBER >= 2)
+ // EP2
+ #define FS_C1_I0_A0_EP2_FIFO_START (FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO)
+ #define FS_C1_I0_A0_EP2_FIFO_NO (FS_C1_I0_A0_EP2_BLKNO * FS_C1_I0_A0_EP2_BLKSIZE)
+ #define FS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP2_BLKNO - 1) << 2) | FS_C1_I0_A0_EP2_TYPE)
+ #define FS_C1_I0_A0_EP2_FIFO_MAP (((1 - FS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
+ #define FS_C1_I0_A0_EP2_MAP (FS_C1_I0_A0_EP2_FIFO_START | (FS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP2_DIRECTION)))
+ #endif
+ #if (FS_C1_I0_A0_EP_NUMBER >= 3)
+ // EP3
+ //JWEI 2003/07/15
+ // #define FS_C1_I0_A0_EP3_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
+ #define FS_C1_I0_A0_EP3_FIFO_START FIFO14
+ #define FS_C1_I0_A0_EP3_FIFO_NO (FS_C1_I0_A0_EP3_BLKNO * FS_C1_I0_A0_EP3_BLKSIZE)
+ #define FS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP3_BLKNO - 1) << 2) | FS_C1_I0_A0_EP3_TYPE)
+ #define FS_C1_I0_A0_EP3_FIFO_MAP (((1 - FS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
+ #define FS_C1_I0_A0_EP3_MAP (FS_C1_I0_A0_EP3_FIFO_START | (FS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP3_DIRECTION)))
+ #endif
+ #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
+ // EP4
+ #define FS_C1_I0_A0_EP4_FIFO_START (FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO)
+ #define FS_C1_I0_A0_EP4_FIFO_NO (FS_C1_I0_A0_EP4_BLKNO * FS_C1_I0_A0_EP4_BLKSIZE)
+ #define FS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP4_BLKNO - 1) << 2) | FS_C1_I0_A0_EP4_TYPE)
+ #define FS_C1_I0_A0_EP4_FIFO_MAP (((1 - FS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
+ #define FS_C1_I0_A0_EP4_MAP (FS_C1_I0_A0_EP4_FIFO_START | (FS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP4_DIRECTION)))
+ #endif
+ #if (FS_C1_I0_A0_EP_NUMBER >= 5)
+ // EP5
+ #define FS_C1_I0_A0_EP5_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
+ #define FS_C1_I0_A0_EP5_FIFO_NO (FS_C1_I0_A0_EP5_BLKNO * FS_C1_I0_A0_EP5_BLKSIZE)
+ #define FS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP5_BLKNO - 1) << 2) | FS_C1_I0_A0_EP5_TYPE)
+ #define FS_C1_I0_A0_EP5_FIFO_MAP (((1 - FS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
+ #define FS_C1_I0_A0_EP5_MAP (FS_C1_I0_A0_EP5_FIFO_START | (FS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP5_DIRECTION)))
+ #endif
+ #if (FS_C1_I0_A0_EP_NUMBER >= 6)
+ // EP5
+ #define FS_C1_I0_A0_EP6_FIFO_START (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO)
+ #define FS_C1_I0_A0_EP6_FIFO_NO (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE)
+ #define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE)
+ #define FS_C1_I0_A0_EP6_FIFO_MAP (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
+ #define FS_C1_I0_A0_EP6_MAP (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION)))
+ #endif
+ #endif
+
+ #if (FS_C1_I0_ALT_NUMBER >= 2)
+ // AlternateSetting 1
+ #define FS_C1_I0_A1_EP_LENGTH (EP_LENGTH * FS_C1_I0_A1_EP_NUMBER)
+ #if (FS_C1_I0_A1_EP_NUMBER >= 1)
+ // EP1
+ #define FS_C1_I0_A1_EP1_FIFO_START FIFO0
+ #define FS_C1_I0_A1_EP1_FIFO_NO (FS_C1_I0_A1_EP1_BLKNO * FS_C1_I0_A1_EP1_BLKSIZE)
+ #define FS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP1_BLKNO - 1) << 2) | FS_C1_I0_A1_EP1_TYPE)
+ #define FS_C1_I0_A1_EP1_FIFO_MAP (((1 - FS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
+ #define FS_C1_I0_A1_EP1_MAP (FS_C1_I0_A1_EP1_FIFO_START | (FS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP1_DIRECTION)))
+ #endif
+ #if (FS_C1_I0_A1_EP_NUMBER >= 2)
+ // EP2
+ #define FS_C1_I0_A1_EP2_FIFO_START (FS_C1_I0_A1_EP1_FIFO_START + FS_C1_I0_A1_EP1_FIFO_NO)
+ #define FS_C1_I0_A1_EP2_FIFO_NO (FS_C1_I0_A1_EP2_BLKNO * FS_C1_I0_A1_EP2_BLKSIZE)
+ #define FS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP2_BLKNO - 1) << 2) | FS_C1_I0_A1_EP2_TYPE)
+ #define FS_C1_I0_A1_EP2_FIFO_MAP (((1 - FS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
+ #define FS_C1_I0_A1_EP2_MAP (FS_C1_I0_A1_EP2_FIFO_START | (FS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP2_DIRECTION)))
+ #endif
+ #if (FS_C1_I0_A1_EP_NUMBER >= 3)
+ // EP3
+ #define FS_C1_I0_A1_EP3_FIFO_START (FS_C1_I0_A1_EP2_FIFO_START + FS_C1_I0_A1_EP2_FIFO_NO)
+ #define FS_C1_I0_A1_EP3_FIFO_NO (FS_C1_I0_A1_EP3_BLKNO * FS_C1_I0_A1_EP3_BLKSIZE)
+ #define FS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP3_BLKNO - 1) << 2) | FS_C1_I0_A1_EP3_TYPE)
+ #define FS_C1_I0_A1_EP3_FIFO_MAP (((1 - FS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
+ #define FS_C1_I0_A1_EP3_MAP (FS_C1_I0_A1_EP3_FIFO_START | (FS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP3_DIRECTION)))
+ #endif
+ #endif
+
+ #if (FS_C1_I0_ALT_NUMBER == 1)
+ #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH)
+ #elif (FS_C1_I0_ALT_NUMBER == 2)
+ #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH + FS_C1_I0_A1_EP_LENGTH)
+ #endif
+ #endif
+
+ #if (FS_C1_INTERFACE_NUMBER >= 2)
+ // Interface 1
+ #if (FS_C1_I1_ALT_NUMBER >= 1)
+ // AlternateSetting 0
+ #define FS_C1_I1_A0_EP_LENGTH (EP_LENGTH * FS_C1_I1_A0_EP_NUMBER)
+ #if (FS_C1_I1_A0_EP_NUMBER >= 1)
+ // EP1
+ #define FS_C1_I1_A0_EP1_FIFO_START FIFO0
+ #define FS_C1_I1_A0_EP1_FIFO_NO (FS_C1_I1_A0_EP1_BLKNO * FS_C1_I1_A0_EP1_BLKSIZE)
+ #define FS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP1_BLKNO - 1) << 2) | FS_C1_I1_A0_EP1_TYPE)
+ #define FS_C1_I1_A0_EP1_FIFO_MAP (((1 - FS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
+ #define FS_C1_I1_A0_EP1_MAP (FS_C1_I1_A0_EP1_FIFO_START | (FS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP1_DIRECTION)))
+ #endif
+ #if (FS_C1_I1_A0_EP_NUMBER >= 2)
+ // EP2
+ #define FS_C1_I1_A0_EP2_FIFO_START (FS_C1_I1_A0_EP1_FIFO_START + FS_C1_I1_A0_EP1_FIFO_NO)
+ #define FS_C1_I1_A0_EP2_FIFO_NO (FS_C1_I1_A0_EP2_BLKNO * FS_C1_I1_A0_EP2_BLKSIZE)
+ #define FS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP2_BLKNO - 1) << 2) | FS_C1_I1_A0_EP2_TYPE)
+ #define FS_C1_I1_A0_EP2_FIFO_MAP (((1 - FS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
+ #define FS_C1_I1_A0_EP2_MAP (FS_C1_I1_A0_EP2_FIFO_START | (FS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP2_DIRECTION)))
+ #endif
+ #if (FS_C1_I1_A0_EP_NUMBER >= 3)
+ // EP3
+ #define FS_C1_I1_A0_EP3_FIFO_START (FS_C1_I1_A0_EP2_FIFO_START + FS_C1_I1_A0_EP2_FIFO_NO)
+ #define FS_C1_I1_A0_EP3_FIFO_NO (FS_C1_I1_A0_EP3_BLKNO * FS_C1_I1_A0_EP3_BLKSIZE)
+ #define FS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP3_BLKNO - 1) << 2) | FS_C1_I1_A0_EP3_TYPE)
+ #define FS_C1_I1_A0_EP3_FIFO_MAP (((1 - FS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
+ #define FS_C1_I1_A0_EP3_MAP (FS_C1_I1_A0_EP3_FIFO_START | (FS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP3_DIRECTION)))
+ #endif
+ #endif
+
+ #if (FS_C1_I1_ALT_NUMBER >= 2)
+ // AlternateSetting 1
+ #define FS_C1_I1_A1_EP_LENGTH (EP_LENGTH * FS_C1_I1_A1_EP_NUMBER)
+ #if (FS_C1_I1_A1_EP_NUMBER >= 1)
+ // EP1
+ #define FS_C1_I1_A1_EP1_FIFO_START FIFO0
+ #define FS_C1_I1_A1_EP1_FIFO_NO (FS_C1_I1_A1_EP1_BLKNO * FS_C1_I1_A1_EP1_BLKSIZE)
+ #define FS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP1_BLKNO - 1) << 2) | FS_C1_I1_A1_EP1_TYPE)
+ #define FS_C1_I1_A1_EP1_FIFO_MAP (((1 - FS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
+ #define FS_C1_I1_A1_EP1_MAP (FS_C1_I1_A1_EP1_FIFO_START | (FS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP1_DIRECTION)))
+ #endif
+ #if (FS_C1_I1_A1_EP_NUMBER >= 2)
+ // EP2
+ #define FS_C1_I1_A1_EP2_FIFO_START (FS_C1_I1_A1_EP1_FIFO_START + FS_C1_I1_A1_EP1_FIFO_NO)
+ #define FS_C1_I1_A1_EP2_FIFO_NO (FS_C1_I1_A1_EP2_BLKNO * FS_C1_I1_A1_EP2_BLKSIZE)
+ #define FS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP2_BLKNO - 1) << 2) | FS_C1_I1_A1_EP2_TYPE)
+ #define FS_C1_I1_A1_EP2_FIFO_MAP (((1 - FS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
+ #define FS_C1_I1_A1_EP2_MAP (FS_C1_I1_A1_EP2_FIFO_START | (FS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP2_DIRECTION)))
+ #endif
+ #if (FS_C1_I1_A1_EP_NUMBER >= 3)
+ // EP3
+ #define FS_C1_I1_A1_EP3_FIFO_START (FS_C1_I1_A1_EP2_FIFO_START + FS_C1_I1_A1_EP2_FIFO_NO)
+ #define FS_C1_I1_A1_EP3_FIFO_NO (FS_C1_I1_A1_EP3_BLKNO * FS_C1_I1_A1_EP3_BLKSIZE)
+ #define FS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP3_BLKNO - 1) << 2) | FS_C1_I1_A1_EP3_TYPE)
+ #define FS_C1_I1_A1_EP3_FIFO_MAP (((1 - FS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
+ #define FS_C1_I1_A1_EP3_MAP (FS_C1_I1_A1_EP3_FIFO_START | (FS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP3_DIRECTION)))
+ #endif
+ #endif
+
+ #if (FS_C1_I1_ALT_NUMBER == 1)
+ #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH)
+ #elif (FS_C1_I1_ALT_NUMBER == 2)
+ #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH + FS_C1_I1_A1_EP_LENGTH)
+ #endif
+ #endif
+
+ #if (FS_C1_INTERFACE_NUMBER == 1)
+ #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH)
+ #elif (FS_C1_INTERFACE_NUMBER == 2)
+ #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH + HS_FS_C1_I1_ALT_LENGTH)
+ #endif
+#endif
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+#define USB_ENABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable
+
+#define USB_DISABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable
+
+#define USB_UP_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))) // upQ stream mode
+
+#define USB_UP_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3)) // upQ packet mode
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+#define USB_ENABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1)) // lp downstream DMA enable
+
+#define USB_DISABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))) // lp downstream DMA disable
+
+#define USB_LP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT6))) // lpQ packet mode
+
+#define USB_LP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6)) // lpQ stream mode
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+#define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable
+
+#define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable
+
+#define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7))) // hpQ packet mode
+
+#define USB_HP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7)) // hpQ stream mode
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+#define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable
+
+#define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable
+
+#define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10))) // hpQ packet mode
+
+#define USB_MP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10)) // hpQ stream mode
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define USB_ENABLE_UP_PACKET_MODE() USB_DISABLE_UP_DMA(); \
+ USB_UP_PACKET_MODE(); \
+ USB_ENABLE_UP_DMA();
+
+#define USB_ENABLE_LP_DN_PACKET_MODE() USB_DISABLE_LP_DN_DMA(); \
+ USB_LP_DN_PACKET_MODE(); \
+ USB_ENABLE_LP_DN_DMA()
+
+#define USB_ENABLE_MP_DN_PACKET_MODE() USB_DISABLE_MP_DN_DMA(); \
+ USB_MP_DN_PACKET_MODE(); \
+ USB_ENABLE_MP_DN_DMA();
+
+#define USB_ENABLE_HP_DN_PACKET_MODE() USB_DISABLE_HP_DN_DMA(); \
+ USB_HP_DN_PACKET_MODE(); \
+ USB_ENABLE_HP_DN_DMA();
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+#define USB_ENABLE_UP_STREAM_MODE() USB_DISABLE_UP_DMA(); \
+ USB_UP_STREAM_MODE(); \
+ USB_ENABLE_UP_DMA();
+
+#define USB_ENABLE_LP_DN_STREAM_MODE() USB_DISABLE_LP_DN_DMA(); \
+ USB_LP_DN_STREAM_MODE(); \
+ USB_ENABLE_LP_DN_DMA()
+
+#define USB_ENABLE_MP_DN_STREAM_MODE() USB_DISABLE_MP_DN_DMA(); \
+ USB_MP_DN_STREAM_MODE(); \
+ USB_ENABLE_MP_DN_DMA();
+
+#define USB_ENABLE_HP_DN_STREAM_MODE() USB_DISABLE_HP_DN_DMA(); \
+ USB_HP_DN_STREAM_MODE(); \
+ USB_ENABLE_HP_DN_DMA();
+
+#define USB_STREAM_HOST_BUF_SIZE(size) USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size)));
+#define USB_STREAM_TIMEOUT(time_cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt); // set stream mode timeout critirea
+#define USB_STREAM_AGG_PKT_CNT(cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea
+
+#endif
#define ALLOCRAM_SIZE ( SYS_RAM_SZIE - ( ALLOCRAM_START - SYS_D_RAM_REGION_0_BASE) - SYS_D_RAM_STACK_SIZE)
// support for more than 64 bytes on command pipe
-extern void vUsb_Reg_Out_patch(void);
+extern void usb_reg_out_patch(void);
extern int _HIFusb_get_max_msg_len_patch(hif_handle_t handle, int pipe);
extern void _HIFusb_isr_handler_patch(hif_handle_t h);
extern BOOLEAN bSet_configuration_patch(void);
extern void vUSBFIFO_EP6Cfg_FS_patch(void);
-extern void vUsb_Status_In_patch(void);
+extern void usb_status_in_patch(void);
extern void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig);
extern void zfTurnOffPower_patch(void);
extern void zfResetUSBFIFO_patch(void);
if( hostif == HIF_USB ) {
_indir_tbl.hif._get_max_msg_len = _HIFusb_get_max_msg_len_patch;
- _indir_tbl.cmnos.usb._usb_reg_out = vUsb_Reg_Out_patch;
+ _indir_tbl.cmnos.usb._usb_reg_out = usb_reg_out_patch;
_indir_tbl.hif._isr_handler = _HIFusb_isr_handler_patch;
_indir_tbl.cmnos.usb._usb_set_configuration = bSet_configuration_patch;
- _indir_tbl.cmnos.usb._usb_status_in = vUsb_Status_In_patch;
+ _indir_tbl.cmnos.usb._usb_status_in = usb_status_in_patch;
_indir_tbl.cmnos.usb._usb_get_descriptor = bGet_descriptor_patch;
_indir_tbl.cmnos.usb._usb_standard_cmd = bStandardCommand_patch;
_indir_tbl.usbfifo_api._init = _fw_usbfifo_init;
#if defined(_RAM_)
#include "athos_api.h"
-
+#include "usb_defs.h"
+
#if defined(PROJECT_MAGPIE)
#include "regdump.h"
-#include "usb_defs.h"
extern uint32_t *init_htc_handle;
uint8_t htc_complete_setup = 0;
void reset_EP4_FIFO(void);
HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR,
(HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT1));
- HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x0);
+ USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0);
HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)|BIT4);
A_DELAY_USECS(5);
HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)&~BIT4);
A_DELAY_USECS(5);
- HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x1);
+ USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0);
// set clock to bypass mode - 40Mhz from XTAL
HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4));
MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
- A_PRINTF("Jump to BOOT\n");
-
- // reboot.....
+ A_PRINTF("Cold reboot initiated.");
+#if defined(PROJECT_MAGPIE)
+ HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, 0);
+#elif defined(PROJECT_K2)
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, 0);
+#endif /* #if defined(PROJECT_MAGPIE) */
A_USB_JUMP_BOOT();
}
+++ /dev/null
-/*
- * Copyright (c) 2013 Qualcomm Atheros, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted (subject to the limitations in the
- * disclaimer below) provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * * Neither the name of Qualcomm Atheros nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
- * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "usb_defs.h"
-#include "usb_type.h"
-#include "usb_pre.h"
-#include "usb_extr.h"
-#include "usb_std.h"
-#include "reg_defs.h"
-#include "athos_api.h"
-#include "usbfifo_api.h"
-
-#include "sys_cfg.h"
-
-#define measure_time 0
-#define measure_time_pll 10000000
-
-typedef void (* USBFIFO_recv_command)(VBUF *cmd);
-
-extern Action eUsbCxFinishAction;
-extern CommandType eUsbCxCommand;
-extern BOOLEAN UsbChirpFinish;
-extern USB_FIFO_CONFIG usbFifoConf;
-extern uint16_t *pu8DescriptorEX;
-extern uint16_t u16TxRxCounter;
-
-USBFIFO_recv_command m_origUsbfifoRecvCmd = NULL;
-
-void zfTurnOffPower_patch(void);
-
-static void _fw_reset_dma_fifo();
-static void _fw_restore_dma_fifo();
-static void _fw_power_on();
-static void _fw_power_off();
-
-BOOLEAN bEepromExist = TRUE;
-BOOLEAN bJumptoFlash = FALSE;
-
-void _fw_usbfifo_recv_command(VBUF *buf)
-{
- A_UINT8 *cmd_data;
- A_UINT32 tmp;
-
- cmd_data = (A_UINT8 *)(buf->desc_list->buf_addr + buf->desc_list->data_offset);
- tmp = *((A_UINT32 *)cmd_data);
- if ( tmp == 0xFFFFFFFF ) {
- // reset usb/wlan dma
- _fw_reset_dma_fifo();
-
- // restore gpio setting and usb/wlan dma state
- _fw_restore_dma_fifo();
-
- // set clock to bypass mode - 40Mhz from XTAL
- HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4));
-
- A_DELAY_USECS(100); // wait for stable
-
- HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));
-
- A_DELAY_USECS(100); // wait for stable
- A_UART_HWINIT((40*1000*1000), 19200);
-
- A_CLOCK_INIT(40);
-
- if (!bEepromExist) { //jump to flash boot (eeprom data in flash)
- bJumptoFlash = TRUE;
- A_PRINTF("Jump to Flash BOOT\n");
- app_start();
- }else{
- A_PRINTF("receive the suspend command...\n");
- // reboot.....
- A_USB_JUMP_BOOT();
- }
-
- } else {
- m_origUsbfifoRecvCmd(buf);
- }
-}
-
-void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig)
-{
- m_origUsbfifoRecvCmd = pConfig->recv_command;
-
- usbFifoConf.get_command_buf = pConfig->get_command_buf;
- usbFifoConf.recv_command = _fw_usbfifo_recv_command;
- usbFifoConf.get_event_buf = pConfig->get_event_buf;
- usbFifoConf.send_event_done = pConfig->send_event_done;
-}
-
-/*
- * -- support more than 64 bytes command on ep4 --
- */
-void vUsb_Reg_Out_patch(void)
-{
- uint16_t usbfifolen;
- uint16_t ii;
- uint32_t ep4_data;
- static volatile uint32_t *regaddr;
- static uint16_t cmdLen;
- static VBUF *buf;
- BOOLEAN cmd_is_last = FALSE;
- static BOOLEAN cmd_is_new = TRUE;
-
- // get the size of this transcation
- usbfifolen = USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_LOW_OFFSET);
-
- // check is command is new
- if( cmd_is_new ){
-
- buf = usbFifoConf.get_command_buf();
- cmdLen = 0;
-
- if( !buf )
- goto ERR;
-
- // copy free, assignment buffer of the address
- regaddr = (uint32_t *)buf->desc_list->buf_addr;
-
- cmd_is_new = FALSE;
- }
-
- // just in case, suppose should not happen
- if( !buf )
- goto ERR;
-
- // if size is smaller, this is the last command!
- // zero-length supposed should be set through 0x27/bit7->0x19/bit4, not here
- if( usbfifolen<64 ) {
- cmd_is_last = TRUE;
- }
-
- // accumulate the size
- cmdLen += usbfifolen;
-
- // round it to alignment
- if(usbfifolen % 4)
- usbfifolen = (usbfifolen >> 2) + 1;
- else
- usbfifolen = usbfifolen >> 2;
-
- // retrieve the data from fifo
- for(ii = 0; ii < usbfifolen; ii++)
- {
- ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out
- *regaddr = ep4_data;
- regaddr++;
- }
-
- // if this is the last command, callback to HTC
- if ( cmd_is_last )
- {
- buf->desc_list->next_desc = NULL;
- buf->desc_list->data_offset = 0;
- buf->desc_list->data_size = cmdLen;
- buf->desc_list->control = 0;
- buf->next_buf = NULL;
- buf->buf_length = cmdLen;
-
- usbFifoConf.recv_command(buf);
-
- cmd_is_new = TRUE;
- }
-
- goto DONE;
-ERR:
- // we might get no command buffer here?
- // but if we return here, the ep4 fifo will be lock out,
- // so that we still read them out but just drop it ?
- for(ii = 0; ii < usbfifolen; ii++)
- {
- ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out
- }
-
-DONE:
- //mUSB_STATUS_IN_INT_ENABLE();
- ;
-}
-
-
-/*
- * -- usb1.1 ep6 fix --
- */
-extern uint16_t u8UsbConfigValue;
-extern uint16_t u8UsbInterfaceValue;
-extern uint16_t u8UsbInterfaceAlternateSetting;
-extern SetupPacket ControlCmd;
-extern void vUsbClrEPx(void);
-
-#undef FS_C1_I0_A0_EP_NUMBER
-#define FS_C1_I0_A0_EP_NUMBER 6
-
-#define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE
-#define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK
-#define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT
-#define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK
-#define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040
-#define FS_C1_I0_A0_EP6_bInterval 00
-
-// EP6
-#define FS_C1_I0_A0_EP6_FIFO_START (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO)
-#define FS_C1_I0_A0_EP6_FIFO_NO (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE)
-#define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE)
-#define FS_C1_I0_A0_EP6_FIFO_MAP (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
-#define FS_C1_I0_A0_EP6_MAP (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION)))
-
-
-#define CMD_PCI_RC_RESET_ON() HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \
- (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)| \
- (PCI_RC_PHY_SHIFT_RESET_BIT|PCI_RC_PLL_RESET_BIT|PCI_RC_PHY_RESET_BIT|PCI_RC_RESET_BIT)))
-
-void vUSBFIFO_EP6Cfg_FS_patch(void)
-{
-#if (FS_C1_I0_A0_EP_NUMBER >= 6)
- int i;
-
- //EP0X06
- mUsbEPMap(EP6, FS_C1_I0_A0_EP6_MAP);
- mUsbFIFOMap(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_MAP);
- mUsbFIFOConfig(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_CONFIG);
-
- for(i = FS_C1_I0_A0_EP6_FIFO_START + 1 ;
- i < FS_C1_I0_A0_EP6_FIFO_START + FS_C1_I0_A0_EP6_FIFO_NO ; i ++)
- {
- mUsbFIFOConfig(i, (FS_C1_I0_A0_EP6_FIFO_CONFIG & (~BIT7)) );
- }
-
- mUsbEPMxPtSzHigh(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff));
- mUsbEPMxPtSzLow(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff));
- mUsbEPinHighBandSet(EP6 , FS_C1_I0_A0_EP6_DIRECTION, FS_C1_I0_A0_EP6_MAX_PACKET);
-#endif
-}
-
-void vUsbFIFO_EPxCfg_FS_patch(void)
-{
- switch (u8UsbConfigValue)
- {
-#if (FS_CONFIGURATION_NUMBER >= 1)
- // Configuration 0X01
- case 0X01:
- switch (u8UsbInterfaceValue)
- {
-#if (FS_C1_INTERFACE_NUMBER >= 1)
- // Interface 0
- case 0:
- switch (u8UsbInterfaceAlternateSetting)
- {
-
-#if (FS_C1_I0_ALT_NUMBER >= 1)
- // AlternateSetting 0
- case 0:
-
- // snapped....
-
- // patch up this ep6_fs config
- vUSBFIFO_EP6Cfg_FS_patch();
-
- break;
-
-#endif
- default:
- break;
- }
- break;
-#endif
- default:
- break;
- }
- break;
-#endif
- default:
- break;
- }
- //mCHECK_STACK();
-}
-
-
-BOOLEAN bSet_configuration_patch(void)
-{
- bSet_configuration();
-
- if (mLOW_BYTE(mDEV_REQ_VALUE()) == 0)
- {
- // snapped....
- ;
- }
- else
- {
- if (mUsbHighSpeedST()) // First judge HS or FS??
- {
- // snapped....
- ;
- }
- else
- {
- // snapped....
- vUsbFIFO_EPxCfg_FS_patch();
- }
-
- // snapped....
- }
-
- eUsbCxFinishAction = ACT_DONE;
- return TRUE;
-}
-
-
-/*
- * -- support more than 64 bytes command on ep3 --
- */
-void vUsb_Status_In_patch(void)
-{
- uint16_t count;
- uint16_t remainder;
- u16_t RegBufLen;
- BOOLEAN cmdEnd = FALSE;
-
- static u16_t mBufLen;
- static VBUF *evntbuf = NULL;
- static volatile u32_t *regaddr;
- static BOOLEAN cmd_is_new = TRUE;
-
- if( cmd_is_new )
- {
- evntbuf = usbFifoConf.get_event_buf();
- if ( evntbuf != NULL )
- {
- regaddr = (u32_t *)VBUF_GET_DATA_ADDR(evntbuf);
- mBufLen = evntbuf->buf_length;
- }
- else
- {
- mUSB_STATUS_IN_INT_DISABLE();
- goto ERR_DONE;
- }
-
- cmd_is_new = FALSE;
- }
-
- if( mBufLen > bUSB_EP_MAX_PKT_SIZE_64 ) {
- RegBufLen = bUSB_EP_MAX_PKT_SIZE_64;
- mBufLen -= bUSB_EP_MAX_PKT_SIZE_64;
- }
- // TODO: 64 byes... controller supposed will take care of zero-length?
- else {
- RegBufLen = mBufLen;
- cmdEnd = TRUE;
- }
-
- /* INT use EP3 */
- for(count = 0; count < (RegBufLen / 4); count++)
- {
- USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
- regaddr++;
- }
-
- remainder = RegBufLen % 4;
-
- if (remainder)
- {
- switch(remainder)
- {
- case 3:
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
- break;
- case 2:
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
- break;
- case 1:
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
- break;
- }
-
- USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
-
- // Restore CBus FIFO size to word size
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
- }
-
- mUSB_EP3_XFER_DONE();
-
- if ( evntbuf != NULL && cmdEnd )
- {
- usbFifoConf.send_event_done(evntbuf);
- cmd_is_new = TRUE;
- }
-
-ERR_DONE:
- ;
-}
-
-
-#define PCI_RC_RESET_BIT BIT6
-#define PCI_RC_PHY_RESET_BIT BIT7
-#define PCI_RC_PLL_RESET_BIT BIT8
-#define PCI_RC_PHY_SHIFT_RESET_BIT BIT10
-
-
-/*
- * -- urn_off_merlin --
- * . values suggested from Lalit
- *
- */
-static void turn_off_merlin()
-{
- volatile uint32_t default_data[9];
- uint32_t i=0;
-
- if(1)
- {
- A_PRINTF("turn_off_merlin_ep_start ......\n");
- A_DELAY_USECS(measure_time);
- default_data[0] = 0x9248fd00;
- default_data[1] = 0x24924924;
- default_data[2] = 0xa8000019;
- default_data[3] = 0x17160820;
- default_data[4] = 0x25980560;
- default_data[5] = 0xc1c00000;
- default_data[6] = 0x1aaabe40;
- default_data[7] = 0xbe105554;
- default_data[8] = 0x00043007;
-
- for(i=0; i<9; i++)
- {
- A_DELAY_USECS(10);
-
- HAL_WORD_REG_WRITE( 0x10ff4040, default_data[i]);
- }
- A_DELAY_USECS(10);
- HAL_WORD_REG_WRITE(0x10ff4044, BIT0);
- A_PRINTF("turn_off_merlin_ep_end ......\n");
- }
-}
-
-/*
- * -- turn_off_phy --
- *
- * . write shift register to both pcie ep and rc
- * .
- */
-
-static void turn_off_phy()
-{
-
- volatile uint32_t default_data[9];
- volatile uint32_t read_data = 0;
- uint32_t i=0;
-
- default_data[0] = 0x9248fd00;
- default_data[1] = 0x24924924;
- default_data[2] = 0xa8000019;
- default_data[3] = 0x17160820;
- default_data[4] = 0x25980560;
- default_data[5] = 0xc1c00000;
- default_data[6] = 0x1aaabe40;
- default_data[7] = 0xbe105554;
- default_data[8] = 0x00043007;
-
- for(i=0; i<9; i++)
- {
- // check for the done bit to be set
-
- while (1)
- {
- read_data=HAL_WORD_REG_READ(0x40028);
- if( read_data & BIT31 )
- break;
- }
-
- A_DELAY_USECS(1);
-
- HAL_WORD_REG_WRITE( 0x40024, default_data[i]);
- }
- HAL_WORD_REG_WRITE(0x40028, BIT0);
-}
-
-static void turn_off_phy_rc()
-{
-
- volatile uint32_t default_data[9];
- volatile uint32_t read_data = 0;
- uint32_t i=0;
-
- A_PRINTF("turn_off_phy_rc\n");
-
- default_data[0] = 0x9248fd00;
- default_data[1] = 0x24924924;
- default_data[2] = 0xa8000019;
- default_data[3] = 0x13160820;//PwdClk1MHz=0
- default_data[4] = 0x25980560;
- default_data[5] = 0xc1c00000;
- default_data[6] = 0x1aaabe40;
- default_data[7] = 0xbe105554;
- default_data[8] = 0x00043007;
-
- for(i=0; i<9; i++)
- {
- // check for the done bit to be set
-
- while (1)
- {
- read_data=HAL_WORD_REG_READ(0x40028);
- if( read_data & BIT31 )
- break;
- }
-
- A_DELAY_USECS(1);
-
- HAL_WORD_REG_WRITE( 0x40024, default_data[i]);
- }
- HAL_WORD_REG_WRITE(0x40028, BIT0);
-}
-
-volatile uint32_t gpio_func = 0x0;
-volatile uint32_t gpio = 0x0;
-
-/*
- * -- patch zfTurnOffPower --
- *
- * . set suspend counter to non-zero value
- * .
- */
-void zfTurnOffPower_patch(void)
-{
- A_PRINTF("+++ goto suspend ......\n");
-
- // setting the go suspend here, power down right away...
- HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8));
-
- A_DELAY_USECS(100);
-
- // TURN OFF ETH PLL
- _fw_power_off();
-
- //32clk wait for External ETH PLL stable
- A_DELAY_USECS(100);
-
- HAL_WORD_REG_WRITE(0x52000, 0x70303);//read back 0x703f7
- HAL_WORD_REG_WRITE(0x52008, 0x0e91c);//read back 0x1e948
-
- HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(BIT0))); //0x56030
- // wake up, and turn on cpu, eth, pcie and usb pll
- _fw_power_on();
- // restore gpio and other settings
- _fw_restore_dma_fifo();
-
- // clear suspend..................
- HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)&(~BIT0)));
- HAL_WORD_REG_WRITE(0x52028, HAL_WORD_REG_READ(0x52028)&(~(BIT8|BIT12|BIT16)));
-}
-
-/*
- * -- patch zfResetUSBFIFO_patch --
- *
- * . clear ep3/ep4 fifo
- * . set suspend magic pattern
- * . reset pcie ep phy
- * . reset pcie rc phy
- * . turn off pcie pll
- * . reset all pcie/gmac related registers
- * . reset usb dma
- */
-void zfResetUSBFIFO_patch(void)
-{
- A_PRINTF("0x9808 0x%x ......\n", HAL_WORD_REG_READ(0x10ff9808));
- A_PRINTF("0x7890 0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890));
- A_PRINTF("0x7890 0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890));
- A_PRINTF("0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
- _fw_reset_dma_fifo();
-}
-
-static void _fw_reset_dma_fifo()
-{
- HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
- HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10));
- A_PRINTF("_fw_reset_dma_fifo\n");
-
- // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!!
- mUSB_STATUS_IN_INT_DISABLE();
-
- // update magic pattern to indicate this is a suspend
- HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, SUS_MAGIC_PATTERN);
-
- A_PRINTF("org 0x4048 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048));
- A_PRINTF("org 0x404C 0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C));
- A_PRINTF("org 0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
-
- HAL_WORD_REG_WRITE(0x10ff4088,0xaaa6a);//1010.1010.1010.0110.1010 for UB94
- HAL_WORD_REG_WRITE(0x10ff404C,0x0);
-
- A_DELAY_USECS(1000);
- A_PRINTF("0x4048 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048));
- A_PRINTF("0x404C 0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C));
- A_PRINTF("0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
-
- // turn off merlin
- turn_off_merlin();
- // pcie ep
- A_PRINTF("turn_off_magpie_ep_start ......\n");
- A_DELAY_USECS(measure_time);
- HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)|BIT0|(1<<1)));
- turn_off_phy();
- HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&~(BIT0|(1<<1))));
- A_PRINTF("turn_off_magpie_ep_end ......\n");
-
- // pcie rc
- A_PRINTF("turn_off_magpie_rc_start ......\n");
- A_DELAY_USECS(measure_time);
- HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&(~BIT0)));
- turn_off_phy_rc();
- A_PRINTF("turn_off_magpie_rc_end ......down\n");
- A_DELAY_USECS(measure_time);
-
- A_PRINTF("0x4001C %p ......\n", HAL_WORD_REG_READ(0x4001c));
- A_PRINTF("0x40040 %p ......\n", HAL_WORD_REG_READ(0x40040));
-
- // turn off pcie_pll - power down (bit16)
- A_PRINTF(" before pwd PCIE PLL CFG:0x5601C %p ......\n", HAL_WORD_REG_READ(0x5601C));
- HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)|(BIT18)));
- A_PRINTF(" after pwd PCIE PLL CFG:0x5601C %p ......\n", HAL_WORD_REG_READ(0x5601C));
-
- /* set everything to reset state?, requested by Oligo */
- HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)|(BIT13|BIT12|BIT11|BIT9|BIT7|BIT6));
-
- HAL_WORD_REG_WRITE(0x5C000, 0);
-
- A_DELAY_USECS(10);
-
- // reset usb DMA controller
- HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x0);
-
- HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT4)));
- A_DELAY_USECS(5);
- HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~BIT4)));
-
-
- HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x1);
-}
-
-static void _fw_power_off()
-{
- /*
- * 1. set CPU bypass
- * 2. turn off CPU PLL
- * 3. turn off ETH PLL
- * 4. disable ETH PLL bypass and update
- * 4.1 set suspend timeout
- * 5. set SUSPEND_ENABLE
- */
-
- HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4)); //0x56004
-
- A_DELAY_USECS(100); // wait for stable
-
- HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));//0x56000
-
- A_DELAY_USECS(100); // wait for stable
-
- A_UART_HWINIT((40*1000*1000), 19200);
- A_CLOCK_INIT(40);
-
- HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)|(BIT16))); //0x5600c
-
- HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)|(BIT4|BIT0))); //0x56010
-
- HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(0x10<<8))); //0x56030
-}
-
-static void _fw_power_on()
-{
- /*
- * 1. turn on CPU PLL
- * 2. disable CPU bypass
- * 3. turn on ETH PLL
- * 4. disable ETH PLL bypass and update
- * 5. turn on pcie pll
- */
-
- HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)&(~BIT16)));
-
- // deassert eth_pll bypass mode and trigger update bit
- HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)&(~(BIT4|BIT0))));
-}
-
-static void _fw_restore_dma_fifo(void)
-{
- HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)&(~(BIT18))));
-
- // reset pcie_rc shift
- HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~(BIT10|BIT8|BIT7))));
- A_DELAY_USECS(1);
- HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT10|BIT8|BIT7)));
-
- // reset pci_rc phy
- CMD_PCI_RC_RESET_ON();
- A_DELAY_USECS(20);
-
- // enable dma swap function
- MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
- MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
- MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
- MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
-}
-
-extern uint16_t *u8ConfigDescriptorEX;
-extern uint16_t *pu8DescriptorEX;
-extern uint16_t u16TxRxCounter;
-
-extern uint16_t *u8UsbDeviceDescriptor;
-
-extern BOOLEAN bGet_descriptor(void);
-
-uint16_t ConfigDescriptorPatch[30];
-
-uint16_t UsbDeviceDescriptorPatch[9];
-#define BCD_DEVICE_OFFSET 6
-#define BCD_DEVICE_FW_SIGNATURE 0xffff
-#define VENDOR_ID_OFFSET 4
-#define PRODUCT_ID_OFFSET 5
-
-#define EP3_TRANSFER_TYPE_OFFSET 17
-#define EP3_INT_INTERVAL 19
-#define EP4_TRANSFER_TYPE_OFFSET 21
-#define EP4_INT_INTERVAL 22
-
-
-
- #define A_SFLASH_READ_4B(u32Data, start_addr) u32Data = *(uint32_t *)(0xf000000+start_addr);
- #define FLASH_SIZE 0x800000 //8M
- #define FLASH_USB_VENDOR_ID_OFFSET 0x86
- #define FLASH_USB_PRODUCT_ID_OFFSET 0x87
-
- // flash reserved size for saving eeprom data is 4K.
- #define EE_DATA_RESERVED_LEN 0x1000 //4K
-
-#define mLOW_MASK(u16) ((uint8_t) ((u16) & mMASK(8)))
-#define mHIGH_MASK(u16) ((uint8_t) ((u16) & ~mMASK(8)))
-
-/* (1234) -> 0034 */
-//#define mLOW_BYTE(u16) ((U_8)(u16))
-#define mLOW_BYTE(u16) mLOW_MASK(u16)
-/* (1234) -> 0012 */
-#define mHIGH_BYTE(u16) ((uint8_t) (((uint16_t) (u16)) >> 8))
-
-#define mLOW_WORD0(u32) ((uint16_t) ((u32) & 0xFFFF))
-#define mHIGH_WORD0(u32) ((uint16_t) ((u32) >> 16))
-
-/* (1234) -> 3412 */
-#define mSWAP_BYTE(u16) ((mLOW_MASK(u16) << 8) | mHIGH_BYTE(u16))
-
-BOOLEAN bGet_descriptor_patch(void)
-{
- if (mDEV_REQ_VALUE_HIGH() == 1)
- {
- uint8_t *p = (uint8_t *)u8UsbDeviceDescriptor;
- uint32_t u32Tmp=0;
- /* Copy Usb Device Descriptor */
- ath_hal_memcpy(UsbDeviceDescriptorPatch, p, sizeof(UsbDeviceDescriptorPatch));
-
- UsbDeviceDescriptorPatch[BCD_DEVICE_OFFSET] =
- BCD_DEVICE_FW_SIGNATURE;
-
- /* Patch for custom id from flash */
- if (bEepromExist == FALSE) {
- A_SFLASH_READ_4B(u32Tmp, FLASH_SIZE -
- EE_DATA_RESERVED_LEN + FLASH_USB_VENDOR_ID_OFFSET*2);
- UsbDeviceDescriptorPatch[VENDOR_ID_OFFSET] =
- mSWAP_BYTE(mLOW_WORD0(u32Tmp));
- UsbDeviceDescriptorPatch[PRODUCT_ID_OFFSET] =
- mSWAP_BYTE(mHIGH_WORD0(u32Tmp));
- }
-
- pu8DescriptorEX = UsbDeviceDescriptorPatch;
- u16TxRxCounter = mTABLE_LEN(u8UsbDeviceDescriptor[0]);
-
- if (u16TxRxCounter > mDEV_REQ_LENGTH())
- u16TxRxCounter = mDEV_REQ_LENGTH();
-
- A_USB_EP0_TX_DATA();
-
- //u16TxRxCounter = 18;
- return TRUE;
- }
- if (mDEV_REQ_VALUE_HIGH() == 2) {
- uint8_t *p = (uint8_t *)u8ConfigDescriptorEX;
-
- /* Copy ConfigDescriptor */
- ath_hal_memcpy(ConfigDescriptorPatch, p, sizeof(ConfigDescriptorPatch));
-
- /* place holder for EPx patches */
-
- switch (mDEV_REQ_VALUE_LOW())
- {
- case 0x00: // configuration no: 0
- pu8DescriptorEX = ConfigDescriptorPatch;
- u16TxRxCounter = ConfigDescriptorPatch[1];
- //u16TxRxCounter = 46;
- break;
- default:
- return FALSE;
- }
-
- if (u16TxRxCounter > mDEV_REQ_LENGTH())
- u16TxRxCounter = mDEV_REQ_LENGTH();
-
- A_USB_EP0_TX_DATA();
- return TRUE;
- }
- else {
- return bGet_descriptor();
- }
-}
-
-extern BOOLEAN bStandardCommand(void);
-
-BOOLEAN bStandardCommand_patch(void)
-{
- if (mDEV_REQ_REQ() == USB_SET_CONFIGURATION) {
- A_USB_SET_CONFIG();
-
-#if ENABLE_SWAP_DATA_MODE
- // SWAP FUNCTION should be enabled while DMA engine is not working,
- // the best place to enable it is before we trigger the DMA
- MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
- MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
-
-#if SYSTEM_MODULE_HP_EP5
- MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
-#endif
-
-#if SYSTEM_MODULE_HP_EP6
- MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
-#endif
-
-#endif //ENABLE_SWAP_DATA_MODE
- return TRUE;
- }
- else {
- return bStandardCommand();
- }
-}
a_uint16_t tmp;
a_uint16_t offset = IEEE80211_WLAN_HDR_LEN;
a_uint8_t b1, b2;
+ struct ieee80211_qosframe_addr4 *wh_mesh;
if (IEEE80211_QOS_HAS_SEQ(wh))
offset += 4; // pad for 4 byte alignment
+ /* set the offset to 32 if the mesh control field is present */
+ wh_mesh = (struct ieee80211_qosframe_addr4 *)wh;
+ if (wh_mesh->i_qos[1] == 0x01)
+ offset = 32;
+
iv = (a_uint8_t *) wh;
iv = iv + offset;
void owl_tgt_tx_tasklet(TQUEUE_ARG data);
static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
+static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
extern void ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
+static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr)
+{
+ if ((addr & 0xffffe000) == 0x2000) {
+ /* SEEPROM registers */
+ ath_hal_reg_read_target(ah, addr);
+ if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0))
+ adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
+
+ return (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
+ } else if (addr > 0xffff)
+ /* SoC registers */
+ return HAL_WORD_REG_READ(addr);
+ else
+ /* MAC registers */
+ return ath_hal_reg_read_target(ah, addr);
+}
+
static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
{
addr = *(a_uint32_t *)(data + i);
addr = adf_os_ntohl(addr);
- if ((addr & 0xffffe000) == 0x2000) {
- /* SEEPROM */
- ath_hal_reg_read_target(ah, addr);
- if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) {
- adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
- }
- val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
- } else if (addr > 0xffff) {
- val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr;
- } else
- val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr);
-
- val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]);
+ val[i/sizeof(a_int32_t)] =
+ adf_os_ntohl(ath_reg_read_filter(ah, addr));
}
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
}
+static void ath_pll_reset_ones(struct ath_hal *ah)
+{
+ static uint8_t reset_pll = 0;
+
+ if(reset_pll == 0) {
+#if defined(PROJECT_K2)
+ /* here we write to core register */
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+ /* and here to mac register */
+ ath_hal_reg_write_target(ah, 0x786c,
+ ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
+ ath_hal_reg_write_target(ah, 0x786c,
+ ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
+
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
+
+#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
+ ath_hal_reg_write_target(ah, 0x7890,
+ ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
+ ath_hal_reg_write_target(ah, 0x7890,
+ ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
+#endif
+ reset_pll = 1;
+ }
+}
+
+static void ath_hal_reg_write_filter(struct ath_hal *ah,
+ a_uint32_t reg, a_uint32_t val)
+{
+ if(reg > 0xffff) {
+ HAL_WORD_REG_WRITE(reg, val);
+#if defined(PROJECT_K2)
+ if(reg == 0x50040) {
+ static uint8_t flg=0;
+
+ if(flg == 0) {
+ /* reinit clock and uart.
+ * TODO: Independent on what host will
+ * here set. We do our own decision. Why? */
+ A_CLOCK_INIT(117);
+ A_UART_HWINIT(117*1000*1000, 19200);
+ flg = 1;
+ }
+ }
+#endif
+ } else {
+ if(reg == 0x7014)
+ ath_pll_reset_ones(ah);
+
+ ath_hal_reg_write_target(ah, reg, val);
+ }
+}
+
static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
{
for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
t = (struct registerWrite *)(data+i);
- if( t->reg > 0xffff ) {
- HAL_WORD_REG_WRITE(t->reg, t->val);
-#if defined(PROJECT_K2)
- if( t->reg == 0x50040 ) {
- static uint8_t flg=0;
-
- if( flg == 0 ) {
- A_CLOCK_INIT(117);
- A_UART_HWINIT(117*1000*1000, 19200);
- flg = 1;
- }
- }
-#endif
- } else {
-#if defined(PROJECT_K2)
- if( t->reg == 0x7014 ) {
- static uint8_t resetPLL = 0;
-
- if( resetPLL == 0 ) {
- /* here we write to core register */
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
- /* and here to mac register */
- ath_hal_reg_write_target(ah, 0x786c,
- ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
- ath_hal_reg_write_target(ah, 0x786c,
- ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
-
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
- resetPLL = 1;
- }
- }
-#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
- if( t->reg == 0x7014 ){
- static uint8_t resetPLL = 0;
-
- if( resetPLL == 0 ) {
- ath_hal_reg_write_target(ah, 0x7890,
- ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
- ath_hal_reg_write_target(ah, 0x7890,
- ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
- resetPLL = 1;
- }
- }
-#endif
- ath_hal_reg_write_target(ah,t->reg,t->val);
- }
+ ath_hal_reg_write_filter(ah, t->reg, t->val);
}
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
+static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command,
+ A_UINT16 SeqNo, A_UINT8 *data,
+ a_int32_t datalen)
+{
+ struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
+ struct ath_hal *ah = sc->sc_ah;
+ struct register_rmw *buf = (struct register_rmw *)data;
+ int i;
+
+ for (i = 0; i < datalen;
+ i += sizeof(struct register_rmw)) {
+ a_uint32_t val;
+ buf = (struct register_rmw *)(data + i);
+
+ val = ath_reg_read_filter(ah, buf->reg);
+ val &= ~buf->clr;
+ val |= buf->set;
+ ath_hal_reg_write_filter(ah, buf->reg, val);
+ }
+ wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
+}
+
static void ath_vap_delete_tgt(void *Context, A_UINT16 Command,
A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
{
{ath_tx_stats_tgt, WMI_TX_STATS_CMDID, 0},
{ath_rx_stats_tgt, WMI_RX_STATS_CMDID, 0},
{ath_rc_mask_tgt, WMI_BITRATE_MASK_CMDID, 0},
+ {ath_hal_reg_rmw_tgt, WMI_REG_RMW_CMDID, 0},
};
/*****************/
WMI_TX_STATS_CMDID,
WMI_RX_STATS_CMDID,
WMI_BITRATE_MASK_CMDID,
+ WMI_REG_RMW_CMDID,
} WMI_COMMAND_ID;
/*
__WMI_TXSTATUS_EVENT txstatus[HTC_MAX_TX_STATUS];
} POSTPACK WMI_TXSTATUS_EVENT;
+struct register_rmw {
+ a_uint32_t reg;
+ a_uint32_t set;
+ a_uint32_t clr;
+};
+
#ifndef ATH_TARGET
//#include "athendpack.h"
#endif
projects / open-ath9k-htc-firmware.git / commitdiff