*/
#define __adf_os_virt_module_exit(_fn)
-/**
- * initiallize a generic module
- */
-#define __adf_os_virt_module_name(_name)
-
-
#define __adf_os_module_dep(_name, _dep)
#endif
adf_os_virt_module_exit(exit_htc_tgt);
adf_os_module_dep(htc_tgt, adf_net);
adf_os_module_dep(htc_tgt, inproc_hif);
-adf_os_virt_module_name(htc_tgt);
*/
#define adf_os_virt_module_exit(_mod_exit_func) __adf_os_virt_module_exit(_mod_exit_func)
-/**
- * @brief Specify the module's name.
- */
-#define adf_os_virt_module_name(_name) __adf_os_virt_module_name(_name)
-
/**
* @brief Specify the module's dependency on another module.
*/
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "opt_ah.h"
#include "ah.h"
#include "ah_internal.h"
#include <asf_bitmap.h>
-extern struct ath_hal *ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev,
- a_uint32_t flags, HAL_STATUS *status);
+extern struct ath_hal *ar5416Attach(HAL_SOFTC sc, adf_os_device_t dev,
+ HAL_STATUS *status);
struct ath_hal*
ath_hal_attach_tgt(a_uint32_t devid,HAL_SOFTC sc,
{
struct ath_hal *ah = AH_NULL;
- devid = AR5416_DEVID_PCIE;
- ah = ar5416Attach(devid, sc, dev, flags, error);
+ ah = ar5416Attach(sc, dev, error);
return ah;
}
HAL_STATUS
-ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
- a_uint32_t capability, a_uint32_t *result)
-
+ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type)
{
const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
switch (type) {
}
}
-void
-ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt)
-{
- a_int32_t i;
-
- if (rt->rateCodeToIndex[0] != 0)
- return;
-
- for (i = 0; i < 32; i++)
- rt->rateCodeToIndex[i] = (a_uint8_t) -1;
- for (i = 0; i < rt->rateCount; i++) {
- a_uint8_t code = rt->info[i].rateCode;
- a_uint8_t cix = rt->info[i].controlRate;
-
- rt->rateCodeToIndex[code] = i;
- rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
- rt->info[i].lpAckDuration = ath_hal_computetxtime(ah, rt,
- WLAN_CTRL_FRAME_SIZE, cix, AH_FALSE);
- rt->info[i].spAckDuration = ath_hal_computetxtime(ah, rt,
- WLAN_CTRL_FRAME_SIZE, cix, AH_TRUE);
- }
-}
-
#define CCK_SIFS_TIME 10
#define CCK_PREAMBLE_BITS 144
#define CCK_PLCP_BITS 48
numBits = frameLen << 3;
txTime = phyTime + ((numBits * 1000)/kbps);
/* TODO: make sure the same value of txTime can use in all device */
- if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, AH_NULL) != HAL_OK)
+ if (ath_hal_getcapability(ah, HAL_CAP_HT) != HAL_OK)
txTime = txTime + CCK_SIFS_TIME;
break;
case IEEE80211_T_OFDM:
numSymbols = asf_howmany(numBits, bitsPerSymbol);
txTime = OFDM_PREAMBLE_TIME + (numSymbols * OFDM_SYMBOL_TIME);
/* TODO: make sure the same value of txTime can use in all device */
- if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, AH_NULL) != HAL_OK)
+ if (ath_hal_getcapability(ah, HAL_CAP_HT) != HAL_OK)
txTime = txTime + OFDM_SIFS_TIME;
break;
default:
a_int32_t i;
- if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, AH_NULL) == HAL_OK) {
+ if (ath_hal_getcapability(ah, HAL_CAP_HT) == HAL_OK) {
for (i = 0; i < AH_TIMEOUT_11N; i++) {
if ((OS_REG_READ(ah, reg) & mask) == val)
return AH_TRUE;
HAL_BOOL incTrigLevel);
/* Misc Functions */
- HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
- HAL_CAPABILITY_TYPE, a_uint32_t capability,
- a_uint32_t *result);
void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, a_uint32_t);
-
- HAL_BOOL __ahdecl(*ah_updateCTSForBursting)(struct ath_hal *,
- struct ath_desc *, struct ath_desc *,
- struct ath_desc *, struct ath_desc *,
- a_uint32_t, a_uint32_t);
void __ahdecl(*ah_setRxFilter)(struct ath_hal*, a_uint32_t);
/* Target Transmit Functions */
-
- a_uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, a_uint32_t);
HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, a_uint32_t, a_uint32_t txdp);
a_uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, a_uint32_t q);
HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, a_uint32_t);
HAL_BOOL __ahdecl(*ah_abortTxDma)(struct ath_hal *);
- void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *ah,
- struct ath_tx_desc *ds,
+ void __ahdecl(*ah_set11nTxDesc)(struct ath_tx_desc *ds,
a_uint32_t pktLen, HAL_PKT_TYPE type,
a_uint32_t txPower, a_uint32_t keyIx,
HAL_KEY_TYPE keyType,
a_uint32_t flags);
- void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *ah,
- struct ath_tx_desc *ds,
+ void __ahdecl(*ah_set11nRateScenario)(struct ath_tx_desc *ds,
a_uint32_t durUpdateEn,
a_uint32_t rtsctsRate,
- a_uint32_t rtsctsDuration,
HAL_11N_RATE_SERIES series[],
a_uint32_t nseries, a_uint32_t flags);
- void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *ah,
- struct ath_tx_desc *ds, a_uint32_t aggrLen,
+ void __ahdecl(*ah_set11nAggrFirst)(struct ath_tx_desc *ds, a_uint32_t aggrLen,
a_uint32_t numDelims);
- void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *ah,
- struct ath_tx_desc *ds, a_uint32_t numDelims);
- void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *ah,
- struct ath_tx_desc *ds);
- void __ahdecl(*ah_clr11nAggr)(struct ath_hal *ah,
- struct ath_tx_desc *ds);
- void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *ah,
- struct ath_tx_desc *ds,
+ void __ahdecl(*ah_set11nAggrMiddle)(struct ath_tx_desc *ds, a_uint32_t numDelims);
+ void __ahdecl(*ah_set11nAggrLast)(struct ath_tx_desc *ds);
+ void __ahdecl(*ah_clr11nAggr)(struct ath_tx_desc *ds);
+ void __ahdecl(*ah_set11nBurstDuration)(struct ath_tx_desc *ds,
a_uint32_t burstDuration);
- void __ahdecl(*ah_set11nVirtualMoreFrag)(struct ath_hal *ah,
- struct ath_tx_desc *ds, a_uint32_t vmf);
+ void __ahdecl(*ah_set11nVirtualMoreFrag)(struct ath_tx_desc *ds, a_uint32_t vmf);
- HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_tx_desc *,
+ HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_tx_desc *,
a_uint32_t pktLen, a_uint32_t hdrLen,
HAL_PKT_TYPE type, a_uint32_t txPower,
a_uint32_t txRate0, a_uint32_t txTries0,
- a_uint32_t keyIx, a_uint32_t antMode, a_uint32_t flags,
- a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration,
- a_uint32_t compicvLen, a_uint32_t compivLen,
- a_uint32_t comp);
- HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_tx_desc *,
+ a_uint32_t keyIx, a_uint32_t flags,
+ a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration);
+ HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_tx_desc *,
a_uint32_t segLen, HAL_BOOL firstSeg,
HAL_BOOL lastSeg, const struct ath_tx_desc *);
- HAL_BOOL __ahdecl (*ah_fillKeyTxDesc) (struct ath_hal *, struct ath_tx_desc *, HAL_KEY_TYPE);
+ HAL_BOOL __ahdecl (*ah_fillKeyTxDesc) (struct ath_tx_desc *, HAL_KEY_TYPE);
HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_tx_desc *);
- void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, a_uint32_t *);
- void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const a_uint8_t*);
void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
a_uint32_t filter0, a_uint32_t filter1);
-
- a_uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
+
u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
- void __ahdecl(*ah_resetTsf)(struct ath_hal*);
/* Target receive Functions */
- a_uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
void __ahdecl(*ah_setRxDP)(struct ath_hal*, a_uint32_t rxdp);
- HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_rx_desc *,
+ HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_rx_desc *,
a_uint32_t size, a_uint32_t flags);
HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *,
a_uint32_t phyAddr, struct ath_desc *next, u_int64_t tsf);
struct ath_desc *nds,
struct ath_rx_status *rx_stats);
HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
- void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
void __ahdecl(*ah_enableReceive)(struct ath_hal*);
/* Interrupt functions */
HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
- HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
};
adf_os_device_t dev,
a_uint32_t flags, HAL_STATUS* status);
-extern const HAL_RATE_TABLE * __ahdecl ath_hal_getratetable(struct ath_hal *,
- a_uint32_t mode);
-
extern a_uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
const HAL_RATE_TABLE *rates,
a_uint32_t frameLen,
extern HAL_BOOL ath_hal_wait(struct ath_hal *, a_uint32_t reg,
a_uint32_t mask, a_uint32_t val);
-extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list);
-
/* allocate and free memory */
extern void *ath_hal_malloc(size_t);
extern void ath_hal_free(void *);
* this routine to support chip-specific capabilities.
*/
extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
- HAL_CAPABILITY_TYPE type, a_uint32_t capability,
- a_uint32_t *result);
+ HAL_CAPABILITY_TYPE type);
extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
HAL_CAPABILITY_TYPE type, a_uint32_t capability,
a_uint32_t setting, HAL_STATUS *status);
#include <adf_os_atomic.h>
#include <adf_nbuf.h>
#include <adf_net.h>
-#include <adf_net_types.h>
#include "ah.h"
#include<ah_internal.h>
return ah;
}
-void
-ath_hal_detach(struct ath_hal *ah)
-{
- (*ah->ah_detach)(ah);
-}
-
extern void *global_hdl;
/*
adf_os_mem_free(p);
}
-void __ahdecl
-ath_hal_memzero(void *dst, adf_os_size_t n)
-{
- adf_os_mem_set(dst, 0, n);
-}
-
void * __ahdecl
ath_hal_memcpy(void *dst, const void *src, adf_os_size_t n)
{
return 0;
}
-/*
- * Print/log message support.
- */
-void __ahdecl
-ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)
-{
-}
-
enum {
DEV_ATH = 9, /* XXX must match driver */
};
adf_os_module_dep(hal, adf_net);
adf_os_module_dep(hal, hal);
-adf_os_virt_module_name(hal);
extern void* __ahdecl ath_hal_ioremap(a_uint32_t addr, a_uint32_t len);
#define OS_REMAP(_addr, _len) ath_hal_ioremap(_addr, _len)
-#define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n))
-extern void __ahdecl ath_hal_memzero(void *, size_t);
#define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n)
extern void * __ahdecl ath_hal_memcpy(void *, const void *, size_t);
#define AH_USE_EEPROM 0x00000001
extern struct ath_hal *_ath_hal_attach_tgt( a_uint32_t, HAL_SOFTC, adf_os_device_t,
a_uint32_t flags, void* status);
-extern void ath_hal_detach(struct ath_hal *);
#endif /* _ATH_AH_OSDEP_H_ */
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "opt_ah.h"
#include "ah.h"
#include "ah_internal.h"
#include "ar5416.h"
#include "ar5416reg.h"
-#include "ar5416phy.h"
#include "ar5416desc.h"
#define N(a) (sizeof(a)/sizeof(a[0]))
/* Transmit functions */
.ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
- .ah_getTxDP = ar5416GetTxDP,
.ah_setTxDP = ar5416SetTxDP,
.ah_numTxPending = ar5416NumTxPending,
.ah_startTxDma = ar5416StartTxDma,
.ah_stopTxDma = ar5416StopTxDma,
-
- .ah_getTxIntrQueue = ar5416GetTxIntrQueue,
+
.ah_abortTxDma = ar5416AbortTxDma,
/* Misc Functions */
- .ah_getCapability = ar5416GetCapability,
- .ah_getTsf32 = ar5416GetTsf32,
.ah_getTsf64 = ar5416GetTsf64,
- .ah_resetTsf = ar5416ResetTsf,
.ah_setRxFilter = ar5416SetRxFilter,
/* RX Functions */
- .ah_getRxDP = ar5416GetRxDP,
.ah_setRxDP = ar5416SetRxDP,
.ah_stopDmaReceive = ar5416StopDmaReceive,
.ah_enableReceive = ar5416EnableReceive,
- .ah_startPcuReceive = ar5416StartPcuReceive,
.ah_stopPcuReceive = ar5416StopPcuReceive,
/* Interrupt Functions */
.ah_isInterruptPending = ar5416IsInterruptPending,
.ah_getPendingInterrupts = ar5416GetPendingInterrupts,
- .ah_getInterrupts = ar5416GetInterrupts,
.ah_setInterrupts = ar5416SetInterrupts,
},
};
}
struct ath_hal *
-ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev,
- a_uint32_t flags, HAL_STATUS *status)
+ar5416Attach(HAL_SOFTC sc, adf_os_device_t dev, HAL_STATUS *status)
{
struct ath_hal_5416 *ahp;
struct ath_hal *ah;
ah->ah_dev = dev;
ah->ah_sc = sc;
-
- /* If its a Owl 2.0 chip then change the hal structure to
- point to the Owl 2.0 ar5416_hal_20 structure */
- if(1) {
- ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
- ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
- ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
- ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
- ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
- ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
- ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
- ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
- ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
- ah->ah_updateCTSForBursting = NULL;
- ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
- ah->ah_reqTxIntrDesc = ar5416IntrReqTxDesc_20;
- ah->ah_fillTxDesc = ar5416FillTxDesc_20;
- ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
- ah->ah_procTxDesc = ar5416ProcTxDesc_20;
- ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
- }
+
+ ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
+ ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
+ ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
+ ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
+ ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
+ ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
+ ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
+ ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
+ ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
+ ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
+ ah->ah_fillTxDesc = ar5416FillTxDesc_20;
+ ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
+ ah->ah_procTxDesc = ar5416ProcTxDesc_20;
+ ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
return ah;
}
return AH_TRUE;
}
-HAL_INT ar5416GetInterrupts(struct ath_hal *ah)
-{
- return AH5416(ah)->ah_maskReg;
-}
-
HAL_INT
ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
{
return omask;
}
-/****************/
-/* Capabilities */
-/****************/
-
-HAL_STATUS ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
- a_uint32_t capability, a_uint32_t *result)
-
-{
- return ath_hal_getcapability(ah, type, capability, result);
-}
-
/****************/
/* TSF Handling */
/****************/
return tsf;
}
-a_uint32_t ar5416GetTsf32(struct ath_hal *ah)
-{
- return OS_REG_READ(ah, AR_TSF_L32);
-}
-
-void ar5416ResetTsf(struct ath_hal *ah)
-{
- a_int32_t count;
-
- count = 0;
-
- while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
- count++;
- if (count > 10) {
- break;
- }
- OS_DELAY(10);
- }
- OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
-}
-
/******/
/* RX */
/******/
-
-a_uint32_t ar5416GetRxDP(struct ath_hal *ath)
-{
- return OS_REG_READ(ath, AR_RXDP);
-}
-
-
void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
{
OS_REG_WRITE(ah, AR_RXDP, rxdp);
HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
}
-void ar5416SetMulticastFilter(struct ath_hal *ah, a_uint32_t filter0, a_uint32_t filter1)
-{
- OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
- OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
-}
-
-HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
-{
- a_uint32_t val;
-
- if (ix >= 64)
- return AH_FALSE;
- if (ix >= 32) {
- val = OS_REG_READ(ah, AR_MCAST_FIL1);
- OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
- } else {
- val = OS_REG_READ(ah, AR_MCAST_FIL0);
- OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
- }
- return AH_TRUE;
-}
-
HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
{
OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
}
}
-HAL_BOOL ar5416SetMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
-{
- a_uint32_t val;
-
- if (ix >= 64)
- return AH_FALSE;
- if (ix >= 32) {
- val = OS_REG_READ(ah, AR_MCAST_FIL1);
- OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
- } else {
- val = OS_REG_READ(ah, AR_MCAST_FIL0);
- OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
- }
- return AH_TRUE;
-}
-
-void ar5416StartPcuReceive(struct ath_hal *ah)
-{
- OS_REG_CLR_BIT(ah, AR_DIAG_SW,
- (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
-}
-
void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
{
a_uint32_t phybits;
OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
}
-HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *ah, struct ath_rx_desc *ds,
+HAL_BOOL ar5416SetupRxDesc_20(struct ath_rx_desc *ds,
a_uint32_t size, a_uint32_t flags)
{
struct ar5416_desc *ads = AR5416DESC(ds);
return (newLevel != curLevel);
}
-a_uint32_t ar5416GetTxDP(struct ath_hal *ah, a_uint32_t q)
-{
- HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
- return OS_REG_READ(ah, AR_QTXDP(q));
-}
-
HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
{
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
return (i != 0);
}
-void ar5416GetTxIntrQueue(struct ath_hal *ah, a_uint32_t *txqs)
-{
- struct ath_hal_5416 *ahp = AH5416(ah);
- *txqs &= ahp->ah_intrTxqs;
- ahp->ah_intrTxqs &= ~(*txqs);
-}
-
-void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds)
-{
- struct ar5416_desc *ads = AR5416DESC(ds);
- ads->ds_ctl0 |= AR_TxIntrReq;
-}
-
-HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+HAL_BOOL ar5416SetupTxDesc_20(struct ath_tx_desc *ds,
a_uint32_t pktLen,
a_uint32_t hdrLen,
HAL_PKT_TYPE type,
a_uint32_t txPower,
a_uint32_t txRate0, a_uint32_t txTries0,
a_uint32_t keyIx,
- a_uint32_t antMode,
a_uint32_t flags,
a_uint32_t rtsctsRate,
- a_uint32_t rtsctsDuration,
- a_uint32_t compicvLen,
- a_uint32_t compivLen,
- a_uint32_t comp)
+ a_uint32_t rtsctsDuration)
{
#define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
#undef RTSCTS
}
-HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+HAL_BOOL ar5416FillTxDesc_20(struct ath_tx_desc *ds,
a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
const struct ath_tx_desc *ds0)
{
return AH_TRUE;
}
-HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_tx_desc *ds,
HAL_KEY_TYPE keyType)
{
struct ar5416_desc *ads = AR5416DESC(ds);
return HAL_OK;
}
-void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+void ar5416Set11nTxDesc_20(struct ath_tx_desc *ds,
a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
a_uint32_t keyIx, HAL_KEY_TYPE keyType,
a_uint32_t flags)
ads->ds_ctl6 = SM(keyType, AR_EncrType);
}
-#ifdef MAGPIE_MERLIN
-
-void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+void ar5416Set11nRateScenario_20(struct ath_tx_desc *ds,
a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
- a_uint32_t rtsctsDuration,
HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
a_uint32_t flags)
{
- struct ar5416_desc *ads = AR5416DESC(ds);
- a_uint32_t ds_ctl0;
+ struct ar5416_desc *ads = AR5416DESC(ds);
+ a_uint32_t ds_ctl0;
- HALASSERT(nseries == 4);
- (void)nseries;
+ HALASSERT(nseries == 4);
+ (void)nseries;
- /*
- * Rate control settings override
- */
+ /*
+ * Rate control settings override
+ */
ds_ctl0 = ads->ds_ctl0;
- if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
+ if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
if (flags & HAL_TXDESC_RTSENA) {
ds_ctl0 &= ~AR_CTSEnable;
ds_ctl0 |= AR_RTSEnable;
ds_ctl0 &= ~AR_RTSEnable;
ds_ctl0 |= AR_CTSEnable;
}
- } else {
+ } else {
+ /* this line is only difference between merlin and k2
+ * Current one is for merlin */
ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
- }
+ }
ads->ds_ctl0 = ds_ctl0;
- ads->ds_ctl2 = set11nTries(series, 0)
- | set11nTries(series, 1)
- | set11nTries(series, 2)
- | set11nTries(series, 3)
- | (durUpdateEn ? AR_DurUpdateEn : 0);
-
- ads->ds_ctl3 = set11nRate(series, 0)
- | set11nRate(series, 1)
- | set11nRate(series, 2)
- | set11nRate(series, 3);
-
- ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
- | set11nPktDurRTSCTS(series, 1);
-
- ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
- | set11nPktDurRTSCTS(series, 3);
-
- ads->ds_ctl7 = set11nRateFlags(series, 0)
- | set11nRateFlags(series, 1)
- | set11nRateFlags(series, 2)
- | set11nRateFlags(series, 3)
- | SM(rtsctsRate, AR_RTSCTSRate);
-}
-
-#else
-
-void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
- a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
- a_uint32_t rtsctsDuration,
- HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
- a_uint32_t flags)
-{
- struct ar5416_desc *ads = AR5416DESC(ds);
- a_uint32_t ds_ctl0;
-
- HALASSERT(nseries == 4);
- (void)nseries;
-
- /*
- * Rate control settings override
- */
- if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
- ds_ctl0 = ads->ds_ctl0;
+ ads->ds_ctl2 = set11nTries(series, 0)
+ | set11nTries(series, 1)
+ | set11nTries(series, 2)
+ | set11nTries(series, 3)
+ | (durUpdateEn ? AR_DurUpdateEn : 0);
- if (flags & HAL_TXDESC_RTSENA) {
- ds_ctl0 &= ~AR_CTSEnable;
- ds_ctl0 |= AR_RTSEnable;
- } else {
- ds_ctl0 &= ~AR_RTSEnable;
- ds_ctl0 |= AR_CTSEnable;
- }
+ ads->ds_ctl3 = set11nRate(series, 0)
+ | set11nRate(series, 1)
+ | set11nRate(series, 2)
+ | set11nRate(series, 3);
- ads->ds_ctl0 = ds_ctl0;
- }
-
- ads->ds_ctl2 = set11nTries(series, 0)
- | set11nTries(series, 1)
- | set11nTries(series, 2)
- | set11nTries(series, 3)
- | (durUpdateEn ? AR_DurUpdateEn : 0);
-
- ads->ds_ctl3 = set11nRate(series, 0)
- | set11nRate(series, 1)
- | set11nRate(series, 2)
- | set11nRate(series, 3);
+ ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
+ | set11nPktDurRTSCTS(series, 1);
- ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
- | set11nPktDurRTSCTS(series, 1);
+ ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
+ | set11nPktDurRTSCTS(series, 3);
- ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
- | set11nPktDurRTSCTS(series, 3);
-
- ads->ds_ctl7 = set11nRateFlags(series, 0)
- | set11nRateFlags(series, 1)
- | set11nRateFlags(series, 2)
- | set11nRateFlags(series, 3)
- | SM(rtsctsRate, AR_RTSCTSRate);
+ ads->ds_ctl7 = set11nRateFlags(series, 0)
+ | set11nRateFlags(series, 1)
+ | set11nRateFlags(series, 2)
+ | set11nRateFlags(series, 3)
+ | SM(rtsctsRate, AR_RTSCTSRate);
}
-#endif
-
-void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t aggrLen,
+void ar5416Set11nAggrFirst_20(struct ath_tx_desc *ds, a_uint32_t aggrLen,
a_uint32_t numDelims)
{
struct ar5416_desc *ads = AR5416DESC(ds);
SM(numDelims, AR_PadDelim);
}
-void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t numDelims)
+void ar5416Set11nAggrMiddle_20(struct ath_tx_desc *ds, a_uint32_t numDelims)
{
struct ar5416_desc *ads = AR5416DESC(ds);
a_uint32_t ctl6;
ads->ds_ctl6 = ctl6;
}
-void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds)
+void ar5416Set11nAggrLast_20(struct ath_tx_desc *ds)
{
struct ar5416_desc *ads = AR5416DESC(ds);
ads->ds_ctl6 &= ~AR_PadDelim;
}
-void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_tx_desc *ds)
+void ar5416Clr11nAggr_20(struct ath_tx_desc *ds)
{
struct ar5416_desc *ads = AR5416DESC(ds);
ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
}
-void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+void ar5416Set11nBurstDuration_20(struct ath_tx_desc *ds,
a_uint32_t burstDuration)
{
struct ar5416_desc *ads = AR5416DESC(ds);
ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
}
-void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+void ar5416Set11nVirtualMoreFrag_20(struct ath_tx_desc *ds,
a_uint32_t vmf)
{
struct ar5416_desc *ads = AR5416DESC(ds);
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "opt_ah.h"
#include "ah.h"
#include "ah_internal.h"
#include "ar5416.h"
extern void ar5416StartPcuReceive(struct ath_hal *ah);
extern void ar5416StopPcuReceive(struct ath_hal *ah);
extern void ar5416AbortPcuReceive(struct ath_hal *ah);
-extern void ar5416SetMulticastFilter(struct ath_hal *ah,
- a_uint32_t filter0, a_uint32_t filter1);
-extern HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *, a_uint32_t ix);
-extern HAL_BOOL ar5416SetMulticastFilterIndex(struct ath_hal *, a_uint32_t ix);
extern a_uint32_t ar5416GetRxFilter(struct ath_hal *ah);
extern void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits);
extern HAL_BOOL ar5416UpdateCTSForBursting_20(struct ath_hal *, struct ath_desc *,
struct ath_desc *,struct ath_desc *, struct ath_desc *,
a_uint32_t, a_uint32_t);
-extern HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+extern HAL_BOOL ar5416SetupTxDesc_20(struct ath_tx_desc *ds,
a_uint32_t pktLen, a_uint32_t hdrLen, HAL_PKT_TYPE type, a_uint32_t txPower,
a_uint32_t txRate0, a_uint32_t txTries0,
- a_uint32_t keyIx, a_uint32_t antMode, a_uint32_t flags,
- a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration,
- a_uint32_t compicvLen, a_uint32_t compivLen, a_uint32_t comp);
-extern HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+ a_uint32_t keyIx, a_uint32_t flags,
+ a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration);
+extern HAL_BOOL ar5416FillTxDesc_20(struct ath_tx_desc *ds,
a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
const struct ath_tx_desc *ds0);
-extern HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *,HAL_KEY_TYPE);
+extern HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_tx_desc *,HAL_KEY_TYPE);
extern HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *);
-extern void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds);
-extern void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+extern void ar5416Set11nTxDesc_20(struct ath_tx_desc *ds,
a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
a_uint32_t keyIx, HAL_KEY_TYPE keyType, a_uint32_t flags);
-extern void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
- a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration, HAL_11N_RATE_SERIES series[],
+extern void ar5416Set11nRateScenario_20(struct ath_tx_desc *ds,
+ a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, HAL_11N_RATE_SERIES series[],
a_uint32_t nseries, a_uint32_t flags);
-extern void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+extern void ar5416Set11nAggrFirst_20(struct ath_tx_desc *ds,
a_uint32_t aggrLen, a_uint32_t numDelims);
-extern void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+extern void ar5416Set11nAggrMiddle_20(struct ath_tx_desc *ds,
a_uint32_t numDelims);
-extern void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds);
-extern void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_tx_desc *ds);
-extern void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+extern void ar5416Set11nAggrLast_20(struct ath_tx_desc *ds);
+extern void ar5416Clr11nAggr_20(struct ath_tx_desc *ds);
+extern void ar5416Set11nBurstDuration_20(struct ath_tx_desc *ds,
a_uint32_t burstDuration);
-extern void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+extern void ar5416Set11nVirtualMoreFrag_20(struct ath_tx_desc *ds,
a_uint32_t vmf);
-extern HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *,
- struct ath_rx_desc *, a_uint32_t size, a_uint32_t flags);
+extern HAL_BOOL ar5416SetupRxDesc_20(struct ath_rx_desc *,
+ a_uint32_t size, a_uint32_t flags);
extern HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah,
struct ath_rx_desc *, a_uint32_t,
struct ath_desc *,
+++ /dev/null
-/*
- * Copyright (c) 2013 Qualcomm Atheros, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted (subject to the limitations in the
- * disclaimer below) provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * * Neither the name of Qualcomm Atheros nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
- * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
- * Copyright (c) 2002-2005 Atheros Communications, Inc.
- * All rights reserved.
- *
- * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/hal/main/ar5416/ar5416phy.h#1 $
- */
-#ifndef _DEV_ATH_AR5416PHY_H_
-#define _DEV_ATH_AR5416PHY_H_
-
-/* PHY registers */
-#define AR_PHY_BASE 0x9800 /* base address of phy regs */
-#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
-
-#define AR_PHY_TEST 0x9800 /* PHY test control */
-#define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
-#define RFSILENT_BB 0x00002000 /* shush bb */
-
-/* TX99_11N_CHANGE begin */
-#define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
-#define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
-#define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
-#define AR_PHY_TESTCTRL_TXSRC_ALT_S 7
-#define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
-#define AR_PHY_TESTCTRL_TXSRC_SRC_S 1
-/* TX99_11N_CHANGE end */
-
-
-#define AR_PHY_TURBO 0x9804 /* frame control register */
-#define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
-#define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
-#define AR_PHY_FC_DYN2040_EN 0x00000004 /* Enable dyn 20/40 mode */
-#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
-#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
-#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
-#define AR_PHY_FC_HT_EN 0x00000040 /* ht enable */
-#define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
-#define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
-#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
-
-#define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */
-#define AR_PHY_TIMING2_USE_FORCE 0x00001000
-#define AR_PHY_TIMING2_FORCE_VAL 0x00000fff
-
-#define AR_PHY_TIMING3 0x9814 /* Timing control 3 */
-#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
-#define AR_PHY_TIMING3_DSC_MAN_S 17
-#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
-#define AR_PHY_TIMING3_DSC_EXP_S 13
-
-#define AR_PHY_CHIP_ID 0x9818 /* PHY chip revision ID */
-#define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */
-#define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */
-#define AR_PHY_CHIP_ID_SOWL_REV_0 0xb0 /* 9160 Rev 0 (sowl 1.0) BB */
-
-#define AR_PHY_ACTIVE 0x981C /* activation register */
-#define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */
-#define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */
-
-#define AR_PHY_RF_CTL2 0x9824
-#define AR_PHY_TX_END_DATA_START 0x000000FF
-#define AR_PHY_TX_END_DATA_START_S 0
-#define AR_PHY_TX_END_PA_ON 0x0000FF00
-#define AR_PHY_TX_END_PA_ON_S 8
-
-
-#define AR_PHY_RF_CTL3 0x9828
-#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
-#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
-
-#define AR_PHY_ADC_CTL 0x982C
-#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
-#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
-#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
-#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 /* BB Rev 4.2+ only */
-#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 /* BB Rev 4.2+ only */
-#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
-#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
-
-#define AR_PHY_ADC_SERIAL_CTL 0x9830
-#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
-#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
-
-#define AR_PHY_RF_CTL4 0x9834
-#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
-#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
-#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
-#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
-#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
-#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
-#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
-#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
-
-/* TX99_11N_CHANGE begin */
-#define AR_PHY_BB_XP_PA_CTL 0x9838
-#define AR_PHY_BB_XPAA_ACTIVE_HIGH 0x00000001
-#define AR_PHY_BB_XPAB_ACTIVE_HIGH 0x00000002
-#define AR_PHY_BB_XPAB_ACTIVE_HIGH_S 1
-
-#define AR_PHY_TSTDAC_CONST 0x983C
-#define AR_PHY_TSTDAC_CONST_Q 0x0003FE00
-#define AR_PHY_TSTDAC_CONST_Q_S 9
-#define AR_PHY_TSTDAC_CONST_I 0x000001FF
-/* TX99_11N_CHANGE end */
-
-#define AR_PHY_SETTLING 0x9844
-#define AR_PHY_SETTLING_SWITCH 0x00003F80
-#define AR_PHY_SETTLING_SWITCH_S 7
-
-#define AR_PHY_RXGAIN 0x9848
-#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
-#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
-#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
-#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
-
-#define AR_PHY_DESIRED_SZ 0x9850
-#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
-#define AR_PHY_DESIRED_SZ_ADC_S 0
-#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
-#define AR_PHY_DESIRED_SZ_PGA_S 8
-#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
-#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
-
-#define AR_PHY_FIND_SIG 0x9858
-#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
-#define AR_PHY_FIND_SIG_FIRSTEP_S 12
-#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
-#define AR_PHY_FIND_SIG_FIRPWR_S 18
-
-#define AR_PHY_AGC_CTL1 0x985C
-#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
-#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
-#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
-#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
-
-#define AR_PHY_AGC_CONTROL 0x9860 /* chip calibration and noise floor setting */
-#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */
-#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calculation */
-
-#define AR_PHY_CCA 0x9864
-#define AR_PHY_MINCCA_PWR 0x0FF80000
-#define AR_PHY_MINCCA_PWR_S 19
-#define AR_PHY_CCA_THRESH62 0x0007F000
-#define AR_PHY_CCA_THRESH62_S 12
-
-#define AR_PHY_SFCORR_LOW 0x986C
-#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
-#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
-#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
-#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
-#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
-#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
-#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
-
-#define AR_PHY_SFCORR 0x9868
-#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
-#define AR_PHY_SFCORR_M2COUNT_THR_S 0
-#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
-#define AR_PHY_SFCORR_M1_THRESH_S 17
-#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
-#define AR_PHY_SFCORR_M2_THRESH_S 24
-
-#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
-#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
-#define AR_PHY_SLEEP_SCAL 0x9878
-
-#define AR_PHY_PLL_CTL 0x987c /* PLL control register */
-#define AR_PHY_PLL_CTL_40 0xaa /* 40 MHz */
-#define AR_PHY_PLL_CTL_40_5413 0x04
-#define AR_PHY_PLL_CTL_44 0xab /* 44 MHz for 11b, 11g */
-#define AR_PHY_PLL_CTL_44_2133 0xeb /* 44 MHz for 11b, 11g */
-#define AR_PHY_PLL_CTL_40_2133 0xea /* 40 MHz for 11a, turbos */
-
-#define AR_PHY_RX_DELAY 0x9914 /* analog pow-on time (100ns) */
-#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
-
-#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) /* timing control */
-#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */
-#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */
-#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */
-#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */
-#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */
-#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */
-#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */
-#define AR_PHY_TIMING_CTRL4_DO_IQCAL 0x10000 /* perform IQ calibration */
-
-#define AR_PHY_TIMING5 0x9924
-#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
-#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
-
-#define AR_PHY_POWER_TX_RATE1 0x9934
-#define AR_PHY_POWER_TX_RATE2 0x9938
-#define AR_PHY_POWER_TX_RATE_MAX 0x993c
-#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
-
-#define AR_PHY_FRAME_CTL 0x9944
-#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
-#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
-
-#define AR_PHY_TXPWRADJ 0x994C /* BB Rev 4.2+ only */
-#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
-#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
-#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
-#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
-
-#define AR_PHY_RADAR_0 0x9954 /* radar detection settings */
-#define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */
-#define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */
-#define AR_PHY_RADAR_0_INBAND_S 1
-#define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */
-#define AR_PHY_RADAR_0_PRSSI_S 6
-#define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */
-#define AR_PHY_RADAR_0_HEIGHT_S 12
-#define AR_PHY_RADAR_0_RRSSI 0x00FC0000 /* Radar rssi threshold */
-#define AR_PHY_RADAR_0_RRSSI_S 18
-#define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */
-#define AR_PHY_RADAR_0_FIRPWR_S 24
-
-#define AR_PHY_RADAR_1 0x9958 /* AR5413+ radar settigns */
-#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 /* enable to check radar relative power */
-#define AR_PHY_RADAR_1_USE_FIR128 0x00400000 /* enable to use the average inband power
- * measured over 128 cycles
- */
-#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 /* relative pwr thresh */
-#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
-#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 /* Enable to block radar check if weak
- * OFDM sig or pkt is immediately after
- * tx to rx transition
- */
-#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 /* Enable to use max rssi */
-#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 /* Enable to use pulse relative step check */
-#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 /* Pulse relative step threshold */
-#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
-#define AR_PHY_RADAR_1_MAXLEN 0x000000FF /* Max length of radar pulse */
-#define AR_PHY_RADAR_1_MAXLEN_S 0
-
-#define AR_PHY_SWITCH_CHAIN_0 0x9960
-#define AR_PHY_SWITCH_COM 0x9964
-
-#define AR_PHY_SIGMA_DELTA 0x996C /* AR5312 only */
-#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
-#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
-#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
-#define AR_PHY_SIGMA_DELTA_FILT2_S 3
-#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
-#define AR_PHY_SIGMA_DELTA_FILT1_S 8
-#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
-#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
-
-#define AR_PHY_RESTART 0x9970 /* restart */
-#define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */
-#define AR_PHY_RESTART_DIV_GC_S 18
-
-#define AR_PHY_RFBUS_REQ 0x997C
-#define AR_PHY_RFBUS_REQ_EN 0x00000001
-
-#define AR_PHY_RX_CHAINMASK 0x99a4
-
-#define AR_PHY_EXT_CCA 0x99bc
-#define AR_PHY_EXT_CCA_THRESH62 0x007F0000 // [22:16] not replicated
-#define AR_PHY_EXT_CCA_THRESH62_S 16
-#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
-#define AR_PHY_EXT_MINCCA_PWR_S 23
-
-#define AR_PHY_HALFGI 0x99D0 /* Timing control 3 */
-#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
-#define AR_PHY_HALFGI_DSC_MAN_S 4
-#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
-#define AR_PHY_HALFGI_DSC_EXP_S 0
-
-#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
-
-#define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */
-#define AR_PHY_REFCLKDLY 0x99f4
-#define AR_PHY_REFCLKPD 0x99f8
-
-#define AR_PHY_CALMODE 0x99f0
-/* PHY IQ calibration results */
-#define AR_PHY_IQCAL_RES_PWR_MEAS_I(_i) (0x9c10 + ((_i) << 12)) /* power measurement for I */
-#define AR_PHY_IQCAL_RES_PWR_MEAS_Q(_i) (0x9c14 + ((_i) << 12)) /* power measurement for Q */
-#define AR_PHY_IQCAL_RES_IQ_CORR_MEAS(_i) (0x9c18 + ((_i) << 12)) /* IQ correlation measurement */
-
-#define AR_PHY_CURRENT_RSSI 0x9c1c /* rssi of current frame rx'd */
-
-#define AR_PHY_RFBUS_GRANT 0x9C20
-#define AR_PHY_RFBUS_GRANT_EN 0x00000001
-
-#define AR_PHY_MODE 0xA200 /* Mode register */
-#define AR_PHY_MODE_AR2133 0x08 /* AR2133 */
-#define AR_PHY_MODE_AR5111 0x00 /* AR5111/AR2111 */
-#define AR_PHY_MODE_AR5112 0x08 /* AR5112*/
-#define AR_PHY_MODE_DYNAMIC 0x04 /* dynamic CCK/OFDM mode */
-#define AR_PHY_MODE_RF2GHZ 0x02 /* 2.4 GHz */
-#define AR_PHY_MODE_RF5GHZ 0x00 /* 5 GHz */
-#define AR_PHY_MODE_CCK 0x01 /* CCK */
-#define AR_PHY_MODE_OFDM 0x00 /* OFDM */
-
-#define AR_PHY_CCK_TX_CTRL 0xA204
-#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
-
-#define AR_PHY_CCK_DETECT 0xA208
-#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
-#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
-#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 // [12:6] settling time for antenna switch
-#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
-#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
-
-#define AR_PHY_GAIN_2GHZ 0xA20C
-#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
-#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
-#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
-#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
-#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
-#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
-
-#define AR_PHY_CCK_RXCTRL4 0xA21C
-#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
-#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
-
-#define AR_PHY_DAG_CTRLCCK 0xA228
-#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 /* BB Rev 4.2+ only */
-#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 /* BB Rev 4.2+ only */
-#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 /* BB Rev 4.2+ only */
-
-#define AR_PHY_POWER_TX_RATE3 0xA234
-#define AR_PHY_POWER_TX_RATE4 0xA238
-
-#define AR_PHY_SCRM_SEQ_XR 0xA23C
-#define AR_PHY_HEADER_DETECT_XR 0xA240
-#define AR_PHY_CHIRP_DETECTED_XR 0xA244
-#define AR_PHY_BLUETOOTH 0xA254
-
-#define AR_PHY_TPCRG1 0xA258 /* ar2413 power control */
-#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
-#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
-
-#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
-#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
-#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
-#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
-#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
-#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
-//
-
-#define AR_PHY_ANALOG_SWAP 0xa268
-#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
-
-#define AR_PHY_TPCRG5 0xA26C /* ar2413 power control */
-#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
-#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
-
-#define AR_PHY_POWER_TX_RATE5 0xA38C
-#define AR_PHY_POWER_TX_RATE6 0xA390
-
-#define AR_PHY_CAL_CHAINMASK 0xA39C
-
-#define AR_PHY_POWER_TX_SUB 0xA3C8
-#define AR_PHY_POWER_TX_RATE7 0xA3CC
-#define AR_PHY_POWER_TX_RATE8 0xA3D0
-#define AR_PHY_POWER_TX_RATE9 0xA3D4
-
-#define AR_PHY_CH1_CCA 0xa864
-#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
-#define AR_PHY_CH1_MINCCA_PWR_S 19
-
-#define AR_PHY_CH2_CCA 0xb864
-#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
-#define AR_PHY_CH2_MINCCA_PWR_S 19
-
-#define AR_PHY_CH1_EXT_CCA 0xa9bc
-#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
-#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
-
-#define AR_PHY_CH2_EXT_CCA 0xb9bc
-#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
-#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
-
-
-#ifdef MAGPIE_MERLIN
-
-#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
-#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
-#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
-#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
-
-#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* Enable noise floor calibration to happen */
-#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* Don't update noise floor automatically */
-
-#define AR9280_PHY_MINCCA_PWR 0x1FF00000
-#define AR9280_PHY_MINCCA_PWR_S 20
-#define AR9280_PHY_CCA_THRESH62 0x000FF000
-#define AR9280_PHY_CCA_THRESH62_S 12
-
-#define AR_PHY_CCA_MAX_GOOD_VALUE -85
-#define AR_PHY_CCA_MAX_HIGH_VALUE -62
-#define AR_PHY_CCA_MIN_BAD_VALUE -121
-
-#define AR_PHY_SYNTH_CONTROL 0x9874
-#define AR9280_PHY_CURRENT_RSSI 0x9c3c
-
-#define AR9280_PHY_CURRENT_RSSI 0x9c3c
-
-#define AR_PHY_XPA_CFG 0xA3D8
-#define AR_PHY_FORCE_XPA_CFG 0x000000001
-#define AR_PHY_FORCE_XPA_CFG_S 0
-
-#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
-#define AR9280_PHY_CH1_MINCCA_PWR_S 20
-
-#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
-#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
-
-#endif
-
-
-
-#endif /* _DEV_ATH_AR5416PHY_H_ */
#include <adf_net.h>
#include <if_llc.h>
-#include <if_ethersubr.h>
#include "ieee80211_var.h"
-#include "_ieee80211.h"
#include "ieee80211.h"
#include <wlan_hdr.h>
return size;
}
-/*
- * Return the size of the 802.11 header for a management or data frame.
- */
-static __inline a_int32_t
-ieee80211_hdrsize_padding(const void *data)
-{
- const struct ieee80211_frame *wh = data;
- a_int32_t size = sizeof(struct ieee80211_frame);
- a_int32_t is4addr = (wh->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS;
- a_int32_t is_qos = IEEE80211_QOS_HAS_SEQ(wh);
-
- /* NB: we don't handle control frames */
- adf_os_assert((wh->i_fc[0]&IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL);
- if (is4addr)
- size += IEEE80211_ADDR_LEN;
- if (is_qos)
- size += sizeof(a_uint16_t);
- if (is4addr && is_qos)
- size += sizeof(a_uint16_t);
- return size;
-}
-
/*
* Like ieee80211_hdrsize, but handles any type of frame.
*/
#include <adf_os_irq.h>
#include <if_ath_pci.h>
-#include "if_ethersubr.h"
#include "if_llc.h"
#include "ieee80211_var.h"
-#include "ieee80211_proto.h"
#include "if_athrate.h"
#include "if_athvar.h"
#include "ah_desc.h"
+#include "ah.h"
static a_int32_t ath_numrxbufs = -1;
static a_int32_t ath_numrxdescs = -1;
void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
-/*************/
-/* Utilities */
-/*************/
-
-#undef adf_os_cpu_to_le16
-
-static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
-{
- return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
-}
-
/*
* Extend a 32 bit TSF to 64 bit, taking wrapping into account.
*/
static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
{
+ struct ath_hal *ah = sc->sc_ah;
u_int64_t tsf;
u_int32_t tsf_low;
u_int64_t tsf64;
- tsf = ath_hal_gettsf64(sc->sc_ah);
+ tsf = ah->ah_getTsf64(ah);
tsf_low = tsf & 0xffffffff;
tsf64 = (tsf & ~0xffffffffULL) | rstamp;
switch (mode) {
case IEEE80211_MODE_11NA:
- sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11NA);
+ sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NA);
break;
case IEEE80211_MODE_11NG:
- sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11NG);
+ sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NG);
break;
default:
return 0;
ds->ds_link = 0;
adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
- ath_hal_setuprxdesc(ah, ds,
- adf_nbuf_tailroom(ds->ds_nbuf),
- 0);
+ ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0);
if (sc->sc_rxlink == NULL) {
- ath_hal_putrxbuf(ah, ds->ds_daddr);
+ ah->ah_setRxDP(ah, ds->ds_daddr);
}
else {
*sc->sc_rxlink = ds->ds_daddr;
}
sc->sc_rxlink = &ds->ds_link;
- ath_hal_rxena(ah);
+ ah->ah_enableReceive(ah);
return 0;
}
((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
- tsf = ath_hal_gettsf64(ah);
+ tsf = ah->ah_getTsf64(ah);
bf = asf_tailq_first(&sc->sc_rxbuf);
ds = asf_tailq_first(&sc->sc_rxdesc);
continue;
}
- retval = ath_hal_rxprocdescfast(ah, ds, ds->ds_daddr,
+ retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr,
PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
if (HAL_EINPROGRESS == retval) {
break;
}
ds = asf_tailq_first(&sc->sc_rxdesc);
- ath_hal_putrxbuf(ah, ds->ds_daddr);
+ ah->ah_setRxDP(ah, ds->ds_daddr);
return 0;
}
} while(1);
sc->sc_imask |= HAL_INT_RX;
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
}
/*******************/
rt = sc->sc_currates;
rate = rt->info[rix].rateCode;
- ath_hal_setuptxdesc(ah, ds
+ ah->ah_setupTxDesc(ds
, adf_nbuf_len(skb) + IEEE80211_CRC_LEN
, sizeof(struct ieee80211_frame)
, HAL_PKT_TYPE_BEACON
, MAX_RATE_POWER
, rate, 1
, HAL_TXKEYIX_INVALID
- , 0
, flags
, 0
- , 0
- , 0
- , 0
- , ATH_COMP_PROC_NO_COMP_NO_CCS);
+ , 0);
- ath_hal_filltxdesc(ah, ds
+ ah->ah_fillTxDesc(ds
, asf_roundup(adf_nbuf_len(skb), 4)
, AH_TRUE
, AH_TRUE
series[0].Rate = rate;
series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
series[0].RateFlags = 0;
- ath_hal_set11n_ratescenario(ah, ds, 0, 0, 0, series, 4, 0);
+ ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0);
}
static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info);
ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]);
- ath_hal_stoptxdma(ah, sc->sc_bhalq);
- ath_hal_puttxbuf(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
- ath_hal_txstart(ah, sc->sc_bhalq);
+ ah->ah_stopTxDma(ah, sc->sc_bhalq);
+ ah->ah_setTxDP(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
+ ah->ah_startTxDma(ah, sc->sc_bhalq);
}
/******/
{
struct ath_hal *ah = sc->sc_ah;
- (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
+ ah->ah_stopTxDma(ah, txq->axq_qnum);
}
static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq)
ath_tx_status_clear(sc);
sc->sc_tx_draining = 1;
- (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
+ ah->ah_stopTxDma(ah, sc->sc_bhalq);
for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
if (ATH_TXQ_SETUP(sc, i))
a_uint32_t tmp;
#ifdef ATH_ENABLE_CABQ
- tsf = ath_hal_gettsf64(ah);
+ tsf = ah->ah_getTsf64(ah);
tmp = tsf - sc->sc_swba_tsf;
if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
if (sc->sc_invalid)
return ADF_OS_IRQ_NONE;
- if (!ath_hal_intrpend(ah))
+ if (!ah->ah_isInterruptPending(ah))
return ADF_OS_IRQ_NONE;
- ath_hal_getisr(ah, &status);
+ ah->ah_getPendingInterrupts(ah, &status);
status &= sc->sc_imask;
if (status & HAL_INT_FATAL) {
- ath_hal_intrset(ah, 0);
+ ah->ah_setInterrupts(ah, 0);
ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
} else {
if (status & HAL_INT_SWBA) {
WMI_SWBA_EVENT swbaEvt;
struct ath_txq *txq = ATH_TXQ(sc, 8);
- swbaEvt.tsf = ath_hal_gettsf64(ah);
- swbaEvt.beaconPendingCount = ath_hal_numtxpending(ah, sc->sc_bhalq);
- sc->sc_swba_tsf = ath_hal_gettsf64(ah);
+ swbaEvt.tsf = ah->ah_getTsf64(ah);
+ swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq);
+ sc->sc_swba_tsf = ah->ah_getTsf64(ah);
wmi_event(sc->tgt_wmi_handle,
WMI_SWBA_EVENTID,
ath_uapsd_processtriggers(sc);
sc->sc_imask &= ~HAL_INT_RX;
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
}
if (status & HAL_INT_TXURN) {
sc->sc_int_stats.ast_txurn++;
- ath_hal_updatetxtriglevel(ah, AH_TRUE);
+ ah->ah_updateTxTrigLevel(ah, AH_TRUE);
}
ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq);
sc->sc_imask |= HAL_INT_BMISS;
}
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
}
sc->sc_imask |= HAL_INT_GTT;
- if (ath_hal_htsupported(ah))
+ if (ath_hal_getcapability(ah, HAL_CAP_HT))
sc->sc_imask |= HAL_INT_CST;
adf_os_setup_intr(sc->sc_dev, ath_intr);
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
struct ath_hal *ah = sc->sc_ah;
- ath_hal_intrset(ah, 0);
+ ah->ah_setInterrupts(ah, 0);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
}
A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
{
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
+ struct ath_hal *ah = sc->sc_ah;
- ath_hal_aborttxdma(sc->sc_ah);
+ ah->ah_abortTxDma(sc->sc_ah);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
q = *(a_uint32_t *)data;
q = adf_os_ntohl(q);
- ath_hal_stoptxdma(ah, q);
+ ah->ah_stopTxDma(ah, q);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
struct ath_hal *ah = sc->sc_ah;
- ath_hal_stoppcurecv(ah);
- ath_hal_setrxfilter(ah, 0);
- ath_hal_stopdmarecv(ah);
+ ah->ah_stopPcuReceive(ah);
+ ah->ah_setRxFilter(ah, 0);
+ ah->ah_stopDmaReceive(ah);
sc->sc_rxlink = NULL;
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
struct ath_hal *ah = sc->sc_ah;
ath_desc_free(sc);
- ath_hal_detach(ah);
+ ah->ah_detach(ah);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
adf_os_mem_free(sc);
}
ath_tgt_txq_setup(sc);
sc->sc_imask =0;
- ath_hal_intrset(ah,0);
+ ah->ah_setInterrupts(ah, 0);
return 0;
bad:
bad2:
ath_desc_free(sc);
if (ah)
- ath_hal_detach(ah);
+ ah->ah_detach(ah);
}
static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)
#include <adf_net.h>
#include <adf_os_irq.h>
-#include <adf_net_types.h>
#include <adf_net_wcmd.h>
#include <ieee80211_var.h>
* Attach/detach a rate control module.
*/
struct ath_ratectrl *ath_rate_attach(struct ath_softc_tgt *);
-void ath_rate_detach(struct ath_ratectrl *);
/*
* Return the transmit info for a data packet. If multi-rate state
a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp);
-#define ath_hal_getratetable(_ah, _mode) \
- ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
-#define ath_hal_intrset(_ah, _mask) \
- ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
-#define ath_hal_intrpend(_ah) \
- ((*(_ah)->ah_isInterruptPending)((_ah)))
-#define ath_hal_getisr(_ah, _pmask) \
- ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
-#define ath_hal_updatetxtriglevel(_ah, _inc) \
- ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
-#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
- ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
-#define ath_hal_rxprocdescfast(_ah, _ds, _dspa, _dsnext, _rx_stats) \
- ((*(_ah)->ah_procRxDescFast)((_ah), (_ds), (_dspa), (_dsnext), (_rx_stats)))
-#define ath_hal_stoptxdma(_ah, _qnum) \
- ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
-#define ath_hal_aborttxdma(_ah) \
- ((*(_ah)->ah_abortTxDma)(_ah))
-#define ath_hal_set11n_txdesc(_ah, _ds, _pktlen, _type, _txpower,\
- _keyix, _keytype, _flags) \
- ((*(_ah)->ah_set11nTxDesc)(_ah, _ds, _pktlen, _type, _txpower, _keyix,\
- _keytype, _flags))
-#define ath_hal_set11n_ratescenario(_ah, _ds, _durupdate, _rtsctsrate, _rtsctsduration, \
- _series, _nseries, _flags) \
- ((*(_ah)->ah_set11nRateScenario)(_ah, _ds, _durupdate, _rtsctsrate, _rtsctsduration,\
- _series, _nseries, _flags))
-#define ath_hal_clr11n_aggr(_ah, _ds) \
- ((*(_ah)->ah_clr11nAggr)(_ah, _ds))
-#define ath_hal_set11n_burstduration(_ah, _ds, _burstduration) \
- ((*(_ah)->ah_set11nBurstDuration)(_ah, _ds, _burstduration))
-#define ath_hal_set11n_virtualmorefrag(_ah, _ds, _vmf) \
- ((*(_ah)->ah_set11nVirtualMoreFrag)(_ah, _ds, _vmf))
-#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
- _txr0, _txtr0, _keyix, _ant, _flags, \
- _rtsrate, _rtsdura, \
- _compicvlen, _compivlen, _comp) \
- ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
- (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
- (_flags), (_rtsrate), (_rtsdura), \
- (_compicvlen), (_compivlen), (_comp)))
-#define ath_hal_fillkeytxdesc(_ah, _ds, _keytype) \
- ((*(_ah)->ah_fillKeyTxDesc)((_ah), (_ds), (_keytype)))
-#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
- ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
-#define ath_hal_txprocdesc(_ah, _ds) \
- ((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
-#define ath_hal_putrxbuf(_ah, _bufaddr) \
- ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
-#define ath_hal_rxena(_ah) \
- ((*(_ah)->ah_enableReceive)((_ah)))
-#define ath_hal_stopdmarecv(_ah) \
- ((*(_ah)->ah_stopDmaReceive)((_ah)))
-#define ath_hal_stoppcurecv(_ah) \
- ((*(_ah)->ah_stopPcuReceive)((_ah)))
-#define ath_hal_htsupported(_ah) \
- (ath_hal_getcapability(_ah, HAL_CAP_HT, 0, NULL) == HAL_OK)
-#define ath_hal_getrtsaggrlimit(_ah, _pv) \
- (ath_hal_getcapability(_ah, HAL_CAP_RTS_AGGR_LIMIT, 0, _pv) == HAL_OK)
-#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
- ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
- #define ath_hal_txstart(_ah, _q) \
- ((*(_ah)->ah_startTxDma)((_ah), (_q)))
-#define ath_hal_setrxfilter(_ah, _filter) \
- ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
-#define ath_hal_gettsf64(_ah) \
- ((*(_ah)->ah_getTsf64)((_ah)))
-#define ath_hal_intrset(_ah, _mask) \
- ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
-#define ath_hal_getcapability(_ah, _cap, _param, _result) \
- ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
-#define ath_hal_set11n_aggr_first(_ah, _ds, _aggrlen, _numdelims) \
- ((*(_ah)->ah_set11nAggrFirst)(_ah, _ds, _aggrlen, _numdelims))
-#define ath_hal_set11n_aggr_middle(_ah, _ds, _numdelims) \
- ((*(_ah)->ah_set11nAggrMiddle)(_ah, _ds, _numdelims))
-#define ath_hal_set11n_aggr_last(_ah, _ds) \
- ((*(_ah)->ah_set11nAggrLast)(_ah, _ds))
-#define ath_hal_numtxpending(_ah, _q) \
- ((*(_ah)->ah_numTxPending)((_ah), (_q)))
-
#endif /* _DEV_ATH_ATHVAR_H */
+++ /dev/null
-/*-
- * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer,
- * without modification.
- * 2. Redistributions in binary form must reproduce at minimum a disclaimer
- * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
- * redistribution must be conditioned upon including a substantially
- * similar Disclaimer requirement for further binary redistribution.
- * 3. Neither the names of the above-listed copyright holders nor the names
- * of any contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
- * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
- * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGES.
- *
- * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/madwifi/net80211/if_ethersubr.h#1 $
- */
-
-#ifndef _NET_IF_ETHERSUBR_H_
-#define _NET_IF_ETHERSUBR_H_
-
-#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */
-#define ETHER_TYPE_LEN 2 /* length of the Ethernet type field */
-#define ETHER_CRC_LEN 4 /* length of the Ethernet CRC */
-#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
-#define ETHER_MAX_LEN 1518
-
-#define ETHERMTU (ETHER_MAX_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
-
-/*
- * Structure of a 10Mb/s Ethernet header.
- */
-/* struct ether_header { */
-/* u_char ether_dhost[ETHER_ADDR_LEN]; */
-/* u_char ether_shost[ETHER_ADDR_LEN]; */
-/* u_short ether_type; */
-/* } adf_os_packed; */
-
-#ifndef ETHERTYPE_PAE
-#define ETHERTYPE_PAE 0x888e /* EAPOL PAE/802.1x */
-#endif
-#ifndef ETHERTYPE_IP
-#define ETHERTYPE_IP 0x0800 /* IP protocol */
-#endif
-
-/*
- * Structure of a 48-bit Ethernet address.
- */
-/* struct ether_addr { */
-/* u_char octet[ETHER_ADDR_LEN]; */
-/* } adf_os_packed; */
-
-#define ETHER_IS_MULTICAST(addr) (*(addr) & 0x01) /* is address mcast/bcast? */
-
-#define VLAN_PRI_SHIFT 13 /* Shift to find VLAN user priority */
-#define VLAN_PRI_MASK 7 /* Mask for user priority bits in VLAN */
-
-
-#endif /* _NET_IF_ETHERSUBR_H_ */
#include <adf_net.h>
#include <adf_net_wcmd.h>
-#include "if_ethersubr.h"
#include "if_llc.h"
#ifdef USE_HEADERLEN_RESV
#include "if_athrate.h"
#include "if_athvar.h"
#include "ah_desc.h"
-#include "if_ath_pci.h"
#define ath_tgt_free_skb adf_nbuf_free
static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
struct ath_tx_desc *ds0, *ds = bf->bf_desc;
+ struct ath_hal *ah = sc->sc_ah;
a_uint8_t i;
ds0 = ds;
} else
ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
- ath_hal_filltxdesc(sc->sc_ah, ds
+ ah->ah_fillTxDesc(ds
, bf->bf_dmamap_info.dma_segs[i].len
, i == 0
, i == (bf->bf_dmamap_info.nsegs - 1)
static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
struct ath_tx_desc *ds = bf->bf_desc;
+ struct ath_hal *ah = sc->sc_ah;
switch (bf->bf_protmode) {
case IEEE80211_PROT_RTSCTS:
break;
}
- ath_hal_set11n_txdesc(sc->sc_ah, ds
+ ah->ah_set11nTxDesc(ds
, bf->bf_pktlen
, bf->bf_atype
, 60
HAL_11N_RATE_SERIES series[4];
a_int32_t i, flags;
a_uint8_t rix, cix, rtsctsrate;
- a_uint32_t ctsduration = 0;
a_int32_t prot_mode = AH_FALSE;
rt = sc->sc_currates;
cix = rt->info[sc->sc_protrix].controlRate;
prot_mode = AH_TRUE;
} else {
- if (ath_hal_htsupported(ah) && (!bf->bf_ismcast))
+ if (ath_hal_getcapability(ah, HAL_CAP_HT) && (!bf->bf_ismcast))
flags = HAL_TXDESC_RTSENA;
for (i = 4; i--;) {
rtsctsrate = rt->info[cix].rateCode |
(bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
- ath_hal_set11n_ratescenario(ah, ds, 1,
- rtsctsrate, ctsduration,
+ ah->ah_set11nRateScenario(ds, 1,
+ rtsctsrate,
series, 4,
flags);
}
static void owltgt_tx_process_cabq(struct ath_softc_tgt *sc, struct ath_txq *txq)
{
- ath_hal_intrset(sc->sc_ah, sc->sc_imask & ~HAL_INT_SWBA);
+ struct ath_hal *ah = sc->sc_ah;
+ ah->ah_setInterrupts(ah, sc->sc_imask & ~HAL_INT_SWBA);
owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
- ath_hal_intrset(sc->sc_ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
}
void owl_tgt_tx_tasklet(TQUEUE_ARG data)
{
struct ath_tx_buf *bf;
struct ath_tx_desc *ds;
+ struct ath_hal *ah = sc->sc_ah;
HAL_STATUS status;
for (;;) {
bf = asf_tailq_first(&txq->axq_q);
ds = bf->bf_lastds;
- status = ath_hal_txprocdesc(sc->sc_ah, ds);
+ status = ah->ah_procTxDesc(ah, ds);
if (status == HAL_EINPROGRESS) {
if (txqstate == OWL_TXQ_ACTIVE)
txq = bf->bf_txq;
- status = ath_hal_txprocdesc(sc->sc_ah, bf->bf_lastds);
+ status = ah->ah_procTxDesc(ah, bf->bf_lastds);
ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
if (txq->axq_link == NULL) {
- ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
+ ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
} else {
*txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
txe_val = OS_REG_READ(ah, 0x840);
if (!(txe_val & (1<< txq->axq_qnum)))
- ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
+ ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
}
txq->axq_link = &bf->bf_lastds->ds_link;
- ath_hal_txstart(ah, txq->axq_qnum);
+ ah->ah_startTxDma(ah, txq->axq_qnum);
}
static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
{
a_int32_t i ;
struct ath_tx_desc *bfd = NULL;
+ struct ath_hal *ah = sc->sc_ah;
for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
- ath_hal_clr11n_aggr(sc->sc_ah, bfd);
- ath_hal_set11n_burstduration(sc->sc_ah, bfd, 0);
- ath_hal_set11n_virtualmorefrag(sc->sc_ah, bfd, 0);
+ ah->ah_clr11nAggr(bfd);
+ ah->ah_set11nBurstDuration(bfd, 0);
+ ah->ah_set11nVirtualMoreFrag(bfd, 0);
}
ath_dma_unmap(sc, bf);
struct ath_vap_target *avp;
struct ath_hal *ah = sc->sc_ah;
a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
- a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration;
+ a_uint32_t subtype, flags, ctsduration;
a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
struct ath_tx_desc *ds=NULL;
struct ath_txq *txq=NULL;
flags |= HAL_TXDESC_INTREQ;
- ath_hal_setuptxdesc(ah, ds
+ ah->ah_setupTxDesc(ds
, pktlen
, hdrlen
, atype
, 60
, txrate, try0
, keyix
- , 0
, flags
, ctsrate
- , ctsduration
- , icvlen
- , ivlen
- , ATH_COMP_PROC_NO_COMP_NO_CCS);
+ , ctsduration);
bf->bf_flags = flags;
* in Auth frame 3 of Shared Authentication, owl needs this.
*/
if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
- (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
- ath_hal_fillkeytxdesc(ah, ds, mh->keytype);
+ (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
+ ah->ah_fillKeyTxDesc(ds, mh->keytype);
ath_filltxdesc(sc, bf);
series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
series[i].RateFlags = 0;
}
- ath_hal_set11n_ratescenario(ah, ds, 0, ctsrate, ctsduration, series, 4, 0);
+ ah->ah_set11nRateScenario(ds, 0, ctsrate, series, 4, 0);
ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
return;
ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
if (txq->axq_link == NULL) {
- ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
+ ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
} else {
*txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
}
txq->axq_link = &lastds->ds_link;
- ath_hal_txstart(ah, txq->axq_qnum);
+ ah->ah_startTxDma(ah, txq->axq_qnum);
}
void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
ath_tx_bufhead bf_q;
struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno);
struct ath_tx_desc *ds = NULL;
+ struct ath_hal *ah = sc->sc_ah;
int i;
bf->bf_next = NULL;
for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
- ath_hal_clr11n_aggr(sc->sc_ah, ds);
+ ah->ah_clr11nAggr(ds);
ath_buf_set_rate(sc, bf);
bf->bf_txq_add(sc, bf);
bf->bf_isaggr = 1;
ath_buf_set_rate(sc, bf);
- ath_hal_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al,
+ ah->ah_set11nAggrFirst(bf->bf_desc, bf->bf_al,
bf->bf_ndelim);
bf->bf_lastds = bf_last->bf_lastds;
for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
- ath_hal_set11n_aggr_last(sc->sc_ah, &bf_last->bf_descarr[i]);
+ ah->ah_set11nAggrLast(&bf_last->bf_descarr[i]);
if (status == ATH_AGGR_8K_LIMITED) {
adf_os_assert(0);
int nframes = 0, rl = 0;;
struct ath_tx_desc *ds = NULL;
struct ath_tx_buf *bf;
+ struct ath_hal *ah = sc->sc_ah;
u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta;
u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
bf_prev = bf;
for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
- ath_hal_set11n_aggr_middle(sc->sc_ah, ds, bf->bf_ndelim);
+ ah->ah_set11nAggrMiddle(ds, bf->bf_ndelim);
} while (!asf_tailq_empty(&tid->buf_q));
struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
struct ath_tx_desc *ds = NULL;
+ struct ath_hal *ah = sc->sc_ah;
int i = 0;
__stats(sc, txaggr_compretries);
for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
- ath_hal_clr11n_aggr(sc->sc_ah, ds);
- ath_hal_set11n_burstduration(sc->sc_ah, ds, 0);
- ath_hal_set11n_virtualmorefrag(sc->sc_ah, ds, 0);
+ ah->ah_clr11nAggr(ds);
+ ah->ah_set11nBurstDuration(ds, 0);
+ ah->ah_set11nVirtualMoreFrag(ds, 0);
}
if (bf->bf_retries >= OWLMAX_RETRIES) {
struct ieee80211_frame_bar *bar;
u_int8_t min_rate;
struct ath_tx_desc *ds, *ds0;
+ struct ath_hal *ah = sc->sc_ah;
HAL_11N_RATE_SERIES series[4];
int i = 0;
adf_nbuf_queue_t skbhead;
adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
ds = bf->bf_desc;
- ath_hal_setuptxdesc(sc->sc_ah, ds
+ ah->ah_setupTxDesc(ds
, adf_nbuf_len(skb) + IEEE80211_CRC_LEN
, 0
, HAL_PKT_TYPE_NORMAL
, min_rate
, ATH_TXMAXTRY
, bf->bf_keyix
- , 0
, HAL_TXDESC_INTREQ
| HAL_TXDESC_CLRDMASK
- , 0, 0, 0, 0
- , ATH_COMP_PROC_NO_COMP_NO_CCS);
+ , 0, 0);
skbhead = bf->bf_skbhead;
bf->bf_isaggr = 0;
bf->bf_next = NULL;
for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
- ath_hal_clr11n_aggr(sc->sc_ah, ds0);
+ ah->ah_clr11nAggr(ds0);
}
ath_filltxdesc(sc, bf);
series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
}
- ath_hal_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 0, 0, 0, series, 4, 4);
+ ah->ah_set11nRateScenario(bf->bf_desc, 0, 0, series, 4, 4);
ath_tgt_txq_add_ucast(sc, bf);
}
+++ /dev/null
-/*
- * Copyright (c) 1991, 1993
- * The Regents of the University of California. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @(#)queue.h 8.5 (Berkeley) 8/20/94
- * $FreeBSD: src/sys/sys/queue.h,v 1.58 2004/04/07 04:19:49 imp Exp $
- * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/madwifi/include/sys/queue.h#1 $
- */
-
-#ifndef _SYS_QUEUE_H_
-#define _SYS_QUEUE_H_
-
-/*
- * This file defines four types of data structures: singly-linked lists,
- * singly-linked tail queues, lists and tail queues.
- *
- * A singly-linked list is headed by a single forward pointer. The elements
- * are singly linked for minimum space and pointer manipulation overhead at
- * the expense of O(n) removal for arbitrary elements. New elements can be
- * added to the list after an existing element or at the head of the list.
- * Elements being removed from the head of the list should use the explicit
- * macro for this purpose for optimum efficiency. A singly-linked list may
- * only be traversed in the forward direction. Singly-linked lists are ideal
- * for applications with large datasets and few or no removals or for
- * implementing a LIFO queue.
- *
- * A singly-linked tail queue is headed by a pair of pointers, one to the
- * head of the list and the other to the tail of the list. The elements are
- * singly linked for minimum space and pointer manipulation overhead at the
- * expense of O(n) removal for arbitrary elements. New elements can be added
- * to the list after an existing element, at the head of the list, or at the
- * end of the list. Elements being removed from the head of the tail queue
- * should use the explicit macro for this purpose for optimum efficiency.
- * A singly-linked tail queue may only be traversed in the forward direction.
- * Singly-linked tail queues are ideal for applications with large datasets
- * and few or no removals or for implementing a FIFO queue.
- *
- * A list is headed by a single forward pointer (or an array of forward
- * pointers for a hash table header). The elements are doubly linked
- * so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before
- * or after an existing element or at the head of the list. A list
- * may only be traversed in the forward direction.
- *
- * A tail queue is headed by a pair of pointers, one to the head of the
- * list and the other to the tail of the list. The elements are doubly
- * linked so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before or
- * after an existing element, at the head of the list, or at the end of
- * the list. A tail queue may be traversed in either direction.
- *
- * For details on the use of these macros, see the queue(3) manual page.
- *
- *
- * SLIST LIST STAILQ TAILQ
- * _HEAD + + + +
- * _HEAD_INITIALIZER + + + +
- * _ENTRY + + + +
- * _INIT + + + +
- * _EMPTY + + + +
- * _FIRST + + + +
- * _NEXT + + + +
- * _PREV - - - +
- * _LAST - - + +
- * _FOREACH + + + +
- * _FOREACH_SAFE + + + +
- * _FOREACH_REVERSE - - - +
- * _FOREACH_REVERSE_SAFE - - - +
- * _INSERT_HEAD + + + +
- * _INSERT_BEFORE - + - +
- * _INSERT_AFTER + + + +
- * _INSERT_TAIL - - + +
- * _CONCAT - - + +
- * _REMOVE_HEAD + - + -
- * _REMOVE + + + +
- *
- */
-#define QUEUE_MACRO_DEBUG 0
-#if QUEUE_MACRO_DEBUG
-/* Store the last 2 places the queue element or head was altered */
-struct qm_trace {
- char * lastfile;
- a_int32_t lastline;
- char * prevfile;
- a_int32_t prevline;
-};
-
-#define TRACEBUF struct qm_trace trace;
-#define TRASHIT(x) do {(x) = (void *)-1;} while (0)
-
-#define QMD_TRACE_HEAD(head) do { \
- (head)->trace.prevline = (head)->trace.lastline; \
- (head)->trace.prevfile = (head)->trace.lastfile; \
- (head)->trace.lastline = __LINE__; \
- (head)->trace.lastfile = __FILE__; \
-} while (0)
-
-#define QMD_TRACE_ELEM(elem) do { \
- (elem)->trace.prevline = (elem)->trace.lastline; \
- (elem)->trace.prevfile = (elem)->trace.lastfile; \
- (elem)->trace.lastline = __LINE__; \
- (elem)->trace.lastfile = __FILE__; \
-} while (0)
-
-#else
-#define QMD_TRACE_ELEM(elem)
-#define QMD_TRACE_HEAD(head)
-#define TRACEBUF
-#define TRASHIT(x)
-#endif /* QUEUE_MACRO_DEBUG */
-
-/*
- * Singly-linked List declarations.
- */
-#define SLIST_HEAD(name, type) \
-struct name { \
- struct type *slh_first; /* first element */ \
-}
-
-#define SLIST_HEAD_INITIALIZER(head) \
- { NULL }
-
-#define SLIST_ENTRY(type) \
-struct { \
- struct type *sle_next; /* next element */ \
-}
-
-/*
- * Singly-linked List functions.
- */
-#define SLIST_EMPTY(head) ((head)->slh_first == NULL)
-
-#define SLIST_FIRST(head) ((head)->slh_first)
-
-#define SLIST_FOREACH(var, head, field) \
- for ((var) = SLIST_FIRST((head)); \
- (var); \
- (var) = SLIST_NEXT((var), field))
-
-#define SLIST_FOREACH_SAFE(var, head, field, tvar) \
- for ((var) = SLIST_FIRST((head)); \
- (var) && ((tvar) = SLIST_NEXT((var), field), 1); \
- (var) = (tvar))
-
-#define SLIST_FOREACH_PREVPTR(var, varp, head, field) \
- for ((varp) = &SLIST_FIRST((head)); \
- ((var) = *(varp)) != NULL; \
- (varp) = &SLIST_NEXT((var), field))
-
-#define SLIST_INIT(head) do { \
- SLIST_FIRST((head)) = NULL; \
-} while (0)
-
-#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \
- SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \
- SLIST_NEXT((slistelm), field) = (elm); \
-} while (0)
-
-#define SLIST_INSERT_HEAD(head, elm, field) do { \
- SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \
- SLIST_FIRST((head)) = (elm); \
-} while (0)
-
-#define SLIST_NEXT(elm, field) ((elm)->field.sle_next)
-
-#define SLIST_REMOVE(head, elm, type, field) do { \
- if (SLIST_FIRST((head)) == (elm)) { \
- SLIST_REMOVE_HEAD((head), field); \
- } \
- else { \
- struct type *curelm = SLIST_FIRST((head)); \
- while (SLIST_NEXT(curelm, field) != (elm)) \
- curelm = SLIST_NEXT(curelm, field); \
- SLIST_NEXT(curelm, field) = \
- SLIST_NEXT(SLIST_NEXT(curelm, field), field); \
- } \
-} while (0)
-
-#define SLIST_REMOVE_HEAD(head, field) do { \
- SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \
-} while (0)
-
-/*
- * Singly-linked Tail queue declarations.
- */
-#define STAILQ_HEAD(name, type) \
-struct name { \
- struct type *stqh_first;/* first element */ \
- struct type **stqh_last;/* addr of last next element */ \
-}
-
-#define STAILQ_HEAD_INITIALIZER(head) \
- { NULL, &(head).stqh_first }
-
-#define STAILQ_ENTRY(type) \
-struct { \
- struct type *stqe_next; /* next element */ \
-}
-
-/*
- * Singly-linked Tail queue functions.
- */
-#define STAILQ_CONCAT(head1, head2) do { \
- if (!STAILQ_EMPTY((head2))) { \
- *(head1)->stqh_last = (head2)->stqh_first; \
- (head1)->stqh_last = (head2)->stqh_last; \
- STAILQ_INIT((head2)); \
- } \
-} while (0)
-
-#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL)
-
-#define STAILQ_FIRST(head) ((head)->stqh_first)
-
-#define STAILQ_FOREACH(var, head, field) \
- for((var) = STAILQ_FIRST((head)); \
- (var); \
- (var) = STAILQ_NEXT((var), field))
-
-
-#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \
- for ((var) = STAILQ_FIRST((head)); \
- (var) && ((tvar) = STAILQ_NEXT((var), field), 1); \
- (var) = (tvar))
-
-#define STAILQ_INIT(head) do { \
- STAILQ_FIRST((head)) = NULL; \
- (head)->stqh_last = &STAILQ_FIRST((head)); \
-} while (0)
-
-#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \
- if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
- (head)->stqh_last = &STAILQ_NEXT((elm), field); \
- STAILQ_NEXT((tqelm), field) = (elm); \
-} while (0)
-
-#define STAILQ_INSERT_HEAD(head, elm, field) do { \
- if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \
- (head)->stqh_last = &STAILQ_NEXT((elm), field); \
- STAILQ_FIRST((head)) = (elm); \
-} while (0)
-
-#define STAILQ_INSERT_TAIL(head, elm, field) do { \
- STAILQ_NEXT((elm), field) = NULL; \
- *(head)->stqh_last = (elm); \
- (head)->stqh_last = &STAILQ_NEXT((elm), field); \
-} while (0)
-
-#define STAILQ_LAST(head, type, field) \
- (STAILQ_EMPTY((head)) ? \
- NULL : \
- ((struct type *) \
- ((char *)((head)->stqh_last) - asf_offsetof(struct type, field))))
-
-#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next)
-
-#define STAILQ_REMOVE(head, elm, type, field) do { \
- if (STAILQ_FIRST((head)) == (elm)) { \
- STAILQ_REMOVE_HEAD((head), field); \
- } \
- else { \
- struct type *curelm = STAILQ_FIRST((head)); \
- while (STAILQ_NEXT(curelm, field) != (elm)) \
- curelm = STAILQ_NEXT(curelm, field); \
- if ((STAILQ_NEXT(curelm, field) = \
- STAILQ_NEXT(STAILQ_NEXT(curelm, field), field)) == NULL)\
- (head)->stqh_last = &STAILQ_NEXT((curelm), field);\
- } \
-} while (0)
-
-
-#define STAILQ_REMOVE_AFTER(head, elm, field) do { \
- if (STAILQ_NEXT(elm, field)) { \
- if ((STAILQ_NEXT(elm, field) = \
- STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL)\
- (head)->stqh_last = &STAILQ_NEXT((elm), field); \
- } \
-} while (0)
-
-
-#define STAILQ_REMOVE_HEAD(head, field) do { \
- if ((STAILQ_FIRST((head)) = \
- STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \
- (head)->stqh_last = &STAILQ_FIRST((head)); \
-} while (0)
-
-#define STAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do { \
- if ((STAILQ_FIRST((head)) = STAILQ_NEXT((elm), field)) == NULL) \
- (head)->stqh_last = &STAILQ_FIRST((head)); \
-} while (0)
-
-/*
- * List declarations.
- */
-#define LIST_HEAD(name, type) \
-struct name { \
- struct type *lh_first; /* first element */ \
-}
-
-#define ATH_LIST_HEAD(name, type) \
-struct name { \
- struct type *lh_first; /* first element */ \
-}
-
-#define LIST_HEAD_INITIALIZER(head) \
- { NULL }
-
-#define LIST_ENTRY(type) \
-struct { \
- struct type *le_next; /* next element */ \
- struct type **le_prev; /* address of previous next element */ \
-}
-
-/*
- * List functions.
- */
-
-#define LIST_EMPTY(head) ((head)->lh_first == NULL)
-
-#define LIST_FIRST(head) ((head)->lh_first)
-
-#define LIST_FOREACH(var, head, field) \
- for ((var) = LIST_FIRST((head)); \
- (var); \
- (var) = LIST_NEXT((var), field))
-
-#define LIST_FOREACH_SAFE(var, head, field, tvar) \
- for ((var) = LIST_FIRST((head)); \
- (var) && ((tvar) = LIST_NEXT((var), field), 1); \
- (var) = (tvar))
-
-#define LIST_INIT(head) do { \
- LIST_FIRST((head)) = NULL; \
-} while (0)
-
-#define LIST_INSERT_AFTER(listelm, elm, field) do { \
- if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
- LIST_NEXT((listelm), field)->field.le_prev = \
- &LIST_NEXT((elm), field); \
- LIST_NEXT((listelm), field) = (elm); \
- (elm)->field.le_prev = &LIST_NEXT((listelm), field); \
-} while (0)
-
-#define LIST_INSERT_BEFORE(listelm, elm, field) do { \
- (elm)->field.le_prev = (listelm)->field.le_prev; \
- LIST_NEXT((elm), field) = (listelm); \
- *(listelm)->field.le_prev = (elm); \
- (listelm)->field.le_prev = &LIST_NEXT((elm), field); \
-} while (0)
-
-#define LIST_INSERT_HEAD(head, elm, field) do { \
- if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \
- LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
- LIST_FIRST((head)) = (elm); \
- (elm)->field.le_prev = &LIST_FIRST((head)); \
-} while (0)
-
-#define LIST_NEXT(elm, field) ((elm)->field.le_next)
-
-#define LIST_REMOVE(elm, field) do { \
- if (LIST_NEXT((elm), field) != NULL) \
- LIST_NEXT((elm), field)->field.le_prev = \
- (elm)->field.le_prev; \
- *(elm)->field.le_prev = LIST_NEXT((elm), field); \
-} while (0)
-
-/*
- * Tail queue declarations.
- */
-#define TAILQ_HEAD(name, type) \
-struct name { \
- struct type *tqh_first; /* first element */ \
- struct type **tqh_last; /* addr of last next element */ \
- TRACEBUF \
-}
-
-#define TAILQ_HEAD_INITIALIZER(head) \
- { NULL, &(head).tqh_first }
-
-#define TAILQ_ENTRY(type) \
-struct { \
- struct type *tqe_next; /* next element */ \
- struct type **tqe_prev; /* address of previous next element */ \
- TRACEBUF \
-}
-
-/*
- * Tail queue functions.
- */
-#define TAILQ_CONCAT(head1, head2, field) do { \
- if (!TAILQ_EMPTY(head2)) { \
- *(head1)->tqh_last = (head2)->tqh_first; \
- (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \
- (head1)->tqh_last = (head2)->tqh_last; \
- TAILQ_INIT((head2)); \
- QMD_TRACE_HEAD(head); \
- QMD_TRACE_HEAD(head2); \
- } \
-} while (0)
-
-#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
-
-#define TAILQ_FIRST(head) ((head)->tqh_first)
-
-#define TAILQ_FOREACH(var, head, field) \
- for ((var) = TAILQ_FIRST((head)); \
- (var); \
- (var) = TAILQ_NEXT((var), field))
-
-#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \
- for ((var) = TAILQ_FIRST((head)); \
- (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \
- (var) = (tvar))
-
-#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \
- for ((var) = TAILQ_LAST((head), headname); \
- (var); \
- (var) = TAILQ_PREV((var), headname, field))
-
-#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \
- for ((var) = TAILQ_LAST((head), headname); \
- (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \
- (var) = (tvar))
-
-#define TAILQ_INIT(head) do { \
- TAILQ_FIRST((head)) = NULL; \
- (head)->tqh_last = &TAILQ_FIRST((head)); \
- QMD_TRACE_HEAD(head); \
-} while (0)
-
-#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
- if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
- TAILQ_NEXT((elm), field)->field.tqe_prev = \
- &TAILQ_NEXT((elm), field); \
- else { \
- (head)->tqh_last = &TAILQ_NEXT((elm), field); \
- QMD_TRACE_HEAD(head); \
- } \
- TAILQ_NEXT((listelm), field) = (elm); \
- (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \
- QMD_TRACE_ELEM(&(elm)->field); \
- QMD_TRACE_ELEM(&listelm->field); \
-} while (0)
-
-#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
- (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
- TAILQ_NEXT((elm), field) = (listelm); \
- *(listelm)->field.tqe_prev = (elm); \
- (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \
- QMD_TRACE_ELEM(&(elm)->field); \
- QMD_TRACE_ELEM(&listelm->field); \
-} while (0)
-
-#define TAILQ_INSERT_HEAD(head, elm, field) do { \
- if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \
- TAILQ_FIRST((head))->field.tqe_prev = \
- &TAILQ_NEXT((elm), field); \
- else \
- (head)->tqh_last = &TAILQ_NEXT((elm), field); \
- TAILQ_FIRST((head)) = (elm); \
- (elm)->field.tqe_prev = &TAILQ_FIRST((head)); \
- QMD_TRACE_HEAD(head); \
- QMD_TRACE_ELEM(&(elm)->field); \
-} while (0)
-
-#define TAILQ_INSERT_TAIL(head, elm, field) do { \
- TAILQ_NEXT((elm), field) = NULL; \
- (elm)->field.tqe_prev = (head)->tqh_last; \
- *(head)->tqh_last = (elm); \
- (head)->tqh_last = &TAILQ_NEXT((elm), field); \
- QMD_TRACE_HEAD(head); \
- QMD_TRACE_ELEM(&(elm)->field); \
-} while (0)
-
-#define TAILQ_LAST(head, headname) \
- (*(((struct headname *)((head)->tqh_last))->tqh_last))
-
-#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
-
-#define TAILQ_PREV(elm, headname, field) \
- (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
-
-#define TAILQ_REMOVE(head, elm, field) do { \
- if ((TAILQ_NEXT((elm), field)) != NULL) \
- TAILQ_NEXT((elm), field)->field.tqe_prev = \
- (elm)->field.tqe_prev; \
- else { \
- (head)->tqh_last = (elm)->field.tqe_prev; \
- QMD_TRACE_HEAD(head); \
- } \
- *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \
- TRASHIT((elm)->field.tqe_next); \
- TRASHIT((elm)->field.tqe_prev); \
- QMD_TRACE_ELEM(&(elm)->field); \
-} while (0)
-
-
-#ifdef _KERNEL
-
-/*
- * XXX insque() and remque() are an old way of handling certain queues.
- * They bogusly assumes that all queue heads look alike.
- */
-
-struct quehead {
- struct quehead *qh_link;
- struct quehead *qh_rlink;
-};
-
-#if defined(__GNUC__) || defined(__INTEL_COMPILER)
-
-static __inline void
-insque(void *a, void *b)
-{
- struct quehead *element = (struct quehead *)a,
- *head = (struct quehead *)b;
-
- element->qh_link = head->qh_link;
- element->qh_rlink = head;
- head->qh_link = element;
- element->qh_link->qh_rlink = element;
-}
-
-static __inline void
-remque(void *a)
-{
- struct quehead *element = (struct quehead *)a;
-
- element->qh_link->qh_rlink = element->qh_rlink;
- element->qh_rlink->qh_link = element->qh_link;
- element->qh_rlink = 0;
-}
-
-#else /* !(__GNUC__ || __INTEL_COMPILER) */
-
-void insque(void *a, void *b);
-void remque(void *a);
-
-#endif /* __GNUC__ || __INTEL_COMPILER */
-
-#endif /* _KERNEL */
-
-#endif /* !_SYS_QUEUE_H_ */
* a null arg because we know it's not needed.
*/
#define A_MS_TICKGET() OS_GETUPTIME(NULL)
-#define A_MEM_ZERO(p,s) OS_MEMZERO(p,s)
#define WLAN_PHY_OFDM IEEE80211_T_OFDM
#define WLAN_PHY_TURBO IEEE80211_T_TURBO
#include <adf_os_atomic.h>
#include <adf_nbuf.h>
#include <adf_net.h>
-#include <adf_net_types.h>
#include <ieee80211_var.h>
#include "ratectrl.h"
#include "ratectrl11n.h"
-INLINE A_RSSI median(A_RSSI a, A_RSSI b, A_RSSI c);
-
static void ath_rate_newassoc_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew,
unsigned int capflag, struct ieee80211_rate *rs);
}
-static INLINE A_BOOL
-rcIsValidTxMask(TX_RATE_CTRL *pRc, A_UINT8 index)
-{
- ASSERT(index < pRc->rateTableSize);
- return (pRc->validRateIndex[index]);
-}
-
/* Iterators for validTxRateMask */
static INLINE A_BOOL
rcGetNextValidTxRate(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc,
rcSortValidRates(pRateTable, pRc);
}
-
-
-/*
- * Return the median of three numbers
- */
-INLINE A_RSSI median(A_RSSI a, A_RSSI b, A_RSSI c)
-{
- if (a >= b) {
- if (b >= c) {
- return b;
- } else if (a > c) {
- return c;
- } else {
- return a;
- }
- } else {
- if (a >= c) {
- return a;
- } else if (b >= c) {
- return c;
- } else {
- return b;
- }
- }
-}
-
static A_UINT8
rcRateFind_ht(struct ath_softc_tgt *sc, struct atheros_node *pSib,
const RATE_TABLE_11N *pRateTable, A_BOOL probeAllowed, A_BOOL *isProbing)
return &asc->arc;
}
-void
-ath_rate_detach(struct ath_ratectrl *rc)
-{
- adf_os_mem_free(rc);
-}
-
void
ath_rate_findrate(struct ath_softc_tgt *sc,
struct ath_node_target *an,
rcSibUpdate_ht(sc, an, capflag, 0, rs);
}
}
-
-void ath_rate_mcs2rate(struct ath_softc_tgt *sc,a_uint8_t sgi, a_uint8_t ht40,
- a_uint8_t rateCode, a_uint32_t *txrate, a_uint32_t *rxrate)
-{
- int idx;
- struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc;
- RATE_TABLE_11N *pRateTable = (RATE_TABLE_11N *)asc->hwRateTable[sc->sc_curmode];
- a_uint32_t rateKbps = 0;
-
- *txrate = asc->currentTxRateKbps;
-
- /* look 11NA table for rateKbps*/
- for (idx = 0; idx < pRateTable->rateCount && !rateKbps; ++idx) {
- if (pRateTable->info[idx].rateCode == rateCode) {
- if(ht40 && sgi) {
- if(pRateTable->info[idx].valid == TRUE_40 &&
- pRateTable->info[idx].phy == WLAN_RC_PHY_HT_40_DS_HGI)
- rateKbps = pRateTable->info[idx].rateKbps;
- } else if (ht40) {
- if (pRateTable->info[idx].valid == TRUE_40)/* HT40 only*/
- rateKbps = pRateTable->info[idx].rateKbps;
- } else {
- if (pRateTable->info[idx].valid != FALSE)
- rateKbps = pRateTable->info[idx].rateKbps;
- }
- }
- }
-
- *rxrate = rateKbps;
-}
projects / open-ath9k-htc-firmware.git / commitdiff