--- /dev/null
+/*
+ * xtensa/config/core.h -- HAL definitions dependent on CORE configuration
+ *
+ * This header file is sometimes referred to as the "compile-time HAL" or CHAL.
+ * It pulls definitions tailored for a specific Xtensa processor configuration.
+ *
+ * Sources for binaries meant to be configuration-independent generally avoid
+ * including this file (they may use the configuration-specific HAL library).
+ * It is normal for the HAL library source itself to include this file.
+ */
+
+/*
+ * Copyright (c) 2005-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+
+#ifndef XTENSA_CONFIG_CORE_H
+#define XTENSA_CONFIG_CORE_H
+
+/* CONFIGURATION INDEPENDENT DEFINITIONS: */
+#ifdef __XTENSA__
+#include <xtensa/hal.h>
+#else
+#include "../hal.h"
+#endif
+
+/* CONFIGURATION SPECIFIC DEFINITIONS: */
+#ifdef __XTENSA__
+#include <xtensa/config/core-isa.h>
+#include <xtensa/config/core-matmap.h>
+#include <xtensa/config/tie.h>
+#else
+#include "core-isa.h"
+#include "core-matmap.h"
+#include "tie.h"
+#endif
+
+#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
+#ifdef __XTENSA__
+#include <xtensa/config/tie-asm.h>
+#else
+#include "tie-asm.h"
+#endif
+#endif /*_ASMLANGUAGE or __ASSEMBLER__*/
+
+
+/*----------------------------------------------------------------------
+ GENERAL
+ ----------------------------------------------------------------------*/
+
+/*
+ * Separators for macros that expand into arrays.
+ * These can be predefined by files that #include this one,
+ * when different separators are required.
+ */
+/* Element separator for macros that expand into 1-dimensional arrays: */
+#ifndef XCHAL_SEP
+#define XCHAL_SEP ,
+#endif
+/* Array separator for macros that expand into 2-dimensional arrays: */
+#ifndef XCHAL_SEP2
+#define XCHAL_SEP2 },{
+#endif
+
+
+
+/*----------------------------------------------------------------------
+ ISA
+ ----------------------------------------------------------------------*/
+
+#if XCHAL_HAVE_BE
+# define XCHAL_HAVE_LE 0
+# define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN
+#else
+# define XCHAL_HAVE_LE 1
+# define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN
+#endif
+
+
+
+/*----------------------------------------------------------------------
+ INTERRUPTS
+ ----------------------------------------------------------------------*/
+
+/* Indexing macros: */
+#define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK
+#define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */
+#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
+#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
+#define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM
+#define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */
+#define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL
+#define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */
+#define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE
+#define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */
+#define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT
+#define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */
+
+
+#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
+#define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */
+#define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */
+/* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */
+
+/* These values are constant for existing Xtensa processor implementations: */
+#define XCHAL_INTLEVEL0_MASK 0x00000000
+#define XCHAL_INTLEVEL8_MASK 0x00000000
+#define XCHAL_INTLEVEL9_MASK 0x00000000
+#define XCHAL_INTLEVEL10_MASK 0x00000000
+#define XCHAL_INTLEVEL11_MASK 0x00000000
+#define XCHAL_INTLEVEL12_MASK 0x00000000
+#define XCHAL_INTLEVEL13_MASK 0x00000000
+#define XCHAL_INTLEVEL14_MASK 0x00000000
+#define XCHAL_INTLEVEL15_MASK 0x00000000
+
+/* Array of masks of interrupts at each interrupt level: */
+#define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL1_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL2_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL3_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL4_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL5_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL6_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL7_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL8_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL9_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL10_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL11_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL12_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL13_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL14_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL15_MASK
+
+/* These values are constant for existing Xtensa processor implementations: */
+#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
+#define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
+
+/* Mask of all low-priority interrupts: */
+#define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK
+
+/* Mask of all interrupts masked by PS.EXCM (or CEXCM): */
+#define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL)
+
+/* Array of masks of interrupts at each range 1..n of interrupt levels: */
+#define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \
+ XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK
+
+#if 0 /*XCHAL_HAVE_NMI*/
+/* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */
+# define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1)
+#endif
+
+/* Array of levels of each possible interrupt: */
+#define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \
+ XCHAL_SEP XCHAL_INT1_LEVEL \
+ XCHAL_SEP XCHAL_INT2_LEVEL \
+ XCHAL_SEP XCHAL_INT3_LEVEL \
+ XCHAL_SEP XCHAL_INT4_LEVEL \
+ XCHAL_SEP XCHAL_INT5_LEVEL \
+ XCHAL_SEP XCHAL_INT6_LEVEL \
+ XCHAL_SEP XCHAL_INT7_LEVEL \
+ XCHAL_SEP XCHAL_INT8_LEVEL \
+ XCHAL_SEP XCHAL_INT9_LEVEL \
+ XCHAL_SEP XCHAL_INT10_LEVEL \
+ XCHAL_SEP XCHAL_INT11_LEVEL \
+ XCHAL_SEP XCHAL_INT12_LEVEL \
+ XCHAL_SEP XCHAL_INT13_LEVEL \
+ XCHAL_SEP XCHAL_INT14_LEVEL \
+ XCHAL_SEP XCHAL_INT15_LEVEL \
+ XCHAL_SEP XCHAL_INT16_LEVEL \
+ XCHAL_SEP XCHAL_INT17_LEVEL \
+ XCHAL_SEP XCHAL_INT18_LEVEL \
+ XCHAL_SEP XCHAL_INT19_LEVEL \
+ XCHAL_SEP XCHAL_INT20_LEVEL \
+ XCHAL_SEP XCHAL_INT21_LEVEL \
+ XCHAL_SEP XCHAL_INT22_LEVEL \
+ XCHAL_SEP XCHAL_INT23_LEVEL \
+ XCHAL_SEP XCHAL_INT24_LEVEL \
+ XCHAL_SEP XCHAL_INT25_LEVEL \
+ XCHAL_SEP XCHAL_INT26_LEVEL \
+ XCHAL_SEP XCHAL_INT27_LEVEL \
+ XCHAL_SEP XCHAL_INT28_LEVEL \
+ XCHAL_SEP XCHAL_INT29_LEVEL \
+ XCHAL_SEP XCHAL_INT30_LEVEL \
+ XCHAL_SEP XCHAL_INT31_LEVEL
+
+/* Array of types of each possible interrupt: */
+#define XCHAL_INT_TYPES XCHAL_INT0_TYPE \
+ XCHAL_SEP XCHAL_INT1_TYPE \
+ XCHAL_SEP XCHAL_INT2_TYPE \
+ XCHAL_SEP XCHAL_INT3_TYPE \
+ XCHAL_SEP XCHAL_INT4_TYPE \
+ XCHAL_SEP XCHAL_INT5_TYPE \
+ XCHAL_SEP XCHAL_INT6_TYPE \
+ XCHAL_SEP XCHAL_INT7_TYPE \
+ XCHAL_SEP XCHAL_INT8_TYPE \
+ XCHAL_SEP XCHAL_INT9_TYPE \
+ XCHAL_SEP XCHAL_INT10_TYPE \
+ XCHAL_SEP XCHAL_INT11_TYPE \
+ XCHAL_SEP XCHAL_INT12_TYPE \
+ XCHAL_SEP XCHAL_INT13_TYPE \
+ XCHAL_SEP XCHAL_INT14_TYPE \
+ XCHAL_SEP XCHAL_INT15_TYPE \
+ XCHAL_SEP XCHAL_INT16_TYPE \
+ XCHAL_SEP XCHAL_INT17_TYPE \
+ XCHAL_SEP XCHAL_INT18_TYPE \
+ XCHAL_SEP XCHAL_INT19_TYPE \
+ XCHAL_SEP XCHAL_INT20_TYPE \
+ XCHAL_SEP XCHAL_INT21_TYPE \
+ XCHAL_SEP XCHAL_INT22_TYPE \
+ XCHAL_SEP XCHAL_INT23_TYPE \
+ XCHAL_SEP XCHAL_INT24_TYPE \
+ XCHAL_SEP XCHAL_INT25_TYPE \
+ XCHAL_SEP XCHAL_INT26_TYPE \
+ XCHAL_SEP XCHAL_INT27_TYPE \
+ XCHAL_SEP XCHAL_INT28_TYPE \
+ XCHAL_SEP XCHAL_INT29_TYPE \
+ XCHAL_SEP XCHAL_INT30_TYPE \
+ XCHAL_SEP XCHAL_INT31_TYPE
+
+/* Array of masks of interrupts for each type of interrupt: */
+#define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \
+ XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \
+ XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \
+ XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \
+ XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \
+ XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \
+ XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR
+
+/* Interrupts that can be cleared using the INTCLEAR special register: */
+#define XCHAL_INTCLEARABLE_MASK (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR)
+/* Interrupts that can be triggered using the INTSET special register: */
+#define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE
+
+/* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */
+#define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \
+ XCHAL_SEP XCHAL_TIMER1_INTERRUPT \
+ XCHAL_SEP XCHAL_TIMER2_INTERRUPT \
+ XCHAL_SEP XCHAL_TIMER3_INTERRUPT
+
+
+
+/* For backward compatibility and for the array macros, define macros for
+ * each unconfigured interrupt number (unfortunately, the value of
+ * XTHAL_INTTYPE_UNCONFIGURED is not zero): */
+#if XCHAL_NUM_INTERRUPTS == 0
+# define XCHAL_INT0_LEVEL 0
+# define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 1
+# define XCHAL_INT1_LEVEL 0
+# define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 2
+# define XCHAL_INT2_LEVEL 0
+# define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 3
+# define XCHAL_INT3_LEVEL 0
+# define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 4
+# define XCHAL_INT4_LEVEL 0
+# define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 5
+# define XCHAL_INT5_LEVEL 0
+# define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 6
+# define XCHAL_INT6_LEVEL 0
+# define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 7
+# define XCHAL_INT7_LEVEL 0
+# define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 8
+# define XCHAL_INT8_LEVEL 0
+# define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 9
+# define XCHAL_INT9_LEVEL 0
+# define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 10
+# define XCHAL_INT10_LEVEL 0
+# define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 11
+# define XCHAL_INT11_LEVEL 0
+# define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 12
+# define XCHAL_INT12_LEVEL 0
+# define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 13
+# define XCHAL_INT13_LEVEL 0
+# define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 14
+# define XCHAL_INT14_LEVEL 0
+# define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 15
+# define XCHAL_INT15_LEVEL 0
+# define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 16
+# define XCHAL_INT16_LEVEL 0
+# define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 17
+# define XCHAL_INT17_LEVEL 0
+# define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 18
+# define XCHAL_INT18_LEVEL 0
+# define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 19
+# define XCHAL_INT19_LEVEL 0
+# define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 20
+# define XCHAL_INT20_LEVEL 0
+# define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 21
+# define XCHAL_INT21_LEVEL 0
+# define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 22
+# define XCHAL_INT22_LEVEL 0
+# define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 23
+# define XCHAL_INT23_LEVEL 0
+# define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 24
+# define XCHAL_INT24_LEVEL 0
+# define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 25
+# define XCHAL_INT25_LEVEL 0
+# define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 26
+# define XCHAL_INT26_LEVEL 0
+# define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 27
+# define XCHAL_INT27_LEVEL 0
+# define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 28
+# define XCHAL_INT28_LEVEL 0
+# define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 29
+# define XCHAL_INT29_LEVEL 0
+# define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 30
+# define XCHAL_INT30_LEVEL 0
+# define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 31
+# define XCHAL_INT31_LEVEL 0
+# define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED
+#endif
+
+
+/*
+ * Masks and levels corresponding to each *external* interrupt.
+ */
+
+#define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM)
+#define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM)
+#define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM)
+#define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM)
+#define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM)
+#define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM)
+#define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM)
+#define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM)
+#define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM)
+#define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM)
+#define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM)
+#define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM)
+#define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM)
+#define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM)
+#define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM)
+#define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM)
+#define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM)
+#define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM)
+#define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM)
+#define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM)
+#define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM)
+#define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM)
+#define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM)
+#define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM)
+#define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM)
+#define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM)
+#define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM)
+#define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM)
+#define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM)
+#define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM)
+#define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM)
+#define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM)
+#define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM)
+#define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM)
+#define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM)
+#define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM)
+#define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM)
+#define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM)
+#define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM)
+#define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM)
+#define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM)
+#define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM)
+#define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM)
+#define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM)
+#define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM)
+#define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM)
+#define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM)
+#define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM)
+#define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM)
+#define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM)
+#define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM)
+#define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM)
+#define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM)
+#define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM)
+#define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM)
+#define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM)
+#define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM)
+#define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM)
+#define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM)
+#define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM)
+#define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM)
+#define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM)
+#define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM)
+#define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM)
+
+
+/*----------------------------------------------------------------------
+ EXCEPTIONS and VECTORS
+ ----------------------------------------------------------------------*/
+
+/* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */
+#define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
+#define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
+#ifdef XCHAL_USER_VECTOR_VADDR
+#define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR
+#define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR
+#endif
+#ifdef XCHAL_USER_VECTOR_PADDR
+# define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR
+# define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR
+#endif
+#ifdef XCHAL_KERNEL_VECTOR_VADDR
+# define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR
+# define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR
+#endif
+#ifdef XCHAL_KERNEL_VECTOR_PADDR
+# define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR
+# define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR
+#endif
+
+#if 0
+#if XCHAL_HAVE_DEBUG
+# define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL)
+/* This one should only get defined if the corresponding intlevel paddr macro exists: */
+# define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL)
+#endif
+#endif
+
+/* Indexing macros: */
+#define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
+#define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */
+
+/*
+ * General Exception Causes
+ * (values of EXCCAUSE special register set by general exceptions,
+ * which vector to the user, kernel, or double-exception vectors).
+ *
+ * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros
+ * defined in <xtensa/corebits.h>. (Note that these have slightly
+ * different names, they don't just have the XCHAL_ prefix removed.)
+ */
+#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */
+#define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */
+#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */
+#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
+#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
+#define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */
+#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
+#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */
+#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
+#define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */
+/*10..15 reserved*/
+#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */
+#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */
+#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */
+#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */
+#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */
+/*21..23 reserved*/
+#define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */
+#define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */
+#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */
+#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */
+#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */
+#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */
+/*30..31 reserved*/
+#define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */
+#define XCHAL_EXCCAUSE_FLOATING_POINT 40 /* Floating Point Exception */
+/*40..63 reserved*/
+
+
+/*
+ * Miscellaneous special register fields.
+ *
+ * For each special register, and each field within each register:
+ * XCHAL_<regname>_VALIDMASK is the set of bits defined in the register.
+ * XCHAL_<regname>_<field>_BITS is the number of bits in the field.
+ * XCHAL_<regname>_<field>_NUM is 2^bits, the number of possible values
+ * of the field.
+ * XCHAL_<regname>_<field>_SHIFT is the position of the field within
+ * the register, starting from the least significant bit.
+ *
+ * DEPRECATED. Please use the equivalent macros defined in
+ * <xtensa/corebits.h>. (Note that these have different names.)
+ */
+
+/* DBREAKC (special register number 160): */
+#define XCHAL_DBREAKC_VALIDMASK 0xC000003F
+#define XCHAL_DBREAKC_MASK_BITS 6
+#define XCHAL_DBREAKC_MASK_NUM 64
+#define XCHAL_DBREAKC_MASK_SHIFT 0
+#define XCHAL_DBREAKC_MASK_MASK 0x0000003F
+#define XCHAL_DBREAKC_LOADBREAK_BITS 1
+#define XCHAL_DBREAKC_LOADBREAK_NUM 2
+#define XCHAL_DBREAKC_LOADBREAK_SHIFT 30
+#define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000
+#define XCHAL_DBREAKC_STOREBREAK_BITS 1
+#define XCHAL_DBREAKC_STOREBREAK_NUM 2
+#define XCHAL_DBREAKC_STOREBREAK_SHIFT 31
+#define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000
+/* PS (special register number 230): */
+#define XCHAL_PS_VALIDMASK 0x00070F3F
+#define XCHAL_PS_INTLEVEL_BITS 4
+#define XCHAL_PS_INTLEVEL_NUM 16
+#define XCHAL_PS_INTLEVEL_SHIFT 0
+#define XCHAL_PS_INTLEVEL_MASK 0x0000000F
+#define XCHAL_PS_EXCM_BITS 1
+#define XCHAL_PS_EXCM_NUM 2
+#define XCHAL_PS_EXCM_SHIFT 4
+#define XCHAL_PS_EXCM_MASK 0x00000010
+#define XCHAL_PS_UM_BITS 1
+#define XCHAL_PS_UM_NUM 2
+#define XCHAL_PS_UM_SHIFT 5
+#define XCHAL_PS_UM_MASK 0x00000020
+#define XCHAL_PS_RING_BITS 2
+#define XCHAL_PS_RING_NUM 4
+#define XCHAL_PS_RING_SHIFT 6
+#define XCHAL_PS_RING_MASK 0x000000C0
+#define XCHAL_PS_OWB_BITS 4
+#define XCHAL_PS_OWB_NUM 16
+#define XCHAL_PS_OWB_SHIFT 8
+#define XCHAL_PS_OWB_MASK 0x00000F00
+#define XCHAL_PS_CALLINC_BITS 2
+#define XCHAL_PS_CALLINC_NUM 4
+#define XCHAL_PS_CALLINC_SHIFT 16
+#define XCHAL_PS_CALLINC_MASK 0x00030000
+#define XCHAL_PS_WOE_BITS 1
+#define XCHAL_PS_WOE_NUM 2
+#define XCHAL_PS_WOE_SHIFT 18
+#define XCHAL_PS_WOE_MASK 0x00040000
+/* EXCCAUSE (special register number 232): */
+#define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F
+#define XCHAL_EXCCAUSE_BITS 6
+#define XCHAL_EXCCAUSE_NUM 64
+#define XCHAL_EXCCAUSE_SHIFT 0
+#define XCHAL_EXCCAUSE_MASK 0x0000003F
+/* DEBUGCAUSE (special register number 233): */
+#define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F
+#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1
+#define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2
+#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0
+#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001
+#define XCHAL_DEBUGCAUSE_IBREAK_BITS 1
+#define XCHAL_DEBUGCAUSE_IBREAK_NUM 2
+#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1
+#define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002
+#define XCHAL_DEBUGCAUSE_DBREAK_BITS 1
+#define XCHAL_DEBUGCAUSE_DBREAK_NUM 2
+#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2
+#define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004
+#define XCHAL_DEBUGCAUSE_BREAK_BITS 1
+#define XCHAL_DEBUGCAUSE_BREAK_NUM 2
+#define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3
+#define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008
+#define XCHAL_DEBUGCAUSE_BREAKN_BITS 1
+#define XCHAL_DEBUGCAUSE_BREAKN_NUM 2
+#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4
+#define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010
+#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1
+#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2
+#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5
+#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020
+
+
+
+
+/*----------------------------------------------------------------------
+ TIMERS
+ ----------------------------------------------------------------------*/
+
+/*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/
+
+
+
+/*----------------------------------------------------------------------
+ INTERNAL I/D RAM/ROMs and XLMI
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
+#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
+#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */
+#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
+
+#define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */
+#define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */
+#define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */
+#define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */
+#define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */
+#define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */
+#define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */
+#define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */
+#define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */
+#define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */
+#define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */
+#define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */
+#define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */
+#define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */
+#define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */
+#define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */
+#define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */
+#define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */
+#define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */
+#define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */
+#define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */
+#define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */
+#define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */
+#define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */
+
+
+
+/*----------------------------------------------------------------------
+ CACHE
+ ----------------------------------------------------------------------*/
+
+
+/* Max for both I-cache and D-cache (used for general alignment): */
+#if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE
+# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH
+# define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE
+#else
+# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH
+# define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE
+#endif
+
+#define XCHAL_ICACHE_SETSIZE (1<<XCHAL_ICACHE_SETWIDTH)
+#define XCHAL_DCACHE_SETSIZE (1<<XCHAL_DCACHE_SETWIDTH)
+/* Max for both I and D caches (used for cache-coherency page alignment): */
+#if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH
+# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH
+# define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE
+#else
+# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH
+# define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE
+#endif
+
+/* Instruction cache tag bits: */
+#define XCHAL_ICACHE_TAG_V_SHIFT 0
+#define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */
+#if XCHAL_ICACHE_WAYS > 1
+# define XCHAL_ICACHE_TAG_F_SHIFT 1
+# define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */
+#else
+# define XCHAL_ICACHE_TAG_F_SHIFT 0
+# define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */
+#endif
+#if XCHAL_ICACHE_LINE_LOCKABLE
+# define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1)
+# define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* lock bit */
+#else
+# define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT
+# define XCHAL_ICACHE_TAG_L 0 /* no lock bit */
+#endif
+/* Data cache tag bits: */
+#define XCHAL_DCACHE_TAG_V_SHIFT 0
+#define XCHAL_DCACHE_TAG_V 0x1 /* valid bit */
+#if XCHAL_DCACHE_WAYS > 1
+# define XCHAL_DCACHE_TAG_F_SHIFT 1
+# define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */
+#else
+# define XCHAL_DCACHE_TAG_F_SHIFT 0
+# define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */
+#endif
+#if XCHAL_DCACHE_IS_WRITEBACK
+# define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1)
+# define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* dirty bit */
+#else
+# define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT
+# define XCHAL_DCACHE_TAG_D 0 /* no dirty bit */
+#endif
+#if XCHAL_DCACHE_LINE_LOCKABLE
+# define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1)
+# define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* lock bit */
+#else
+# define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT
+# define XCHAL_DCACHE_TAG_L 0 /* no lock bit */
+#endif
+
+
+/*----------------------------------------------------------------------
+ MMU
+ ----------------------------------------------------------------------*/
+
+/* See <xtensa/config/core-matmap.h> for more details. */
+
+#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */
+
+/* Indexing macros: */
+#define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what
+#define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what )
+#define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what
+#define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what )
+#define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what
+#define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what )
+#define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what
+#define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what )
+/*
+ * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
+ * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
+ */
+
+/* Number of entries per autorefill way: */
+#define XCHAL_ITLB_ARF_ENTRIES (1<<XCHAL_ITLB_ARF_ENTRIES_LOG2)
+#define XCHAL_DTLB_ARF_ENTRIES (1<<XCHAL_DTLB_ARF_ENTRIES_LOG2)
+
+/*
+ * Determine whether we have a full MMU (with Page Table and Protection)
+ * usable for an MMU-based OS:
+ */
+#if 0
+#if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
+# define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */
+#else
+# define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */
+#endif
+#endif
+
+/*
+ * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
+ */
+#if XCHAL_HAVE_PTP_MMU
+#define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */
+#define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */
+#define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */
+#define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */
+#define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */
+#define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */
+
+#define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */
+#define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */
+#define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */
+#define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */
+#define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */
+#define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */
+
+#define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */
+#define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */
+/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */
+#endif
+
+
+/*----------------------------------------------------------------------
+ MISC
+ ----------------------------------------------------------------------*/
+
+/* Data alignment required if used for instructions: */
+#if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH
+# define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH
+#else
+# define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH
+#endif
+
+/*
+ * Names kept for backward compatibility.
+ * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
+ * under which they are released. In the T10##.# era there was no distinction.)
+ */
+#define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR
+#define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR
+#define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME
+
+
+
+
+/*----------------------------------------------------------------------
+ COPROCESSORS and EXTRA STATE
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE
+#define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN
+#define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE
+#define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN
+
+#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
+
+#define xchal_extratie_load xchal_ncptie_load
+#define xchal_extratie_store xchal_ncptie_store
+#define xchal_extratie_load_a2 xchal_ncptie_load_a2
+#define xchal_extratie_store_a2 xchal_ncptie_store_a2
+#define xchal_extra_load xchal_ncp_load
+#define xchal_extra_store xchal_ncp_store
+#define xchal_extra_load_a2 xchal_ncp_load_a2
+#define xchal_extra_store_a2 xchal_ncp_store_a2
+#define xchal_extra_load_funcbody xchal_ncp_load_a2
+#define xchal_extra_store_funcbody xchal_ncp_store_a2
+
+/* Empty placeholder macros for undefined coprocessors: */
+# ifndef XCHAL_CP0_NAME
+# define xchal_cp0_store_a2 xchal_cp0_store a2, a3
+# define xchal_cp0_load_a2 xchal_cp0_load a2, a3
+ .macro xchal_cp0_store ptr tmp
+ .endm
+ .macro xchal_cp0_load ptr tmp
+ .endm
+# endif
+# ifndef XCHAL_CP1_NAME
+# define xchal_cp1_store_a2 xchal_cp1_store a2, a3
+# define xchal_cp1_load_a2 xchal_cp1_load a2, a3
+ .macro xchal_cp1_store ptr tmp
+ .endm
+ .macro xchal_cp1_load ptr tmp
+ .endm
+# endif
+# ifndef XCHAL_CP2_NAME
+# define xchal_cp2_store_a2 xchal_cp2_store a2, a3
+# define xchal_cp2_load_a2 xchal_cp2_load a2, a3
+ .macro xchal_cp2_store ptr tmp
+ .endm
+ .macro xchal_cp2_load ptr tmp
+ .endm
+# endif
+# ifndef XCHAL_CP3_NAME
+# define xchal_cp3_store_a2 xchal_cp3_store a2, a3
+# define xchal_cp3_load_a2 xchal_cp3_load a2, a3
+ .macro xchal_cp3_store ptr tmp
+ .endm
+ .macro xchal_cp3_load ptr tmp
+ .endm
+# endif
+# ifndef XCHAL_CP4_NAME
+# define xchal_cp4_store_a2 xchal_cp4_store a2, a3
+# define xchal_cp4_load_a2 xchal_cp4_load a2, a3
+ .macro xchal_cp4_store ptr tmp
+ .endm
+ .macro xchal_cp4_load ptr tmp
+ .endm
+# endif
+# ifndef XCHAL_CP5_NAME
+# define xchal_cp5_store_a2 xchal_cp5_store a2, a3
+# define xchal_cp5_load_a2 xchal_cp5_load a2, a3
+ .macro xchal_cp5_store ptr tmp
+ .endm
+ .macro xchal_cp5_load ptr tmp
+ .endm
+# endif
+# ifndef XCHAL_CP6_NAME
+# define xchal_cp6_store_a2 xchal_cp6_store a2, a3
+# define xchal_cp6_load_a2 xchal_cp6_load a2, a3
+ .macro xchal_cp6_store ptr tmp
+ .endm
+ .macro xchal_cp6_load ptr tmp
+ .endm
+# endif
+# ifndef XCHAL_CP7_NAME
+# define xchal_cp7_store_a2 xchal_cp7_store a2, a3
+# define xchal_cp7_load_a2 xchal_cp7_load a2, a3
+ .macro xchal_cp7_store ptr tmp
+ .endm
+ .macro xchal_cp7_load ptr tmp
+ .endm
+# endif
+
+ /********************
+ * Macros to create functions that save and restore the state of *any* TIE
+ * coprocessor (by dynamic index).
+ */
+
+ /*
+ * Macro that expands to the body of a function
+ * that stores the selected coprocessor's state (registers etc).
+ * Entry: a2 = ptr to save area in which to save cp state
+ * a3 = coprocessor number
+ * Exit: any register a2-a15 (?) may have been clobbered.
+ */
+ .macro xchal_cpi_store_funcbody
+# ifdef XCHAL_CP0_NAME
+ bnez a3, 99f
+ xchal_cp0_store_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP1_NAME
+ bnei a3, 1, 99f
+ xchal_cp1_store_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP2_NAME
+ bnei a3, 2, 99f
+ xchal_cp2_store_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP3_NAME
+ bnei a3, 3, 99f
+ xchal_cp3_store_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP4_NAME
+ bnei a3, 4, 99f
+ xchal_cp4_store_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP5_NAME
+ bnei a3, 5, 99f
+ xchal_cp5_store_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP6_NAME
+ bnei a3, 6, 99f
+ xchal_cp6_store_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP7_NAME
+ bnei a3, 7, 99f
+ xchal_cp7_store_a2
+ j 90f
+99:
+# endif
+90:
+ .endm
+
+ /*
+ * Macro that expands to the body of a function
+ * that loads the selected coprocessor's state (registers etc).
+ * Entry: a2 = ptr to save area from which to restore cp state
+ * a3 = coprocessor number
+ * Exit: any register a2-a15 (?) may have been clobbered.
+ */
+ .macro xchal_cpi_load_funcbody
+# ifdef XCHAL_CP0_NAME
+ bnez a3, 99f
+ xchal_cp0_load_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP1_NAME
+ bnei a3, 1, 99f
+ xchal_cp1_load_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP2_NAME
+ bnei a3, 2, 99f
+ xchal_cp2_load_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP3_NAME
+ bnei a3, 3, 99f
+ xchal_cp3_load_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP4_NAME
+ bnei a3, 4, 99f
+ xchal_cp4_load_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP5_NAME
+ bnei a3, 5, 99f
+ xchal_cp5_load_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP6_NAME
+ bnei a3, 6, 99f
+ xchal_cp6_load_a2
+ j 90f
+99:
+# endif
+# ifdef XCHAL_CP7_NAME
+ bnei a3, 7, 99f
+ xchal_cp7_load_a2
+ j 90f
+99:
+# endif
+90:
+ .endm
+
+#endif /*_ASMLANGUAGE or __ASSEMBLER__*/
+
+
+/* Other default macros for undefined coprocessors: */
+#ifndef XCHAL_CP0_NAME
+# define XCHAL_CP0_SA_SIZE 0
+# define XCHAL_CP0_SA_ALIGN 1
+# define XCHAL_CP0_NAME 0
+# define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
+# define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
+#endif
+#ifndef XCHAL_CP1_NAME
+# define XCHAL_CP1_SA_SIZE 0
+# define XCHAL_CP1_SA_ALIGN 1
+# define XCHAL_CP1_NAME 0
+# define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
+# define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
+#endif
+#ifndef XCHAL_CP2_NAME
+# define XCHAL_CP2_SA_SIZE 0
+# define XCHAL_CP2_SA_ALIGN 1
+# define XCHAL_CP2_NAME 0
+# define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
+# define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
+#endif
+#ifndef XCHAL_CP3_NAME
+# define XCHAL_CP3_SA_SIZE 0
+# define XCHAL_CP3_SA_ALIGN 1
+# define XCHAL_CP3_NAME 0
+# define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
+# define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
+#endif
+#ifndef XCHAL_CP4_NAME
+# define XCHAL_CP4_SA_SIZE 0
+# define XCHAL_CP4_SA_ALIGN 1
+# define XCHAL_CP4_NAME 0
+# define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
+# define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
+#endif
+#ifndef XCHAL_CP5_NAME
+# define XCHAL_CP5_SA_SIZE 0
+# define XCHAL_CP5_SA_ALIGN 1
+# define XCHAL_CP5_NAME 0
+# define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
+# define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
+#endif
+#ifndef XCHAL_CP6_NAME
+# define XCHAL_CP6_SA_SIZE 0
+# define XCHAL_CP6_SA_ALIGN 1
+# define XCHAL_CP6_NAME 0
+# define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
+# define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
+#endif
+#ifndef XCHAL_CP7_NAME
+# define XCHAL_CP7_SA_SIZE 0
+# define XCHAL_CP7_SA_ALIGN 1
+# define XCHAL_CP7_NAME 0
+# define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
+# define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
+#endif
+
+/* Indexing macros: */
+#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
+#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
+#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
+#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
+
+#define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */
+
+/* Link-time HAL global variables that report coprocessor numbers by name
+ (names are case-preserved from the original TIE): */
+#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
+# define _XCJOIN(a,b) a ## b
+# define XCJOIN(a,b) _XCJOIN(a,b)
+# ifdef XCHAL_CP0_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT);
+extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT);
+# endif
+# ifdef XCHAL_CP1_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT);
+extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT);
+# endif
+# ifdef XCHAL_CP2_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT);
+extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT);
+# endif
+# ifdef XCHAL_CP3_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT);
+extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT);
+# endif
+# ifdef XCHAL_CP4_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT);
+extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT);
+# endif
+# ifdef XCHAL_CP5_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT);
+extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT);
+# endif
+# ifdef XCHAL_CP6_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT);
+extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT);
+# endif
+# ifdef XCHAL_CP7_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT);
+extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT);
+# endif
+#endif
+
+
+
+
+/*----------------------------------------------------------------------
+ DERIVED
+ ----------------------------------------------------------------------*/
+
+#if XCHAL_HAVE_BE
+#define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */
+#define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */
+#define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */
+#else
+#define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */
+#define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */
+#define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */
+#endif
+/* Belongs in xtensa/hal.h: */
+#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
+
+
+/*
+ * Because information as to exactly which hardware version is targeted
+ * by a given software build is not always available, compile-time HAL
+ * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
+ * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
+ * under which they are released. In the T10##.# era there was no distinction.)
+ */
+#if XCHAL_HW_CONFIGID_RELIABLE
+# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
+# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
+# define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
+# define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0)
+#else
+# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
+ : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
+ : XTHAL_MAYBE )
+# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
+ : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
+ : XTHAL_MAYBE )
+# define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
+ ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
+# define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0)
+#endif
+
+/*
+ * Specific errata:
+ */
+
+/*
+ * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
+ * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
+ */
+#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \
+ (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
+ || XCHAL_HW_RELEASE_AT(1050,0)))
+
+
+
+#endif /*XTENSA_CONFIG_CORE_H*/
--- /dev/null
+/*
+ * xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
+ *
+ * (In previous releases, these were defined in specreg.h, a generated file.
+ * This file is not generated, ie. it is processor configuration independent.)
+ */
+
+/* $Id: //depot/rel/BadgerPass/Xtensa/OS/include/xtensa/corebits.h#3 $ */
+
+/*
+ * Copyright (c) 2005-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+#ifndef XTENSA_COREBITS_H
+#define XTENSA_COREBITS_H
+
+/* EXCCAUSE register fields: */
+#define EXCCAUSE_EXCCAUSE_SHIFT 0
+#define EXCCAUSE_EXCCAUSE_MASK 0x3F
+/* EXCCAUSE register values: */
+/*
+ * General Exception Causes
+ * (values of EXCCAUSE special register set by general exceptions,
+ * which vector to the user, kernel, or double-exception vectors).
+ */
+#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
+#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
+#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
+# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
+#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
+# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
+#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
+# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
+#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
+#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
+#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
+#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
+#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
+/* Reserved 10..11 */
+#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
+#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
+#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
+#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
+#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
+#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
+#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
+/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
+#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
+/* Reserved 21..23 */
+#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
+#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
+#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
+/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
+#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
+#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
+/* Reserved 30..31 */
+#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
+#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
+#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
+#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
+#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
+#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
+#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
+#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
+#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
+/*#define EXCCAUSE_FLOATING_POINT 40*/ /* Floating Point Exception (not implemented) */
+/* Reserved 40..63 */
+
+/* PS register fields: */
+#define PS_WOE_SHIFT 18
+#define PS_WOE_MASK 0x00040000
+#define PS_WOE PS_WOE_MASK
+#define PS_CALLINC_SHIFT 16
+#define PS_CALLINC_MASK 0x00030000
+#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
+#define PS_OWB_SHIFT 8
+#define PS_OWB_MASK 0x00000F00
+#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
+#define PS_RING_SHIFT 6
+#define PS_RING_MASK 0x000000C0
+#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
+#define PS_UM_SHIFT 5
+#define PS_UM_MASK 0x00000020
+#define PS_UM PS_UM_MASK
+#define PS_EXCM_SHIFT 4
+#define PS_EXCM_MASK 0x00000010
+#define PS_EXCM PS_EXCM_MASK
+#define PS_INTLEVEL_SHIFT 0
+#define PS_INTLEVEL_MASK 0x0000000F
+#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
+/* Backward compatibility (deprecated): */
+#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
+#define PS_PROGSTACK_MASK PS_UM_MASK
+#define PS_PROG_SHIFT PS_UM_SHIFT
+#define PS_PROG_MASK PS_UM_MASK
+#define PS_PROG PS_UM
+
+/* DBREAKCn register fields: */
+#define DBREAKC_MASK_SHIFT 0
+#define DBREAKC_MASK_MASK 0x0000003F
+#define DBREAKC_LOADBREAK_SHIFT 30
+#define DBREAKC_LOADBREAK_MASK 0x40000000
+#define DBREAKC_STOREBREAK_SHIFT 31
+#define DBREAKC_STOREBREAK_MASK 0x80000000
+
+/* DEBUGCAUSE register fields: */
+#define DEBUGCAUSE_DEBUGINT_SHIFT 5
+#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
+#define DEBUGCAUSE_BREAKN_SHIFT 4
+#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
+#define DEBUGCAUSE_BREAK_SHIFT 3
+#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
+#define DEBUGCAUSE_DBREAK_SHIFT 2
+#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
+#define DEBUGCAUSE_IBREAK_SHIFT 1
+#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
+#define DEBUGCAUSE_ICOUNT_SHIFT 0
+#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
+
+/* MESR register fields: */
+#define MESR_MEME 0x00000001 /* memory error */
+#define MESR_MEME_SHIFT 0
+#define MESR_DME 0x00000002 /* double memory error */
+#define MESR_DME_SHIFT 1
+#define MESR_RCE 0x00000010 /* recorded memory error */
+#define MESR_RCE_SHIFT 4
+#define MESR_LCE
+#define MESR_LCE_SHIFT ?
+#define MESR_LCE_L
+#define MESR_ERRENAB 0x00000100
+#define MESR_ERRENAB_SHIFT 8
+#define MESR_ERRTEST 0x00000200
+#define MESR_ERRTEST_SHIFT 9
+#define MESR_DATEXC 0x00000400
+#define MESR_DATEXC_SHIFT 10
+#define MESR_INSEXC 0x00000800
+#define MESR_INSEXC_SHIFT 11
+#define MESR_WAYNUM_SHIFT 16
+#define MESR_ACCTYPE_SHIFT 20
+#define MESR_MEMTYPE_SHIFT 24
+#define MESR_ERRTYPE_SHIFT 30
+
+
+#endif /*XTENSA_COREBITS_H*/
--- /dev/null
+/*
+ xtensa/hal.h -- contains a definition of the Core HAL interface
+
+ All definitions in this header file are independent of any specific
+ Xtensa processor configuration. Thus software (eg. OS, application,
+ etc) can include this header file and be compiled into configuration-
+ independent objects that can be distributed and eventually linked
+ to the HAL library (libhal.a) to create a configuration-specific
+ final executable.
+
+ Certain definitions, however, are release/version-specific -- such as
+ the XTHAL_RELEASE_xxx macros (or additions made in later versions).
+
+
+ $Id: //depot/rel/BadgerPass/Xtensa/OS/target-os-src/hal.h.tpp#2 $
+
+ Copyright (c) 1999-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
+ These coded instructions, statements, and computer programs are the
+ copyrighted works and confidential proprietary information of Tensilica Inc.
+ They may not be modified, copied, reproduced, distributed, or disclosed to
+ third parties in any manner, medium, or form, in whole or in part, without
+ the prior written consent of Tensilica Inc.
+*/
+
+#ifndef XTENSA_HAL_H
+#define XTENSA_HAL_H
+
+
+/****************************************************************************
+ Definitions Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+
+/*----------------------------------------------------------------------
+ Constant Definitions (shared with assembly)
+ ----------------------------------------------------------------------*/
+
+/*
+ * Software (Xtensa Tools) version information. Not configuration-specific!
+ *
+ * NOTE: "release" is a misnomer here, these are really product "version"
+ * numbers. A "release" is a collection of product versions
+ * made available at once (together) to customers.
+ * In the past, release and version names all matched in T####.# form,
+ * making the distinction irrelevant. This is no longer the case.
+ */
+#define XTHAL_RELEASE_MAJOR 7010
+#define XTHAL_RELEASE_MINOR 0
+#define XTHAL_RELEASE_NAME "7.1.0"
+#define XTHAL_REL_7 1
+#define XTHAL_REL_7_1 1
+#define XTHAL_REL_7_1_0 1
+
+/* HAL version numbers (these names are for backward compatibility): */
+#define XTHAL_MAJOR_REV XTHAL_RELEASE_MAJOR
+#define XTHAL_MINOR_REV XTHAL_RELEASE_MINOR
+/*
+ * A bit of software release/version history on values of XTHAL_{MAJOR,MINOR}_REV:
+ *
+ * SW Version MAJOR MINOR Comment
+ * ======= ===== ===== =======
+ * T1015.n n/a n/a (HAL not yet available)
+ * T1020.{0,1,2} 0 1 (HAL beta)
+ * T1020.{3,4} 0 2 First release.
+ * T1020.n (n>4) 0 2 or >3 (TBD)
+ * T1030.0 0 1 (HAL beta)
+ * T1030.{1,2} 0 3 Equivalent to first release.
+ * T1030.n (n>=3) 0 >= 3 (TBD)
+ * T1040.n 1040 n Full CHAL available from T1040.2
+ * T1050.n 1050 n .
+ * 6.0.n 6000 n Xtensa Tools v6 (RA-200x.n)
+ * 7.0.n 7000 n Xtensa Tools v7 (RB-200x.n)
+ * 7.1.n 7010 n Xtensa Tools v7.1 (RB-200x.(n+2))
+ *
+ *
+ * Note: there is a distinction between the software version with
+ * which something is compiled (accessible using XTHAL_RELEASE_* macros)
+ * and the software version with which the HAL library was compiled
+ * (accessible using Xthal_release_* global variables). This
+ * distinction is particularly relevant for vendors that distribute
+ * configuration-independent binaries (eg. an OS), where their customer
+ * might link it with a HAL of a different Xtensa software version.
+ * In this case, it may be appropriate for the OS to verify at run-time
+ * whether XTHAL_RELEASE_* and Xthal_release_* are compatible.
+ * [Guidelines as to which version is compatible with which are not
+ * currently provided explicitly, but might be inferred from reading
+ * OSKit documentation for all releases -- compatibility is also highly
+ * dependent on which HAL features are used. Each version is usually
+ * backward compatible, with very few exceptions if any.]
+ *
+ * Notes:
+ * Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only.
+ * Tornado 2.0.2 supported in T1040.2+, T1050, and 6.0.
+ * Compile-time HAL port of NucleusPlus supported by T1040.2 and later.
+ */
+
+/* Version comparison operators (among major/minor pairs): */
+#define XTHAL_REL_GE(maja,mina, majb,minb) ((maja) > (majb) || \
+ ((maja) == (majb) && (mina) >= (minb)))
+#define XTHAL_REL_GT(maja,mina, majb,minb) ((maja) > (majb) || \
+ ((maja) == (majb) && (mina) > (minb)))
+#define XTHAL_REL_LE(maja,mina, majb,minb) ((maja) < (majb) || \
+ ((maja) == (majb) && (mina) <= (minb)))
+#define XTHAL_REL_LT(maja,mina, majb,minb) ((maja) < (majb) || \
+ ((maja) == (majb) && (mina) < (minb)))
+#define XTHAL_REL_EQ(maja,mina, majb,minb) ((maja) == (majb) && (mina) == (minb))
+
+/* Fuzzy (3-way) logic operators: */
+#define XTHAL_MAYBE -1 /* 0=NO, 1=YES, -1=MAYBE */
+#define XTHAL_FUZZY_AND(a,b) (((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE)
+#define XTHAL_FUZZY_OR(a,b) (((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE)
+#define XTHAL_FUZZY_NOT(a) (((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE)
+
+
+/*
+ * Architectural limit, independent of configuration:
+ */
+#define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */
+
+/* Misc: */
+#define XTHAL_LITTLEENDIAN 0
+#define XTHAL_BIGENDIAN 1
+
+
+
+#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------
+ HAL
+ ----------------------------------------------------------------------*/
+
+/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */
+extern const unsigned int Xthal_rev_no;
+
+
+/*----------------------------------------------------------------------
+ Optional/Custom Processor State
+ ----------------------------------------------------------------------*/
+
+/* save & restore the extra processor state */
+extern void xthal_save_extra(void *base);
+extern void xthal_restore_extra(void *base);
+
+extern void xthal_save_cpregs(void *base, int);
+extern void xthal_restore_cpregs(void *base, int);
+/* versions specific to each coprocessor id */
+extern void xthal_save_cp0(void *base);
+extern void xthal_save_cp1(void *base);
+extern void xthal_save_cp2(void *base);
+extern void xthal_save_cp3(void *base);
+extern void xthal_save_cp4(void *base);
+extern void xthal_save_cp5(void *base);
+extern void xthal_save_cp6(void *base);
+extern void xthal_save_cp7(void *base);
+extern void xthal_restore_cp0(void *base);
+extern void xthal_restore_cp1(void *base);
+extern void xthal_restore_cp2(void *base);
+extern void xthal_restore_cp3(void *base);
+extern void xthal_restore_cp4(void *base);
+extern void xthal_restore_cp5(void *base);
+extern void xthal_restore_cp6(void *base);
+extern void xthal_restore_cp7(void *base);
+/* pointers to each of the functions above */
+extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS];
+extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS];
+/* similarly for non-windowed ABI (may be same or different) */
+extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS];
+extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS];
+
+/*extern void xthal_save_all_extra(void *base);*/
+/*extern void xthal_restore_all_extra(void *base);*/
+
+/* space for processor state */
+extern const unsigned int Xthal_extra_size;
+extern const unsigned int Xthal_extra_align;
+extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];
+extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];
+extern const unsigned int Xthal_all_extra_size;
+extern const unsigned int Xthal_all_extra_align;
+/* coprocessor names */
+extern const char * const Xthal_cp_names[XTHAL_MAX_CPS];
+
+/* initialize the extra processor */
+/*extern void xthal_init_extra(void);*/
+/* initialize the TIE coprocessor */
+/*extern void xthal_init_cp(int);*/
+
+/* initialize the extra processor */
+extern void xthal_init_mem_extra(void *);
+/* initialize the TIE coprocessor */
+extern void xthal_init_mem_cp(void *, int);
+
+/* the number of TIE coprocessors contiguous from zero (for Tor2) */
+extern const unsigned int Xthal_num_coprocessors;
+
+/* actual number of coprocessors */
+extern const unsigned char Xthal_cp_num;
+/* index of highest numbered coprocessor, plus one */
+extern const unsigned char Xthal_cp_max;
+/* index of highest allowed coprocessor number, per cfg, plus one */
+/*extern const unsigned char Xthal_cp_maxcfg;*/
+/* bitmask of which coprocessors are present */
+extern const unsigned int Xthal_cp_mask;
+
+/* read & write extra state register */
+/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/
+/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/
+
+/* read & write a TIE coprocessor register */
+/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/
+/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/
+
+/* return coprocessor number based on register */
+/*extern int xthal_which_cp(unsigned reg);*/
+
+
+/*----------------------------------------------------------------------
+ Register Windows
+ ----------------------------------------------------------------------*/
+
+/* number of registers in register window */
+extern const unsigned int Xthal_num_aregs;
+extern const unsigned char Xthal_num_aregs_log2;
+
+
+/*----------------------------------------------------------------------
+ Cache
+ ----------------------------------------------------------------------*/
+
+/* size of the cache lines in log2(bytes) */
+extern const unsigned char Xthal_icache_linewidth;
+extern const unsigned char Xthal_dcache_linewidth;
+/* size of the cache lines in bytes (2^linewidth) */
+extern const unsigned short Xthal_icache_linesize;
+extern const unsigned short Xthal_dcache_linesize;
+
+/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */
+extern const unsigned int Xthal_icache_size;
+extern const unsigned int Xthal_dcache_size;
+/* cache features */
+extern const unsigned char Xthal_dcache_is_writeback;
+
+/* invalidate the caches */
+extern void xthal_icache_region_invalidate( void *addr, unsigned size );
+extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
+extern void xthal_icache_line_invalidate(void *addr);
+extern void xthal_dcache_line_invalidate(void *addr);
+/* write dirty data back */
+extern void xthal_dcache_region_writeback( void *addr, unsigned size );
+extern void xthal_dcache_line_writeback(void *addr);
+/* write dirty data back and invalidate */
+extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
+extern void xthal_dcache_line_writeback_inv(void *addr);
+
+/* sync icache and memory */
+extern void xthal_icache_sync( void );
+/* sync dcache and memory */
+extern void xthal_dcache_sync( void );
+
+
+/*----------------------------------------------------------------------
+ Debug
+ ----------------------------------------------------------------------*/
+
+/* 1 if debug option configured, 0 if not: */
+extern const int Xthal_debug_configured;
+
+/* Set (plant) and remove software breakpoint, both synchronizing cache: */
+extern unsigned int xthal_set_soft_break(void *addr);
+extern void xthal_remove_soft_break(void *addr, unsigned int);
+
+
+/*----------------------------------------------------------------------
+ Disassembler
+ ----------------------------------------------------------------------*/
+
+/* Max expected size of the return buffer for a disassembled instruction (hint only): */
+#define XTHAL_DISASM_BUFSIZE 80
+
+/* Disassembly option bits for selecting what to return: */
+#define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */
+#define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */
+#define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */
+#define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */
+#define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */
+
+/* routine to get a string for the disassembled instruction */
+extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,
+ char *buffer, unsigned buflen, unsigned options );
+
+/* routine to get the size of the next instruction. Returns 0 for
+ illegal instruction */
+extern int xthal_disassemble_size( unsigned char *instr_buf );
+
+
+/*----------------------------------------------------------------------
+ Instruction/Data RAM/ROM Access
+ ----------------------------------------------------------------------*/
+
+extern void* xthal_memcpy(void *dst, const void *src, unsigned len);
+extern void* xthal_bcopy(const void *src, void *dst, unsigned len);
+
+
+/*----------------------------------------------------------------------
+ MP Synchronization
+ ----------------------------------------------------------------------*/
+
+extern int xthal_compare_and_set( int *addr, int test_val, int compare_val );
+
+/*extern const char Xthal_have_s32c1i;*/
+
+
+/*----------------------------------------------------------------------
+ Miscellaneous
+ ----------------------------------------------------------------------*/
+
+extern const unsigned int Xthal_release_major;
+extern const unsigned int Xthal_release_minor;
+extern const char * const Xthal_release_name;
+extern const char * const Xthal_release_internal;
+
+extern const unsigned char Xthal_memory_order;
+extern const unsigned char Xthal_have_windowed;
+extern const unsigned char Xthal_have_density;
+extern const unsigned char Xthal_have_booleans;
+extern const unsigned char Xthal_have_loops;
+extern const unsigned char Xthal_have_nsa;
+extern const unsigned char Xthal_have_minmax;
+extern const unsigned char Xthal_have_sext;
+extern const unsigned char Xthal_have_clamps;
+extern const unsigned char Xthal_have_mac16;
+extern const unsigned char Xthal_have_mul16;
+extern const unsigned char Xthal_have_fp;
+extern const unsigned char Xthal_have_speculation;
+extern const unsigned char Xthal_have_threadptr;
+
+extern const unsigned char Xthal_have_pif;
+extern const unsigned short Xthal_num_writebuffer_entries;
+
+extern const unsigned int Xthal_build_unique_id;
+/* Version info for hardware targeted by software upgrades: */
+extern const unsigned int Xthal_hw_configid0;
+extern const unsigned int Xthal_hw_configid1;
+extern const unsigned int Xthal_hw_release_major;
+extern const unsigned int Xthal_hw_release_minor;
+extern const char * const Xthal_hw_release_name;
+extern const char * const Xthal_hw_release_internal;
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
+
+
+
+
+
+/****************************************************************************
+ Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+ Constant Definitions (shared with assembly)
+ ----------------------------------------------------------------------*/
+
+/*
+ * Architectural limits, independent of configuration.
+ * Note that these are ISA-defined limits, not micro-architecture implementation
+ * limits enforced by the Xtensa Processor Generator (which may be stricter than
+ * these below).
+ */
+#define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */
+#define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */
+ /* (as of T1040, implementation limit is 7: 0..6) */
+#define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */
+ /* (as of T1040, implementation limit is 3: 0..2) */
+
+/* Interrupt types: */
+#define XTHAL_INTTYPE_UNCONFIGURED 0
+#define XTHAL_INTTYPE_SOFTWARE 1
+#define XTHAL_INTTYPE_EXTERN_EDGE 2
+#define XTHAL_INTTYPE_EXTERN_LEVEL 3
+#define XTHAL_INTTYPE_TIMER 4
+#define XTHAL_INTTYPE_NMI 5
+#define XTHAL_INTTYPE_WRITE_ERROR 6
+#define XTHAL_MAX_INTTYPES 7 /* number of interrupt types */
+
+/* Timer related: */
+#define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */
+#define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */
+
+/* Local Memory ECC/Parity: */
+#define XTHAL_MEMEP_PARITY 1
+#define XTHAL_MEMEP_ECC 2
+/* Flags parameter to xthal_memep_inject_error(): */
+#define XTHAL_MEMEP_F_LOCAL 0 /* local memory (default) */
+#define XTHAL_MEMEP_F_DCACHE_DATA 4 /* data cache data */
+#define XTHAL_MEMEP_F_DCACHE_TAG 5 /* data cache tag */
+#define XTHAL_MEMEP_F_ICACHE_DATA 6 /* instruction cache data */
+#define XTHAL_MEMEP_F_ICACHE_TAG 7 /* instruction cache tag */
+#define XTHAL_MEMEP_F_CORRECTABLE 16 /* inject correctable error
+ (default is non-corr.) */
+
+
+/* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */
+#define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none
+ exception on any access (aka "illegal") */
+#define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI)
+ [or H HC] way from tag match;
+ [or U UC] (ISA: same except Isolate case) */
+#define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none
+ [or F FI fill] refill cache on miss, way from LRU
+ (ISA: Read/Write Miss Refill) */
+#define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT
+ store immediately to memory (ISA: same) */
+#define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none
+ use cache regardless of hit-vs-miss,
+ way from vaddr (ISA: use-cache-on-miss+hit) */
+#define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G *
+ non-speculative; spec/replay refs not permitted */
+#if 0
+#define XTHAL_AMB_COHERENT 6 /* 040 M MC ?ls: Mem/MP Coherent M
+ on read, other CPU/bus-master may need to supply data;
+ on write, maybe redirect to or flush other CPU dirty line; etc */
+#define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G *
+ mem accesses cannot be out of order */
+#define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none
+ allow combining/merging multiple writes
+ (to same datapath data unit) into one
+ (implied by writeback) */
+#define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none
+ memory will not bus error (if it does,
+ handle as fatal imprecise interrupt) */
+#define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none
+ on refill, read line+1 into prefetch buffers */
+#define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none
+ access one of N stream buffers */
+#endif /*0*/
+
+#define XTHAL_AM_EXCEPTION (1<<XTHAL_AMB_EXCEPTION)
+#define XTHAL_AM_HITCACHE (1<<XTHAL_AMB_HITCACHE)
+#define XTHAL_AM_ALLOCATE (1<<XTHAL_AMB_ALLOCATE)
+#define XTHAL_AM_WRITETHRU (1<<XTHAL_AMB_WRITETHRU)
+#define XTHAL_AM_ISOLATE (1<<XTHAL_AMB_ISOLATE)
+#define XTHAL_AM_GUARD (1<<XTHAL_AMB_GUARD)
+#if 0
+#define XTHAL_AM_ORDERED (1<<XTHAL_AMB_ORDERED)
+#define XTHAL_AM_FUSEWRITES (1<<XTHAL_AMB_FUSEWRITES)
+#define XTHAL_AM_COHERENT (1<<XTHAL_AMB_COHERENT)
+#define XTHAL_AM_TRUSTED (1<<XTHAL_AMB_TRUSTED)
+#define XTHAL_AM_PREFETCH (1<<XTHAL_AMB_PREFETCH)
+#define XTHAL_AM_STREAM (1<<XTHAL_AMB_STREAM)
+#endif /*0*/
+
+/*
+ * Allowed Access Modes (bit combinations).
+ *
+ * Columns are:
+ * "FOGIWACE"
+ * Access mode bits (see XTHAL_AMB_xxx above).
+ * <letter> = bit is set
+ * '-' = bit is clear
+ * '.' = bit is irrelevant / don't care, as follows:
+ * E=1 makes all others irrelevant
+ * W,F relevant only for stores
+ * "2345"
+ * Indicates which Xtensa releases support the corresponding
+ * access mode. Releases for each character column are:
+ * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1
+ * 3 = T1020.2 and later: T1020.2+, T1030
+ * 4 = T1040
+ * 5 = T1050 (maybe), LX1, LX2, LX2.1
+ * 7 = LX2.2
+ * And the character column contents are:
+ * <number> = support by release(s)
+ * "." = unsupported by release(s)
+ * "?" = support unknown
+ */
+ /* FOMGIWACE 23457 */
+/* For instruction fetch: */
+#define XTHAL_FAM_EXCEPTION 0x001 /* ........E 23457 exception */
+#define XTHAL_FAM_ISOLATE 0x012 /* .---I.-C- ..... isolate */
+#define XTHAL_FAM_BYPASS 0x000 /* .----.--- 23457 bypass */
+#define XTHAL_FAM_NACACHED 0x002 /* .----.-C- ..... cached no-allocate (frozen) */
+#define XTHAL_FAM_CACHED 0x006 /* .----.AC- 23457 cached */
+/* For data load: */
+#define XTHAL_LAM_EXCEPTION 0x001 /* ........E 23457 exception */
+#define XTHAL_LAM_ISOLATE 0x012 /* .---I.-C- 23457 isolate */
+#define XTHAL_LAM_BYPASS 0x000 /* .O---.--- 2.... bypass speculative */
+#define XTHAL_LAM_BYPASSG 0x020 /* .O-G-.--- .3457 bypass guarded */
+#define XTHAL_LAM_NACACHED 0x002 /* .O---.-C- 2.... cached no-allocate speculative */
+#define XTHAL_LAM_NACACHEDG 0x022 /* .O-G-.-C- .3457 cached no-allocate guarded */
+#define XTHAL_LAM_CACHED 0x006 /* .----.AC- 23457 cached speculative */
+#define XTHAL_LAM_CACHEDG 0x026 /* .?-G-.AC- ..... cached guarded */
+#define XTHAL_LAM_CACHEDM 0x046 /* .-M--.AC- ....7 cached MP-coherent (experimental) */
+/* For data store: */
+#define XTHAL_SAM_EXCEPTION 0x001 /* ........E 23457 exception */
+#define XTHAL_SAM_ISOLATE 0x032 /* .--GI--C- 23457 isolate */
+#define XTHAL_SAM_BYPASS 0x028 /* -O-G-W--- 23457 bypass */
+/*efine XTHAL_SAM_BYPASSF 0x028*/ /* F--G-W--- ..... bypass write-combined */
+#define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 23457 writethrough */
+/*efine XTHAL_SAM_WRITETHRUF 0x02A*/ /* F--G-W-C- ..... writethrough write-combined */
+#define XTHAL_SAM_WRITEALLOC 0x02E /* -O-G-WAC- ..... writethrough-allocate */
+/*efine XTHAL_SAM_WRITEALLOCF 0x02E*/ /* F--G-WAC- ..... writethrough-allocate write-combined */
+#define XTHAL_SAM_WRITEBACK 0x066 /* F-MG--AC- ...57 writeback (MP-coherent if configured) */
+
+#if 0
+/*
+ Cache attribute encoding for CACHEATTR (per ISA):
+ (Note: if this differs from ISA Ref Manual, ISA has precedence)
+
+ Inst-fetches Loads Stores
+ ------------- ------------ -------------
+0x0 FCA_EXCEPTION ?LCA_NACACHED_G* SCA_WRITETHRU "uncached" (cached no-allocate)
+0x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached
+0x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass
+0x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate
+ or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
+0x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK write-back
+ or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
+0x5..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved)
+0xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate
+0xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal
+ * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)
+*/
+#endif /*0*/
+
+
+#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*----------------------------------------------------------------------
+ Register Windows
+ ----------------------------------------------------------------------*/
+
+/* This spill any live register windows (other than the caller's):
+ * (NOTE: current implementation require privileged code, but
+ * a user-callable implementation is possible.) */
+extern void xthal_window_spill( void );
+
+
+/*----------------------------------------------------------------------
+ Optional/Custom Processor State
+ ----------------------------------------------------------------------*/
+
+/* validate & invalidate the TIE register file */
+extern void xthal_validate_cp(int);
+extern void xthal_invalidate_cp(int);
+
+/* read and write cpenable register */
+extern void xthal_set_cpenable(unsigned);
+extern unsigned xthal_get_cpenable(void);
+
+
+/*----------------------------------------------------------------------
+ Interrupts
+ ----------------------------------------------------------------------*/
+
+/* the number of interrupt levels */
+extern const unsigned char Xthal_num_intlevels;
+/* the number of interrupts */
+extern const unsigned char Xthal_num_interrupts;
+
+/* mask for level of interrupts */
+extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];
+/* mask for level 0 to N interrupts */
+extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];
+
+/* level of each interrupt */
+extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];
+
+/* type per interrupt */
+extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];
+
+/* masks of each type of interrupt */
+extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];
+
+/* interrupt numbers assigned to each timer interrupt */
+extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];
+
+/* INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions: */
+extern unsigned xthal_get_intenable( void );
+extern void xthal_set_intenable( unsigned );
+extern unsigned xthal_get_interrupt( void );
+#define xthal_get_intread xthal_get_interrupt /* backward compatibility */
+extern void xthal_set_intset( unsigned );
+extern void xthal_set_intclear( unsigned );
+
+
+/*----------------------------------------------------------------------
+ Debug
+ ----------------------------------------------------------------------*/
+
+/* Number of instruction and data break registers: */
+extern const int Xthal_num_ibreak;
+extern const int Xthal_num_dbreak;
+
+
+/*----------------------------------------------------------------------
+ Core Counter
+ ----------------------------------------------------------------------*/
+
+/* counter info */
+extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */
+extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */
+
+/* get CCOUNT register (if not present return 0) */
+extern unsigned xthal_get_ccount(void);
+
+/* set and get CCOMPAREn registers (if not present, get returns 0) */
+extern void xthal_set_ccompare(int, unsigned);
+extern unsigned xthal_get_ccompare(int);
+
+
+/*----------------------------------------------------------------------
+ Miscellaneous
+ ----------------------------------------------------------------------*/
+
+extern const unsigned char Xthal_have_prid;
+extern const unsigned char Xthal_have_exceptions;
+extern const unsigned char Xthal_xea_version;
+extern const unsigned char Xthal_have_interrupts;
+extern const unsigned char Xthal_have_highlevel_interrupts;
+extern const unsigned char Xthal_have_nmi;
+
+extern unsigned xthal_get_prid( void );
+
+
+/*----------------------------------------------------------------------
+ Virtual interrupt prioritization (DEPRECATED)
+ ----------------------------------------------------------------------*/
+
+/* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */
+extern unsigned xthal_vpri_to_intlevel(unsigned vpri);
+extern unsigned xthal_intlevel_to_vpri(unsigned intlevel);
+
+/* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */
+extern unsigned xthal_int_enable(unsigned);
+extern unsigned xthal_int_disable(unsigned);
+
+/* Set/get virtual priority of an interrupt: */
+extern int xthal_set_int_vpri(int intnum, int vpri);
+extern int xthal_get_int_vpri(int intnum);
+
+/* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */
+extern void xthal_set_vpri_locklevel(unsigned intlevel);
+extern unsigned xthal_get_vpri_locklevel(void);
+
+/* Set/get current virtual interrupt priority: */
+extern unsigned xthal_set_vpri(unsigned vpri);
+extern unsigned xthal_get_vpri(void);
+extern unsigned xthal_set_vpri_intlevel(unsigned intlevel);
+extern unsigned xthal_set_vpri_lock(void);
+
+
+/*----------------------------------------------------------------------
+ Generic Interrupt Trampolining Support (DEPRECATED)
+ ----------------------------------------------------------------------*/
+
+typedef void (XtHalVoidFunc)(void);
+
+/* Bitmask of interrupts currently trampolining down: */
+extern unsigned Xthal_tram_pending;
+
+/*
+ * Bitmask of which interrupts currently trampolining down synchronously are
+ * actually enabled; this bitmask is necessary because INTENABLE cannot hold
+ * that state (sync-trampolining interrupts must be kept disabled while
+ * trampolining); in the current implementation, any bit set here is not set
+ * in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level
+ * one), its enable bit must be moved from here to INTENABLE:
+ */
+extern unsigned Xthal_tram_enabled;
+
+/* Bitmask of interrupts configured for sync trampolining: */
+extern unsigned Xthal_tram_sync;
+
+/* Trampoline support functions: */
+extern unsigned xthal_tram_pending_to_service( void );
+extern void xthal_tram_done( unsigned serviced_mask );
+extern int xthal_tram_set_sync( int intnum, int sync );
+extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );
+
+
+/*----------------------------------------------------------------------
+ Internal Memories
+ ----------------------------------------------------------------------*/
+
+extern const unsigned char Xthal_num_instrom;
+extern const unsigned char Xthal_num_instram;
+extern const unsigned char Xthal_num_datarom;
+extern const unsigned char Xthal_num_dataram;
+extern const unsigned char Xthal_num_xlmi;
+
+/* Each of the following arrays contains at least one entry,
+ * or as many entries as needed if more than one: */
+extern const unsigned int Xthal_instrom_vaddr[];
+extern const unsigned int Xthal_instrom_paddr[];
+extern const unsigned int Xthal_instrom_size [];
+extern const unsigned int Xthal_instram_vaddr[];
+extern const unsigned int Xthal_instram_paddr[];
+extern const unsigned int Xthal_instram_size [];
+extern const unsigned int Xthal_datarom_vaddr[];
+extern const unsigned int Xthal_datarom_paddr[];
+extern const unsigned int Xthal_datarom_size [];
+extern const unsigned int Xthal_dataram_vaddr[];
+extern const unsigned int Xthal_dataram_paddr[];
+extern const unsigned int Xthal_dataram_size [];
+extern const unsigned int Xthal_xlmi_vaddr[];
+extern const unsigned int Xthal_xlmi_paddr[];
+extern const unsigned int Xthal_xlmi_size [];
+
+
+/*----------------------------------------------------------------------
+ Cache
+ ----------------------------------------------------------------------*/
+
+/* number of cache sets in log2(lines per way) */
+extern const unsigned char Xthal_icache_setwidth;
+extern const unsigned char Xthal_dcache_setwidth;
+/* cache set associativity (number of ways) */
+extern const unsigned int Xthal_icache_ways;
+extern const unsigned int Xthal_dcache_ways;
+/* cache features */
+extern const unsigned char Xthal_icache_line_lockable;
+extern const unsigned char Xthal_dcache_line_lockable;
+
+/* cache attribute register control (used by other HAL routines) */
+extern unsigned xthal_get_cacheattr( void );
+extern unsigned xthal_get_icacheattr( void );
+extern unsigned xthal_get_dcacheattr( void );
+extern void xthal_set_cacheattr( unsigned );
+extern void xthal_set_icacheattr( unsigned );
+extern void xthal_set_dcacheattr( unsigned );
+/* set cache attribute (access modes) for a range of memory */
+extern int xthal_set_region_attribute( void *addr, unsigned size,
+ unsigned cattr, unsigned flags );
+/* Bits of flags parameter to xthal_set_region_attribute(): */
+#define XTHAL_CAFLAG_EXPAND 0x000100 /* only expand allowed access to range, don't reduce it */
+#define XTHAL_CAFLAG_EXACT 0x000200 /* return error if can't apply change to exact range specified */
+#define XTHAL_CAFLAG_NO_PARTIAL 0x000400 /* don't apply change to regions partially covered by range */
+#define XTHAL_CAFLAG_NO_AUTO_WB 0x000800 /* don't writeback data after leaving writeback attribute */
+#define XTHAL_CAFLAG_NO_AUTO_INV 0x001000 /* don't invalidate after disabling cache (entering bypass) */
+
+/* enable caches */
+extern void xthal_icache_enable( void ); /* DEPRECATED */
+extern void xthal_dcache_enable( void ); /* DEPRECATED */
+/* disable caches */
+extern void xthal_icache_disable( void ); /* DEPRECATED */
+extern void xthal_dcache_disable( void ); /* DEPRECATED */
+
+/* invalidate the caches */
+extern void xthal_icache_all_invalidate( void );
+extern void xthal_dcache_all_invalidate( void );
+/* write dirty data back */
+extern void xthal_dcache_all_writeback( void );
+/* write dirty data back and invalidate */
+extern void xthal_dcache_all_writeback_inv( void );
+/* prefetch and lock specified memory range into cache */
+extern void xthal_icache_region_lock( void *addr, unsigned size );
+extern void xthal_dcache_region_lock( void *addr, unsigned size );
+extern void xthal_icache_line_lock(void *addr);
+extern void xthal_dcache_line_lock(void *addr);
+/* unlock from cache */
+extern void xthal_icache_all_unlock( void );
+extern void xthal_dcache_all_unlock( void );
+extern void xthal_icache_region_unlock( void *addr, unsigned size );
+extern void xthal_dcache_region_unlock( void *addr, unsigned size );
+extern void xthal_icache_line_unlock(void *addr);
+extern void xthal_dcache_line_unlock(void *addr);
+
+
+
+/*----------------------------------------------------------------------
+ Local Memory ECC/Parity
+ ----------------------------------------------------------------------*/
+
+/* Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx: */
+extern void xthal_memep_inject_error(void *addr, int size, int flags);
+
+
+
+/*----------------------------------------------------------------------
+ Memory Management Unit
+ ----------------------------------------------------------------------*/
+
+extern const unsigned char Xthal_have_spanning_way;
+extern const unsigned char Xthal_have_identity_map;
+extern const unsigned char Xthal_have_mimic_cacheattr;
+extern const unsigned char Xthal_have_xlt_cacheattr;
+extern const unsigned char Xthal_have_cacheattr;
+extern const unsigned char Xthal_have_tlbs;
+
+extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */
+extern const unsigned char Xthal_mmu_asid_kernel;
+extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
+extern const unsigned char Xthal_mmu_ring_bits;
+extern const unsigned char Xthal_mmu_sr_bits;
+extern const unsigned char Xthal_mmu_ca_bits;
+extern const unsigned int Xthal_mmu_max_pte_page_size;
+extern const unsigned int Xthal_mmu_min_pte_page_size;
+
+extern const unsigned char Xthal_itlb_way_bits;
+extern const unsigned char Xthal_itlb_ways;
+extern const unsigned char Xthal_itlb_arf_ways;
+extern const unsigned char Xthal_dtlb_way_bits;
+extern const unsigned char Xthal_dtlb_ways;
+extern const unsigned char Xthal_dtlb_arf_ways;
+
+/* Convert between virtual and physical addresses (through static maps only): */
+/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/
+extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
+extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+
+
+/****************************************************************************
+ EXPERIMENTAL and DEPRECATED Definitions
+ ****************************************************************************/
+
+
+#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef INCLUDE_DEPRECATED_HAL_CODE
+extern const unsigned char Xthal_have_old_exc_arch;
+extern const unsigned char Xthal_have_mmu;
+extern const unsigned int Xthal_num_regs;
+extern const unsigned char Xthal_num_iroms;
+extern const unsigned char Xthal_num_irams;
+extern const unsigned char Xthal_num_droms;
+extern const unsigned char Xthal_num_drams;
+extern const unsigned int Xthal_configid0;
+extern const unsigned int Xthal_configid1;
+#endif
+
+#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
+#define XTHAL_24_BIT_BREAK 0x80000000
+#define XTHAL_16_BIT_BREAK 0x40000000
+extern const unsigned short Xthal_ill_inst_16[16];
+#define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */
+#define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */
+#define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */
+#define XTHAL_RFW_INST 0x00000800
+#define XTHAL_RFUE_INST 0x00000400
+#define XTHAL_RFI_INST 0x00000200
+#define XTHAL_RFE_INST 0x00000100
+#define XTHAL_RET_INST 0x00000080
+#define XTHAL_BREAK_INST 0x00000040
+#define XTHAL_SYSCALL_INST 0x00000020
+#define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */
+#define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */
+#define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */
+#define XTHAL_24_BIT_INST 0x00000002
+#define XTHAL_16_BIT_INST 0x00000001
+typedef struct xthal_state {
+ unsigned pc;
+ unsigned ar[16];
+ unsigned lbeg;
+ unsigned lend;
+ unsigned lcount;
+ unsigned extra_ptr;
+ unsigned cpregs_ptr[XTHAL_MAX_CPS];
+} XTHAL_STATE;
+extern unsigned int xthal_inst_type(void *addr);
+extern unsigned int xthal_branch_addr(void *addr);
+extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);
+#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
+
+#endif /*XTENSA_HAL_H*/
--- /dev/null
+/*
+ * xtruntime.h -- general C definitions for single-threaded run-time
+ *
+ * Copyright (c) 2002-2006 by Tensilica Inc. ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+#ifndef XTRUNTIME_H
+#define XTRUNTIME_H
+
+#include <xtensa/config/core.h>
+#include <xtensa/config/specreg.h>
+
+#ifndef XTSTR
+#define _XTSTR(x) # x
+#define XTSTR(x) _XTSTR(x)
+#endif
+
+#define _xtos_set_execption_handler _xtos_set_exception_handler /* backward compatibility */
+#define _xtos_set_saved_intenable _xtos_ints_on /* backward compatibility */
+#define _xtos_clear_saved_intenable _xtos_ints_off /* backward compatibility */
+
+#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*typedef void (_xtos_timerdelta_func)(int);*/
+#ifdef __cplusplus
+typedef void (_xtos_handler_func)(...);
+#else
+typedef void (_xtos_handler_func)();
+#endif
+typedef _xtos_handler_func *_xtos_handler;
+
+/*
+ * unsigned XTOS_SET_INTLEVEL(int intlevel);
+ * This macro sets the current interrupt level.
+ * The 'intlevel' parameter must be a constant.
+ * This macro returns a 32-bit value that must be passed to
+ * XTOS_RESTORE_INTLEVEL() to restore the previous interrupt level.
+ * XTOS_RESTORE_JUST_INTLEVEL() also does this, but in XEA2 configs
+ * it restores only PS.INTLEVEL rather than the entire PS register
+ * and thus is slower.
+ */
+#if !XCHAL_HAVE_INTERRUPTS
+# define XTOS_SET_INTLEVEL(intlevel)
+# define XTOS_SET_MIN_INTLEVEL(intlevel)
+# define XTOS_RESTORE_INTLEVEL(restoreval)
+# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)
+#elif XCHAL_HAVE_XEA2
+/* In XEA2, we can simply safely set PS.INTLEVEL directly: */
+/* NOTE: these asm macros don't modify memory, but they are marked
+ * as such to act as memory access barriers to the compiler because
+ * these macros are sometimes used to delineate critical sections;
+ * function calls are natural barriers (the compiler does not know
+ * whether a function modifies memory) unless declared to be inlined. */
+# define XTOS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \
+ __asm__ __volatile__( "rsil %0, " XTSTR(intlevel) "\n" \
+ : "=a" (__tmp) : : "memory" ); \
+ __tmp;})
+# define XTOS_SET_MIN_INTLEVEL(intlevel) ({ unsigned __tmp, __tmp2, __tmp3; \
+ __asm__ __volatile__( "rsr %0, " XTSTR(PS) "\n" /* get old (current) PS.INTLEVEL */ \
+ "movi %2, " XTSTR(intlevel) "\n" \
+ "extui %1, %0, 0, 4\n" /* keep only INTLEVEL bits of parameter */ \
+ "blt %2, %1, 1f\n" \
+ "rsil %0, " XTSTR(intlevel) "\n" \
+ "1:\n" \
+ : "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \
+ __tmp;})
+# define XTOS_RESTORE_INTLEVEL(restoreval) do{ unsigned __tmp = (restoreval); \
+ __asm__ __volatile__( "wsr %0, " XTSTR(PS) " ; rsync\n" \
+ : : "a" (__tmp) : "memory" ); \
+ }while(0)
+# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_intlevel(restoreval)
+#else
+/* In XEA1, we have to rely on INTENABLE register virtualization: */
+extern unsigned _xtos_set_vpri( unsigned vpri );
+extern unsigned _xtos_vpri_enabled; /* current virtual priority */
+# define XTOS_SET_INTLEVEL(intlevel) _xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
+# define XTOS_SET_MIN_INTLEVEL(intlevel) _xtos_set_vpri(_xtos_vpri_enabled & ~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
+# define XTOS_RESTORE_INTLEVEL(restoreval) _xtos_set_vpri(restoreval)
+# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_vpri(restoreval)
+#endif
+
+/*
+ * The following macros build upon the above. They are generally used
+ * instead of invoking the SET_INTLEVEL and SET_MIN_INTLEVEL macros directly.
+ * They all return a value that can be used with XTOS_RESTORE_INTLEVEL()
+ * or _xtos_restore_intlevel() or _xtos_restore_just_intlevel() to restore
+ * the effective interrupt level to what it was before the macro was invoked.
+ * In XEA2, the DISABLE macros are much faster than the MASK macros
+ * (in all configs, DISABLE sets the effective interrupt level, whereas MASK
+ * makes ensures the effective interrupt level is at least the level given
+ * without lowering it; in XEA2 with INTENABLE virtualization, these macros
+ * affect PS.INTLEVEL only, not the virtual priority, so DISABLE has partial
+ * MASK semantics).
+ *
+ * A typical critical section sequence might be:
+ * unsigned rval = XTOS_DISABLE_EXCM_INTERRUPTS;
+ * ... critical section ...
+ * XTOS_RESTORE_INTLEVEL(rval);
+ */
+/* Enable all interrupts (those activated with _xtos_ints_on()): */
+#define XTOS_ENABLE_INTERRUPTS XTOS_SET_INTLEVEL(0)
+/* Disable low priority level interrupts (they can interact with the OS): */
+#define XTOS_DISABLE_LOWPRI_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
+#define XTOS_MASK_LOWPRI_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
+/* Disable interrupts that can interact with the OS: */
+#define XTOS_DISABLE_EXCM_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL)
+#define XTOS_MASK_EXCM_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_EXCM_LEVEL)
+#if 0 /* XTOS_LOCK_LEVEL is not exported to applications */
+/* Disable interrupts that can interact with the OS, or manipulate virtual INTENABLE: */
+#define XTOS_DISABLE_LOCK_INTERRUPTS XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL)
+#define XTOS_MASK_LOCK_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XTOS_LOCK_LEVEL)
+#endif
+/* Disable ALL interrupts (not for common use, particularly if one's processor
+ * configuration has high-level interrupts and one cares about their latency): */
+#define XTOS_DISABLE_ALL_INTERRUPTS XTOS_SET_INTLEVEL(15)
+
+
+extern unsigned int _xtos_ints_off( unsigned int mask );
+extern unsigned int _xtos_ints_on( unsigned int mask );
+extern unsigned _xtos_set_intlevel( int intlevel );
+extern unsigned _xtos_set_min_intlevel( int intlevel );
+extern unsigned _xtos_restore_intlevel( unsigned restoreval );
+extern unsigned _xtos_restore_just_intlevel( unsigned restoreval );
+extern _xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f );
+extern _xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg );
+extern _xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f );
+
+extern void _xtos_memep_initrams( void );
+extern void _xtos_memep_enable( int flags );
+
+/* Deprecated (but kept because they were documented): */
+extern unsigned int _xtos_read_ints( void ); /* use xthal_get_interrupt() instead */
+extern void _xtos_clear_ints( unsigned int mask ); /* use xthal_set_intclear() instead */
+
+#if XCHAL_NUM_CONTEXTS > 1
+extern unsigned _xtos_init_context(int context_num, int stack_size,
+ _xtos_handler_func *start_func, int arg1);
+#endif
+
+/* Deprecated: */
+#if XCHAL_NUM_TIMERS > 0
+extern void _xtos_timer_0_delta( int cycles );
+#endif
+#if XCHAL_NUM_TIMERS > 1
+extern void _xtos_timer_1_delta( int cycles );
+#endif
+#if XCHAL_NUM_TIMERS > 2
+extern void _xtos_timer_2_delta( int cycles );
+#endif
+#if XCHAL_NUM_TIMERS > 3
+extern void _xtos_timer_3_delta( int cycles );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */
+
+#endif /* XTRUNTIME_H */
-I$MAGPIE_ROOT/target/inc \
-I$MAGPIE_ROOT/target/inc/OTUS \
-I$MAGPIE_ROOT/target/adf/ \
+ -I$MAGPIE_ROOT/build/include/xtensa-elf/ \
-I$MAGPIE_ROOT/build/include";
-I$MAGPIE_ROOT/target/inc \
-I$MAGPIE_ROOT/target/inc/OTUS \
-I$MAGPIE_ROOT/target/adf/ \
+ -I$MAGPIE_ROOT/build/include/xtensa-elf/ \
-I$MAGPIE_ROOT/build/include";
export HPATH
+++ /dev/null
-/*
- * xtensa/config/core.h -- HAL definitions dependent on CORE configuration
- *
- * This header file is sometimes referred to as the "compile-time HAL" or CHAL.
- * It pulls definitions tailored for a specific Xtensa processor configuration.
- *
- * Sources for binaries meant to be configuration-independent generally avoid
- * including this file (they may use the configuration-specific HAL library).
- * It is normal for the HAL library source itself to include this file.
- */
-
-/*
- * Copyright (c) 2005-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
- * These coded instructions, statements, and computer programs are the
- * copyrighted works and confidential proprietary information of Tensilica Inc.
- * They may not be modified, copied, reproduced, distributed, or disclosed to
- * third parties in any manner, medium, or form, in whole or in part, without
- * the prior written consent of Tensilica Inc.
- */
-
-
-#ifndef XTENSA_CONFIG_CORE_H
-#define XTENSA_CONFIG_CORE_H
-
-/* CONFIGURATION INDEPENDENT DEFINITIONS: */
-#ifdef __XTENSA__
-#include <xtensa/hal.h>
-#else
-#include "../hal.h"
-#endif
-
-/* CONFIGURATION SPECIFIC DEFINITIONS: */
-#ifdef __XTENSA__
-#include <xtensa/config/core-isa.h>
-#include <xtensa/config/core-matmap.h>
-#include <xtensa/config/tie.h>
-#else
-#include "core-isa.h"
-#include "core-matmap.h"
-#include "tie.h"
-#endif
-
-#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
-#ifdef __XTENSA__
-#include <xtensa/config/tie-asm.h>
-#else
-#include "tie-asm.h"
-#endif
-#endif /*_ASMLANGUAGE or __ASSEMBLER__*/
-
-
-/*----------------------------------------------------------------------
- GENERAL
- ----------------------------------------------------------------------*/
-
-/*
- * Separators for macros that expand into arrays.
- * These can be predefined by files that #include this one,
- * when different separators are required.
- */
-/* Element separator for macros that expand into 1-dimensional arrays: */
-#ifndef XCHAL_SEP
-#define XCHAL_SEP ,
-#endif
-/* Array separator for macros that expand into 2-dimensional arrays: */
-#ifndef XCHAL_SEP2
-#define XCHAL_SEP2 },{
-#endif
-
-
-
-/*----------------------------------------------------------------------
- ISA
- ----------------------------------------------------------------------*/
-
-#if XCHAL_HAVE_BE
-# define XCHAL_HAVE_LE 0
-# define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN
-#else
-# define XCHAL_HAVE_LE 1
-# define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN
-#endif
-
-
-
-/*----------------------------------------------------------------------
- INTERRUPTS
- ----------------------------------------------------------------------*/
-
-/* Indexing macros: */
-#define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK
-#define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */
-#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
-#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
-#define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM
-#define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */
-#define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL
-#define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */
-#define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE
-#define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */
-#define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT
-#define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */
-
-
-#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
-#define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */
-#define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */
-/* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */
-
-/* These values are constant for existing Xtensa processor implementations: */
-#define XCHAL_INTLEVEL0_MASK 0x00000000
-#define XCHAL_INTLEVEL8_MASK 0x00000000
-#define XCHAL_INTLEVEL9_MASK 0x00000000
-#define XCHAL_INTLEVEL10_MASK 0x00000000
-#define XCHAL_INTLEVEL11_MASK 0x00000000
-#define XCHAL_INTLEVEL12_MASK 0x00000000
-#define XCHAL_INTLEVEL13_MASK 0x00000000
-#define XCHAL_INTLEVEL14_MASK 0x00000000
-#define XCHAL_INTLEVEL15_MASK 0x00000000
-
-/* Array of masks of interrupts at each interrupt level: */
-#define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \
- XCHAL_SEP XCHAL_INTLEVEL1_MASK \
- XCHAL_SEP XCHAL_INTLEVEL2_MASK \
- XCHAL_SEP XCHAL_INTLEVEL3_MASK \
- XCHAL_SEP XCHAL_INTLEVEL4_MASK \
- XCHAL_SEP XCHAL_INTLEVEL5_MASK \
- XCHAL_SEP XCHAL_INTLEVEL6_MASK \
- XCHAL_SEP XCHAL_INTLEVEL7_MASK \
- XCHAL_SEP XCHAL_INTLEVEL8_MASK \
- XCHAL_SEP XCHAL_INTLEVEL9_MASK \
- XCHAL_SEP XCHAL_INTLEVEL10_MASK \
- XCHAL_SEP XCHAL_INTLEVEL11_MASK \
- XCHAL_SEP XCHAL_INTLEVEL12_MASK \
- XCHAL_SEP XCHAL_INTLEVEL13_MASK \
- XCHAL_SEP XCHAL_INTLEVEL14_MASK \
- XCHAL_SEP XCHAL_INTLEVEL15_MASK
-
-/* These values are constant for existing Xtensa processor implementations: */
-#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
-#define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-
-/* Mask of all low-priority interrupts: */
-#define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK
-
-/* Mask of all interrupts masked by PS.EXCM (or CEXCM): */
-#define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL)
-
-/* Array of masks of interrupts at each range 1..n of interrupt levels: */
-#define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK
-
-#if 0 /*XCHAL_HAVE_NMI*/
-/* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */
-# define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1)
-#endif
-
-/* Array of levels of each possible interrupt: */
-#define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \
- XCHAL_SEP XCHAL_INT1_LEVEL \
- XCHAL_SEP XCHAL_INT2_LEVEL \
- XCHAL_SEP XCHAL_INT3_LEVEL \
- XCHAL_SEP XCHAL_INT4_LEVEL \
- XCHAL_SEP XCHAL_INT5_LEVEL \
- XCHAL_SEP XCHAL_INT6_LEVEL \
- XCHAL_SEP XCHAL_INT7_LEVEL \
- XCHAL_SEP XCHAL_INT8_LEVEL \
- XCHAL_SEP XCHAL_INT9_LEVEL \
- XCHAL_SEP XCHAL_INT10_LEVEL \
- XCHAL_SEP XCHAL_INT11_LEVEL \
- XCHAL_SEP XCHAL_INT12_LEVEL \
- XCHAL_SEP XCHAL_INT13_LEVEL \
- XCHAL_SEP XCHAL_INT14_LEVEL \
- XCHAL_SEP XCHAL_INT15_LEVEL \
- XCHAL_SEP XCHAL_INT16_LEVEL \
- XCHAL_SEP XCHAL_INT17_LEVEL \
- XCHAL_SEP XCHAL_INT18_LEVEL \
- XCHAL_SEP XCHAL_INT19_LEVEL \
- XCHAL_SEP XCHAL_INT20_LEVEL \
- XCHAL_SEP XCHAL_INT21_LEVEL \
- XCHAL_SEP XCHAL_INT22_LEVEL \
- XCHAL_SEP XCHAL_INT23_LEVEL \
- XCHAL_SEP XCHAL_INT24_LEVEL \
- XCHAL_SEP XCHAL_INT25_LEVEL \
- XCHAL_SEP XCHAL_INT26_LEVEL \
- XCHAL_SEP XCHAL_INT27_LEVEL \
- XCHAL_SEP XCHAL_INT28_LEVEL \
- XCHAL_SEP XCHAL_INT29_LEVEL \
- XCHAL_SEP XCHAL_INT30_LEVEL \
- XCHAL_SEP XCHAL_INT31_LEVEL
-
-/* Array of types of each possible interrupt: */
-#define XCHAL_INT_TYPES XCHAL_INT0_TYPE \
- XCHAL_SEP XCHAL_INT1_TYPE \
- XCHAL_SEP XCHAL_INT2_TYPE \
- XCHAL_SEP XCHAL_INT3_TYPE \
- XCHAL_SEP XCHAL_INT4_TYPE \
- XCHAL_SEP XCHAL_INT5_TYPE \
- XCHAL_SEP XCHAL_INT6_TYPE \
- XCHAL_SEP XCHAL_INT7_TYPE \
- XCHAL_SEP XCHAL_INT8_TYPE \
- XCHAL_SEP XCHAL_INT9_TYPE \
- XCHAL_SEP XCHAL_INT10_TYPE \
- XCHAL_SEP XCHAL_INT11_TYPE \
- XCHAL_SEP XCHAL_INT12_TYPE \
- XCHAL_SEP XCHAL_INT13_TYPE \
- XCHAL_SEP XCHAL_INT14_TYPE \
- XCHAL_SEP XCHAL_INT15_TYPE \
- XCHAL_SEP XCHAL_INT16_TYPE \
- XCHAL_SEP XCHAL_INT17_TYPE \
- XCHAL_SEP XCHAL_INT18_TYPE \
- XCHAL_SEP XCHAL_INT19_TYPE \
- XCHAL_SEP XCHAL_INT20_TYPE \
- XCHAL_SEP XCHAL_INT21_TYPE \
- XCHAL_SEP XCHAL_INT22_TYPE \
- XCHAL_SEP XCHAL_INT23_TYPE \
- XCHAL_SEP XCHAL_INT24_TYPE \
- XCHAL_SEP XCHAL_INT25_TYPE \
- XCHAL_SEP XCHAL_INT26_TYPE \
- XCHAL_SEP XCHAL_INT27_TYPE \
- XCHAL_SEP XCHAL_INT28_TYPE \
- XCHAL_SEP XCHAL_INT29_TYPE \
- XCHAL_SEP XCHAL_INT30_TYPE \
- XCHAL_SEP XCHAL_INT31_TYPE
-
-/* Array of masks of interrupts for each type of interrupt: */
-#define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \
- XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \
- XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \
- XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \
- XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \
- XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \
- XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR
-
-/* Interrupts that can be cleared using the INTCLEAR special register: */
-#define XCHAL_INTCLEARABLE_MASK (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR)
-/* Interrupts that can be triggered using the INTSET special register: */
-#define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE
-
-/* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */
-#define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \
- XCHAL_SEP XCHAL_TIMER1_INTERRUPT \
- XCHAL_SEP XCHAL_TIMER2_INTERRUPT \
- XCHAL_SEP XCHAL_TIMER3_INTERRUPT
-
-
-
-/* For backward compatibility and for the array macros, define macros for
- * each unconfigured interrupt number (unfortunately, the value of
- * XTHAL_INTTYPE_UNCONFIGURED is not zero): */
-#if XCHAL_NUM_INTERRUPTS == 0
-# define XCHAL_INT0_LEVEL 0
-# define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 1
-# define XCHAL_INT1_LEVEL 0
-# define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 2
-# define XCHAL_INT2_LEVEL 0
-# define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 3
-# define XCHAL_INT3_LEVEL 0
-# define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 4
-# define XCHAL_INT4_LEVEL 0
-# define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 5
-# define XCHAL_INT5_LEVEL 0
-# define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 6
-# define XCHAL_INT6_LEVEL 0
-# define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 7
-# define XCHAL_INT7_LEVEL 0
-# define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 8
-# define XCHAL_INT8_LEVEL 0
-# define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 9
-# define XCHAL_INT9_LEVEL 0
-# define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 10
-# define XCHAL_INT10_LEVEL 0
-# define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 11
-# define XCHAL_INT11_LEVEL 0
-# define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 12
-# define XCHAL_INT12_LEVEL 0
-# define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 13
-# define XCHAL_INT13_LEVEL 0
-# define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 14
-# define XCHAL_INT14_LEVEL 0
-# define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 15
-# define XCHAL_INT15_LEVEL 0
-# define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 16
-# define XCHAL_INT16_LEVEL 0
-# define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 17
-# define XCHAL_INT17_LEVEL 0
-# define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 18
-# define XCHAL_INT18_LEVEL 0
-# define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 19
-# define XCHAL_INT19_LEVEL 0
-# define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 20
-# define XCHAL_INT20_LEVEL 0
-# define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 21
-# define XCHAL_INT21_LEVEL 0
-# define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 22
-# define XCHAL_INT22_LEVEL 0
-# define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 23
-# define XCHAL_INT23_LEVEL 0
-# define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 24
-# define XCHAL_INT24_LEVEL 0
-# define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 25
-# define XCHAL_INT25_LEVEL 0
-# define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 26
-# define XCHAL_INT26_LEVEL 0
-# define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 27
-# define XCHAL_INT27_LEVEL 0
-# define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 28
-# define XCHAL_INT28_LEVEL 0
-# define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 29
-# define XCHAL_INT29_LEVEL 0
-# define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 30
-# define XCHAL_INT30_LEVEL 0
-# define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 31
-# define XCHAL_INT31_LEVEL 0
-# define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-
-
-/*
- * Masks and levels corresponding to each *external* interrupt.
- */
-
-#define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM)
-#define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM)
-#define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM)
-#define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM)
-#define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM)
-#define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM)
-#define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM)
-#define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM)
-#define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM)
-#define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM)
-#define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM)
-#define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM)
-#define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM)
-#define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM)
-#define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM)
-#define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM)
-#define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM)
-#define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM)
-#define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM)
-#define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM)
-#define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM)
-#define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM)
-#define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM)
-#define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM)
-#define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM)
-#define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM)
-#define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM)
-#define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM)
-#define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM)
-#define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM)
-#define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM)
-#define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM)
-#define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM)
-#define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM)
-#define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM)
-#define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM)
-#define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM)
-#define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM)
-#define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM)
-#define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM)
-#define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM)
-#define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM)
-#define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM)
-#define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM)
-#define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM)
-#define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM)
-#define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM)
-#define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM)
-#define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM)
-#define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM)
-#define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM)
-#define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM)
-#define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM)
-#define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM)
-#define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM)
-#define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM)
-#define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM)
-#define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM)
-#define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM)
-#define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM)
-#define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM)
-#define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM)
-#define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM)
-#define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM)
-
-
-/*----------------------------------------------------------------------
- EXCEPTIONS and VECTORS
- ----------------------------------------------------------------------*/
-
-/* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */
-#define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
-#define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
-#ifdef XCHAL_USER_VECTOR_VADDR
-#define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR
-#define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR
-#endif
-#ifdef XCHAL_USER_VECTOR_PADDR
-# define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR
-# define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR
-#endif
-#ifdef XCHAL_KERNEL_VECTOR_VADDR
-# define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR
-# define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR
-#endif
-#ifdef XCHAL_KERNEL_VECTOR_PADDR
-# define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR
-# define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR
-#endif
-
-#if 0
-#if XCHAL_HAVE_DEBUG
-# define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL)
-/* This one should only get defined if the corresponding intlevel paddr macro exists: */
-# define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL)
-#endif
-#endif
-
-/* Indexing macros: */
-#define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
-#define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */
-
-/*
- * General Exception Causes
- * (values of EXCCAUSE special register set by general exceptions,
- * which vector to the user, kernel, or double-exception vectors).
- *
- * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros
- * defined in <xtensa/corebits.h>. (Note that these have slightly
- * different names, they don't just have the XCHAL_ prefix removed.)
- */
-#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */
-#define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */
-#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */
-#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
-#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
-#define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */
-#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
-#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */
-#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
-#define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */
-/*10..15 reserved*/
-#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */
-#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */
-#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */
-#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */
-#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */
-/*21..23 reserved*/
-#define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */
-#define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */
-#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */
-#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */
-#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */
-#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */
-/*30..31 reserved*/
-#define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */
-#define XCHAL_EXCCAUSE_FLOATING_POINT 40 /* Floating Point Exception */
-/*40..63 reserved*/
-
-
-/*
- * Miscellaneous special register fields.
- *
- * For each special register, and each field within each register:
- * XCHAL_<regname>_VALIDMASK is the set of bits defined in the register.
- * XCHAL_<regname>_<field>_BITS is the number of bits in the field.
- * XCHAL_<regname>_<field>_NUM is 2^bits, the number of possible values
- * of the field.
- * XCHAL_<regname>_<field>_SHIFT is the position of the field within
- * the register, starting from the least significant bit.
- *
- * DEPRECATED. Please use the equivalent macros defined in
- * <xtensa/corebits.h>. (Note that these have different names.)
- */
-
-/* DBREAKC (special register number 160): */
-#define XCHAL_DBREAKC_VALIDMASK 0xC000003F
-#define XCHAL_DBREAKC_MASK_BITS 6
-#define XCHAL_DBREAKC_MASK_NUM 64
-#define XCHAL_DBREAKC_MASK_SHIFT 0
-#define XCHAL_DBREAKC_MASK_MASK 0x0000003F
-#define XCHAL_DBREAKC_LOADBREAK_BITS 1
-#define XCHAL_DBREAKC_LOADBREAK_NUM 2
-#define XCHAL_DBREAKC_LOADBREAK_SHIFT 30
-#define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000
-#define XCHAL_DBREAKC_STOREBREAK_BITS 1
-#define XCHAL_DBREAKC_STOREBREAK_NUM 2
-#define XCHAL_DBREAKC_STOREBREAK_SHIFT 31
-#define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000
-/* PS (special register number 230): */
-#define XCHAL_PS_VALIDMASK 0x00070F3F
-#define XCHAL_PS_INTLEVEL_BITS 4
-#define XCHAL_PS_INTLEVEL_NUM 16
-#define XCHAL_PS_INTLEVEL_SHIFT 0
-#define XCHAL_PS_INTLEVEL_MASK 0x0000000F
-#define XCHAL_PS_EXCM_BITS 1
-#define XCHAL_PS_EXCM_NUM 2
-#define XCHAL_PS_EXCM_SHIFT 4
-#define XCHAL_PS_EXCM_MASK 0x00000010
-#define XCHAL_PS_UM_BITS 1
-#define XCHAL_PS_UM_NUM 2
-#define XCHAL_PS_UM_SHIFT 5
-#define XCHAL_PS_UM_MASK 0x00000020
-#define XCHAL_PS_RING_BITS 2
-#define XCHAL_PS_RING_NUM 4
-#define XCHAL_PS_RING_SHIFT 6
-#define XCHAL_PS_RING_MASK 0x000000C0
-#define XCHAL_PS_OWB_BITS 4
-#define XCHAL_PS_OWB_NUM 16
-#define XCHAL_PS_OWB_SHIFT 8
-#define XCHAL_PS_OWB_MASK 0x00000F00
-#define XCHAL_PS_CALLINC_BITS 2
-#define XCHAL_PS_CALLINC_NUM 4
-#define XCHAL_PS_CALLINC_SHIFT 16
-#define XCHAL_PS_CALLINC_MASK 0x00030000
-#define XCHAL_PS_WOE_BITS 1
-#define XCHAL_PS_WOE_NUM 2
-#define XCHAL_PS_WOE_SHIFT 18
-#define XCHAL_PS_WOE_MASK 0x00040000
-/* EXCCAUSE (special register number 232): */
-#define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F
-#define XCHAL_EXCCAUSE_BITS 6
-#define XCHAL_EXCCAUSE_NUM 64
-#define XCHAL_EXCCAUSE_SHIFT 0
-#define XCHAL_EXCCAUSE_MASK 0x0000003F
-/* DEBUGCAUSE (special register number 233): */
-#define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F
-#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1
-#define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2
-#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0
-#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001
-#define XCHAL_DEBUGCAUSE_IBREAK_BITS 1
-#define XCHAL_DEBUGCAUSE_IBREAK_NUM 2
-#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1
-#define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002
-#define XCHAL_DEBUGCAUSE_DBREAK_BITS 1
-#define XCHAL_DEBUGCAUSE_DBREAK_NUM 2
-#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2
-#define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004
-#define XCHAL_DEBUGCAUSE_BREAK_BITS 1
-#define XCHAL_DEBUGCAUSE_BREAK_NUM 2
-#define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3
-#define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008
-#define XCHAL_DEBUGCAUSE_BREAKN_BITS 1
-#define XCHAL_DEBUGCAUSE_BREAKN_NUM 2
-#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4
-#define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010
-#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1
-#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2
-#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5
-#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020
-
-
-
-
-/*----------------------------------------------------------------------
- TIMERS
- ----------------------------------------------------------------------*/
-
-/*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/
-
-
-
-/*----------------------------------------------------------------------
- INTERNAL I/D RAM/ROMs and XLMI
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
-#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
-#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */
-#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
-
-#define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */
-#define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */
-#define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */
-#define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */
-#define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */
-#define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */
-#define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */
-#define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */
-#define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */
-#define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */
-#define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */
-#define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */
-#define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */
-#define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */
-#define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */
-#define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */
-#define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */
-#define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */
-#define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */
-#define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */
-#define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */
-#define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */
-#define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */
-#define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */
-
-
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-
-/* Max for both I-cache and D-cache (used for general alignment): */
-#if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE
-# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH
-# define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE
-#else
-# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH
-# define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE
-#endif
-
-#define XCHAL_ICACHE_SETSIZE (1<<XCHAL_ICACHE_SETWIDTH)
-#define XCHAL_DCACHE_SETSIZE (1<<XCHAL_DCACHE_SETWIDTH)
-/* Max for both I and D caches (used for cache-coherency page alignment): */
-#if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH
-# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH
-# define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE
-#else
-# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH
-# define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE
-#endif
-
-/* Instruction cache tag bits: */
-#define XCHAL_ICACHE_TAG_V_SHIFT 0
-#define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */
-#if XCHAL_ICACHE_WAYS > 1
-# define XCHAL_ICACHE_TAG_F_SHIFT 1
-# define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */
-#else
-# define XCHAL_ICACHE_TAG_F_SHIFT 0
-# define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */
-#endif
-#if XCHAL_ICACHE_LINE_LOCKABLE
-# define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1)
-# define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* lock bit */
-#else
-# define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT
-# define XCHAL_ICACHE_TAG_L 0 /* no lock bit */
-#endif
-/* Data cache tag bits: */
-#define XCHAL_DCACHE_TAG_V_SHIFT 0
-#define XCHAL_DCACHE_TAG_V 0x1 /* valid bit */
-#if XCHAL_DCACHE_WAYS > 1
-# define XCHAL_DCACHE_TAG_F_SHIFT 1
-# define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */
-#else
-# define XCHAL_DCACHE_TAG_F_SHIFT 0
-# define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */
-#endif
-#if XCHAL_DCACHE_IS_WRITEBACK
-# define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1)
-# define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* dirty bit */
-#else
-# define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT
-# define XCHAL_DCACHE_TAG_D 0 /* no dirty bit */
-#endif
-#if XCHAL_DCACHE_LINE_LOCKABLE
-# define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1)
-# define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* lock bit */
-#else
-# define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT
-# define XCHAL_DCACHE_TAG_L 0 /* no lock bit */
-#endif
-
-
-/*----------------------------------------------------------------------
- MMU
- ----------------------------------------------------------------------*/
-
-/* See <xtensa/config/core-matmap.h> for more details. */
-
-#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */
-
-/* Indexing macros: */
-#define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what
-#define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what )
-#define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what
-#define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what )
-#define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what
-#define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what )
-#define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what
-#define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what )
-/*
- * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
- * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
- */
-
-/* Number of entries per autorefill way: */
-#define XCHAL_ITLB_ARF_ENTRIES (1<<XCHAL_ITLB_ARF_ENTRIES_LOG2)
-#define XCHAL_DTLB_ARF_ENTRIES (1<<XCHAL_DTLB_ARF_ENTRIES_LOG2)
-
-/*
- * Determine whether we have a full MMU (with Page Table and Protection)
- * usable for an MMU-based OS:
- */
-#if 0
-#if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
-# define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */
-#else
-# define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */
-#endif
-#endif
-
-/*
- * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
- */
-#if XCHAL_HAVE_PTP_MMU
-#define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */
-#define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */
-#define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */
-#define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */
-#define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */
-#define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */
-
-#define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */
-#define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */
-#define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */
-#define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */
-#define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */
-#define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */
-
-#define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */
-#define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */
-/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */
-#endif
-
-
-/*----------------------------------------------------------------------
- MISC
- ----------------------------------------------------------------------*/
-
-/* Data alignment required if used for instructions: */
-#if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH
-# define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH
-#else
-# define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH
-#endif
-
-/*
- * Names kept for backward compatibility.
- * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
- * under which they are released. In the T10##.# era there was no distinction.)
- */
-#define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR
-#define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR
-#define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME
-
-
-
-
-/*----------------------------------------------------------------------
- COPROCESSORS and EXTRA STATE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE
-#define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN
-#define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE
-#define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN
-
-#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
-
-#define xchal_extratie_load xchal_ncptie_load
-#define xchal_extratie_store xchal_ncptie_store
-#define xchal_extratie_load_a2 xchal_ncptie_load_a2
-#define xchal_extratie_store_a2 xchal_ncptie_store_a2
-#define xchal_extra_load xchal_ncp_load
-#define xchal_extra_store xchal_ncp_store
-#define xchal_extra_load_a2 xchal_ncp_load_a2
-#define xchal_extra_store_a2 xchal_ncp_store_a2
-#define xchal_extra_load_funcbody xchal_ncp_load_a2
-#define xchal_extra_store_funcbody xchal_ncp_store_a2
-
-/* Empty placeholder macros for undefined coprocessors: */
-# ifndef XCHAL_CP0_NAME
-# define xchal_cp0_store_a2 xchal_cp0_store a2, a3
-# define xchal_cp0_load_a2 xchal_cp0_load a2, a3
- .macro xchal_cp0_store ptr tmp
- .endm
- .macro xchal_cp0_load ptr tmp
- .endm
-# endif
-# ifndef XCHAL_CP1_NAME
-# define xchal_cp1_store_a2 xchal_cp1_store a2, a3
-# define xchal_cp1_load_a2 xchal_cp1_load a2, a3
- .macro xchal_cp1_store ptr tmp
- .endm
- .macro xchal_cp1_load ptr tmp
- .endm
-# endif
-# ifndef XCHAL_CP2_NAME
-# define xchal_cp2_store_a2 xchal_cp2_store a2, a3
-# define xchal_cp2_load_a2 xchal_cp2_load a2, a3
- .macro xchal_cp2_store ptr tmp
- .endm
- .macro xchal_cp2_load ptr tmp
- .endm
-# endif
-# ifndef XCHAL_CP3_NAME
-# define xchal_cp3_store_a2 xchal_cp3_store a2, a3
-# define xchal_cp3_load_a2 xchal_cp3_load a2, a3
- .macro xchal_cp3_store ptr tmp
- .endm
- .macro xchal_cp3_load ptr tmp
- .endm
-# endif
-# ifndef XCHAL_CP4_NAME
-# define xchal_cp4_store_a2 xchal_cp4_store a2, a3
-# define xchal_cp4_load_a2 xchal_cp4_load a2, a3
- .macro xchal_cp4_store ptr tmp
- .endm
- .macro xchal_cp4_load ptr tmp
- .endm
-# endif
-# ifndef XCHAL_CP5_NAME
-# define xchal_cp5_store_a2 xchal_cp5_store a2, a3
-# define xchal_cp5_load_a2 xchal_cp5_load a2, a3
- .macro xchal_cp5_store ptr tmp
- .endm
- .macro xchal_cp5_load ptr tmp
- .endm
-# endif
-# ifndef XCHAL_CP6_NAME
-# define xchal_cp6_store_a2 xchal_cp6_store a2, a3
-# define xchal_cp6_load_a2 xchal_cp6_load a2, a3
- .macro xchal_cp6_store ptr tmp
- .endm
- .macro xchal_cp6_load ptr tmp
- .endm
-# endif
-# ifndef XCHAL_CP7_NAME
-# define xchal_cp7_store_a2 xchal_cp7_store a2, a3
-# define xchal_cp7_load_a2 xchal_cp7_load a2, a3
- .macro xchal_cp7_store ptr tmp
- .endm
- .macro xchal_cp7_load ptr tmp
- .endm
-# endif
-
- /********************
- * Macros to create functions that save and restore the state of *any* TIE
- * coprocessor (by dynamic index).
- */
-
- /*
- * Macro that expands to the body of a function
- * that stores the selected coprocessor's state (registers etc).
- * Entry: a2 = ptr to save area in which to save cp state
- * a3 = coprocessor number
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_cpi_store_funcbody
-# ifdef XCHAL_CP0_NAME
- bnez a3, 99f
- xchal_cp0_store_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP1_NAME
- bnei a3, 1, 99f
- xchal_cp1_store_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP2_NAME
- bnei a3, 2, 99f
- xchal_cp2_store_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP3_NAME
- bnei a3, 3, 99f
- xchal_cp3_store_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP4_NAME
- bnei a3, 4, 99f
- xchal_cp4_store_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP5_NAME
- bnei a3, 5, 99f
- xchal_cp5_store_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP6_NAME
- bnei a3, 6, 99f
- xchal_cp6_store_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP7_NAME
- bnei a3, 7, 99f
- xchal_cp7_store_a2
- j 90f
-99:
-# endif
-90:
- .endm
-
- /*
- * Macro that expands to the body of a function
- * that loads the selected coprocessor's state (registers etc).
- * Entry: a2 = ptr to save area from which to restore cp state
- * a3 = coprocessor number
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_cpi_load_funcbody
-# ifdef XCHAL_CP0_NAME
- bnez a3, 99f
- xchal_cp0_load_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP1_NAME
- bnei a3, 1, 99f
- xchal_cp1_load_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP2_NAME
- bnei a3, 2, 99f
- xchal_cp2_load_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP3_NAME
- bnei a3, 3, 99f
- xchal_cp3_load_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP4_NAME
- bnei a3, 4, 99f
- xchal_cp4_load_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP5_NAME
- bnei a3, 5, 99f
- xchal_cp5_load_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP6_NAME
- bnei a3, 6, 99f
- xchal_cp6_load_a2
- j 90f
-99:
-# endif
-# ifdef XCHAL_CP7_NAME
- bnei a3, 7, 99f
- xchal_cp7_load_a2
- j 90f
-99:
-# endif
-90:
- .endm
-
-#endif /*_ASMLANGUAGE or __ASSEMBLER__*/
-
-
-/* Other default macros for undefined coprocessors: */
-#ifndef XCHAL_CP0_NAME
-# define XCHAL_CP0_SA_SIZE 0
-# define XCHAL_CP0_SA_ALIGN 1
-# define XCHAL_CP0_NAME 0
-# define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP1_NAME
-# define XCHAL_CP1_SA_SIZE 0
-# define XCHAL_CP1_SA_ALIGN 1
-# define XCHAL_CP1_NAME 0
-# define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP2_NAME
-# define XCHAL_CP2_SA_SIZE 0
-# define XCHAL_CP2_SA_ALIGN 1
-# define XCHAL_CP2_NAME 0
-# define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP3_NAME
-# define XCHAL_CP3_SA_SIZE 0
-# define XCHAL_CP3_SA_ALIGN 1
-# define XCHAL_CP3_NAME 0
-# define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP4_NAME
-# define XCHAL_CP4_SA_SIZE 0
-# define XCHAL_CP4_SA_ALIGN 1
-# define XCHAL_CP4_NAME 0
-# define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP5_NAME
-# define XCHAL_CP5_SA_SIZE 0
-# define XCHAL_CP5_SA_ALIGN 1
-# define XCHAL_CP5_NAME 0
-# define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP6_NAME
-# define XCHAL_CP6_SA_SIZE 0
-# define XCHAL_CP6_SA_ALIGN 1
-# define XCHAL_CP6_NAME 0
-# define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP7_NAME
-# define XCHAL_CP7_SA_SIZE 0
-# define XCHAL_CP7_SA_ALIGN 1
-# define XCHAL_CP7_NAME 0
-# define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
-#endif
-
-/* Indexing macros: */
-#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
-#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
-#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
-#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
-
-#define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */
-
-/* Link-time HAL global variables that report coprocessor numbers by name
- (names are case-preserved from the original TIE): */
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-# define _XCJOIN(a,b) a ## b
-# define XCJOIN(a,b) _XCJOIN(a,b)
-# ifdef XCHAL_CP0_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT);
-# endif
-# ifdef XCHAL_CP1_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT);
-# endif
-# ifdef XCHAL_CP2_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT);
-# endif
-# ifdef XCHAL_CP3_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT);
-# endif
-# ifdef XCHAL_CP4_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT);
-# endif
-# ifdef XCHAL_CP5_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT);
-# endif
-# ifdef XCHAL_CP6_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT);
-# endif
-# ifdef XCHAL_CP7_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT);
-# endif
-#endif
-
-
-
-
-/*----------------------------------------------------------------------
- DERIVED
- ----------------------------------------------------------------------*/
-
-#if XCHAL_HAVE_BE
-#define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */
-#define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */
-#define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */
-#else
-#define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */
-#define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */
-#define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */
-#endif
-/* Belongs in xtensa/hal.h: */
-#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
-
-
-/*
- * Because information as to exactly which hardware version is targeted
- * by a given software build is not always available, compile-time HAL
- * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
- * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
- * under which they are released. In the T10##.# era there was no distinction.)
- */
-#if XCHAL_HW_CONFIGID_RELIABLE
-# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
-# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
-# define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
-# define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0)
-#else
-# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
- : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
- : XTHAL_MAYBE )
-# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
- : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
- : XTHAL_MAYBE )
-# define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
- ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
-# define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0)
-#endif
-
-/*
- * Specific errata:
- */
-
-/*
- * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
- * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
- */
-#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \
- (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
- || XCHAL_HW_RELEASE_AT(1050,0)))
-
-
-
-#endif /*XTENSA_CONFIG_CORE_H*/
+++ /dev/null
-/*
- * xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
- *
- * (In previous releases, these were defined in specreg.h, a generated file.
- * This file is not generated, ie. it is processor configuration independent.)
- */
-
-/* $Id: //depot/rel/BadgerPass/Xtensa/OS/include/xtensa/corebits.h#3 $ */
-
-/*
- * Copyright (c) 2005-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
- * These coded instructions, statements, and computer programs are the
- * copyrighted works and confidential proprietary information of Tensilica Inc.
- * They may not be modified, copied, reproduced, distributed, or disclosed to
- * third parties in any manner, medium, or form, in whole or in part, without
- * the prior written consent of Tensilica Inc.
- */
-
-#ifndef XTENSA_COREBITS_H
-#define XTENSA_COREBITS_H
-
-/* EXCCAUSE register fields: */
-#define EXCCAUSE_EXCCAUSE_SHIFT 0
-#define EXCCAUSE_EXCCAUSE_MASK 0x3F
-/* EXCCAUSE register values: */
-/*
- * General Exception Causes
- * (values of EXCCAUSE special register set by general exceptions,
- * which vector to the user, kernel, or double-exception vectors).
- */
-#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
-#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
-#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
-# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
-#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
-# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
-#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
-# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
-#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
-#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
-#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
-#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
-#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
-/* Reserved 10..11 */
-#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
-#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
-#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
-#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
-#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
-#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
-#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
-/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
-#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
-/* Reserved 21..23 */
-#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
-#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
-#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
-/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
-#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
-#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
-/* Reserved 30..31 */
-#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
-#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
-#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
-#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
-#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
-#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
-#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
-#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
-#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
-/*#define EXCCAUSE_FLOATING_POINT 40*/ /* Floating Point Exception (not implemented) */
-/* Reserved 40..63 */
-
-/* PS register fields: */
-#define PS_WOE_SHIFT 18
-#define PS_WOE_MASK 0x00040000
-#define PS_WOE PS_WOE_MASK
-#define PS_CALLINC_SHIFT 16
-#define PS_CALLINC_MASK 0x00030000
-#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
-#define PS_OWB_SHIFT 8
-#define PS_OWB_MASK 0x00000F00
-#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
-#define PS_RING_SHIFT 6
-#define PS_RING_MASK 0x000000C0
-#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
-#define PS_UM_SHIFT 5
-#define PS_UM_MASK 0x00000020
-#define PS_UM PS_UM_MASK
-#define PS_EXCM_SHIFT 4
-#define PS_EXCM_MASK 0x00000010
-#define PS_EXCM PS_EXCM_MASK
-#define PS_INTLEVEL_SHIFT 0
-#define PS_INTLEVEL_MASK 0x0000000F
-#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
-/* Backward compatibility (deprecated): */
-#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
-#define PS_PROGSTACK_MASK PS_UM_MASK
-#define PS_PROG_SHIFT PS_UM_SHIFT
-#define PS_PROG_MASK PS_UM_MASK
-#define PS_PROG PS_UM
-
-/* DBREAKCn register fields: */
-#define DBREAKC_MASK_SHIFT 0
-#define DBREAKC_MASK_MASK 0x0000003F
-#define DBREAKC_LOADBREAK_SHIFT 30
-#define DBREAKC_LOADBREAK_MASK 0x40000000
-#define DBREAKC_STOREBREAK_SHIFT 31
-#define DBREAKC_STOREBREAK_MASK 0x80000000
-
-/* DEBUGCAUSE register fields: */
-#define DEBUGCAUSE_DEBUGINT_SHIFT 5
-#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
-#define DEBUGCAUSE_BREAKN_SHIFT 4
-#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
-#define DEBUGCAUSE_BREAK_SHIFT 3
-#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
-#define DEBUGCAUSE_DBREAK_SHIFT 2
-#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
-#define DEBUGCAUSE_IBREAK_SHIFT 1
-#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
-#define DEBUGCAUSE_ICOUNT_SHIFT 0
-#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
-
-/* MESR register fields: */
-#define MESR_MEME 0x00000001 /* memory error */
-#define MESR_MEME_SHIFT 0
-#define MESR_DME 0x00000002 /* double memory error */
-#define MESR_DME_SHIFT 1
-#define MESR_RCE 0x00000010 /* recorded memory error */
-#define MESR_RCE_SHIFT 4
-#define MESR_LCE
-#define MESR_LCE_SHIFT ?
-#define MESR_LCE_L
-#define MESR_ERRENAB 0x00000100
-#define MESR_ERRENAB_SHIFT 8
-#define MESR_ERRTEST 0x00000200
-#define MESR_ERRTEST_SHIFT 9
-#define MESR_DATEXC 0x00000400
-#define MESR_DATEXC_SHIFT 10
-#define MESR_INSEXC 0x00000800
-#define MESR_INSEXC_SHIFT 11
-#define MESR_WAYNUM_SHIFT 16
-#define MESR_ACCTYPE_SHIFT 20
-#define MESR_MEMTYPE_SHIFT 24
-#define MESR_ERRTYPE_SHIFT 30
-
-
-#endif /*XTENSA_COREBITS_H*/
+++ /dev/null
-/*
- xtensa/hal.h -- contains a definition of the Core HAL interface
-
- All definitions in this header file are independent of any specific
- Xtensa processor configuration. Thus software (eg. OS, application,
- etc) can include this header file and be compiled into configuration-
- independent objects that can be distributed and eventually linked
- to the HAL library (libhal.a) to create a configuration-specific
- final executable.
-
- Certain definitions, however, are release/version-specific -- such as
- the XTHAL_RELEASE_xxx macros (or additions made in later versions).
-
-
- $Id: //depot/rel/BadgerPass/Xtensa/OS/target-os-src/hal.h.tpp#2 $
-
- Copyright (c) 1999-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
- These coded instructions, statements, and computer programs are the
- copyrighted works and confidential proprietary information of Tensilica Inc.
- They may not be modified, copied, reproduced, distributed, or disclosed to
- third parties in any manner, medium, or form, in whole or in part, without
- the prior written consent of Tensilica Inc.
-*/
-
-#ifndef XTENSA_HAL_H
-#define XTENSA_HAL_H
-
-
-/****************************************************************************
- Definitions Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-
-/*----------------------------------------------------------------------
- Constant Definitions (shared with assembly)
- ----------------------------------------------------------------------*/
-
-/*
- * Software (Xtensa Tools) version information. Not configuration-specific!
- *
- * NOTE: "release" is a misnomer here, these are really product "version"
- * numbers. A "release" is a collection of product versions
- * made available at once (together) to customers.
- * In the past, release and version names all matched in T####.# form,
- * making the distinction irrelevant. This is no longer the case.
- */
-#define XTHAL_RELEASE_MAJOR 7010
-#define XTHAL_RELEASE_MINOR 0
-#define XTHAL_RELEASE_NAME "7.1.0"
-#define XTHAL_REL_7 1
-#define XTHAL_REL_7_1 1
-#define XTHAL_REL_7_1_0 1
-
-/* HAL version numbers (these names are for backward compatibility): */
-#define XTHAL_MAJOR_REV XTHAL_RELEASE_MAJOR
-#define XTHAL_MINOR_REV XTHAL_RELEASE_MINOR
-/*
- * A bit of software release/version history on values of XTHAL_{MAJOR,MINOR}_REV:
- *
- * SW Version MAJOR MINOR Comment
- * ======= ===== ===== =======
- * T1015.n n/a n/a (HAL not yet available)
- * T1020.{0,1,2} 0 1 (HAL beta)
- * T1020.{3,4} 0 2 First release.
- * T1020.n (n>4) 0 2 or >3 (TBD)
- * T1030.0 0 1 (HAL beta)
- * T1030.{1,2} 0 3 Equivalent to first release.
- * T1030.n (n>=3) 0 >= 3 (TBD)
- * T1040.n 1040 n Full CHAL available from T1040.2
- * T1050.n 1050 n .
- * 6.0.n 6000 n Xtensa Tools v6 (RA-200x.n)
- * 7.0.n 7000 n Xtensa Tools v7 (RB-200x.n)
- * 7.1.n 7010 n Xtensa Tools v7.1 (RB-200x.(n+2))
- *
- *
- * Note: there is a distinction between the software version with
- * which something is compiled (accessible using XTHAL_RELEASE_* macros)
- * and the software version with which the HAL library was compiled
- * (accessible using Xthal_release_* global variables). This
- * distinction is particularly relevant for vendors that distribute
- * configuration-independent binaries (eg. an OS), where their customer
- * might link it with a HAL of a different Xtensa software version.
- * In this case, it may be appropriate for the OS to verify at run-time
- * whether XTHAL_RELEASE_* and Xthal_release_* are compatible.
- * [Guidelines as to which version is compatible with which are not
- * currently provided explicitly, but might be inferred from reading
- * OSKit documentation for all releases -- compatibility is also highly
- * dependent on which HAL features are used. Each version is usually
- * backward compatible, with very few exceptions if any.]
- *
- * Notes:
- * Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only.
- * Tornado 2.0.2 supported in T1040.2+, T1050, and 6.0.
- * Compile-time HAL port of NucleusPlus supported by T1040.2 and later.
- */
-
-/* Version comparison operators (among major/minor pairs): */
-#define XTHAL_REL_GE(maja,mina, majb,minb) ((maja) > (majb) || \
- ((maja) == (majb) && (mina) >= (minb)))
-#define XTHAL_REL_GT(maja,mina, majb,minb) ((maja) > (majb) || \
- ((maja) == (majb) && (mina) > (minb)))
-#define XTHAL_REL_LE(maja,mina, majb,minb) ((maja) < (majb) || \
- ((maja) == (majb) && (mina) <= (minb)))
-#define XTHAL_REL_LT(maja,mina, majb,minb) ((maja) < (majb) || \
- ((maja) == (majb) && (mina) < (minb)))
-#define XTHAL_REL_EQ(maja,mina, majb,minb) ((maja) == (majb) && (mina) == (minb))
-
-/* Fuzzy (3-way) logic operators: */
-#define XTHAL_MAYBE -1 /* 0=NO, 1=YES, -1=MAYBE */
-#define XTHAL_FUZZY_AND(a,b) (((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE)
-#define XTHAL_FUZZY_OR(a,b) (((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE)
-#define XTHAL_FUZZY_NOT(a) (((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE)
-
-
-/*
- * Architectural limit, independent of configuration:
- */
-#define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */
-
-/* Misc: */
-#define XTHAL_LITTLEENDIAN 0
-#define XTHAL_BIGENDIAN 1
-
-
-
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*----------------------------------------------------------------------
- HAL
- ----------------------------------------------------------------------*/
-
-/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */
-extern const unsigned int Xthal_rev_no;
-
-
-/*----------------------------------------------------------------------
- Optional/Custom Processor State
- ----------------------------------------------------------------------*/
-
-/* save & restore the extra processor state */
-extern void xthal_save_extra(void *base);
-extern void xthal_restore_extra(void *base);
-
-extern void xthal_save_cpregs(void *base, int);
-extern void xthal_restore_cpregs(void *base, int);
-/* versions specific to each coprocessor id */
-extern void xthal_save_cp0(void *base);
-extern void xthal_save_cp1(void *base);
-extern void xthal_save_cp2(void *base);
-extern void xthal_save_cp3(void *base);
-extern void xthal_save_cp4(void *base);
-extern void xthal_save_cp5(void *base);
-extern void xthal_save_cp6(void *base);
-extern void xthal_save_cp7(void *base);
-extern void xthal_restore_cp0(void *base);
-extern void xthal_restore_cp1(void *base);
-extern void xthal_restore_cp2(void *base);
-extern void xthal_restore_cp3(void *base);
-extern void xthal_restore_cp4(void *base);
-extern void xthal_restore_cp5(void *base);
-extern void xthal_restore_cp6(void *base);
-extern void xthal_restore_cp7(void *base);
-/* pointers to each of the functions above */
-extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS];
-extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS];
-/* similarly for non-windowed ABI (may be same or different) */
-extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS];
-extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS];
-
-/*extern void xthal_save_all_extra(void *base);*/
-/*extern void xthal_restore_all_extra(void *base);*/
-
-/* space for processor state */
-extern const unsigned int Xthal_extra_size;
-extern const unsigned int Xthal_extra_align;
-extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];
-extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];
-extern const unsigned int Xthal_all_extra_size;
-extern const unsigned int Xthal_all_extra_align;
-/* coprocessor names */
-extern const char * const Xthal_cp_names[XTHAL_MAX_CPS];
-
-/* initialize the extra processor */
-/*extern void xthal_init_extra(void);*/
-/* initialize the TIE coprocessor */
-/*extern void xthal_init_cp(int);*/
-
-/* initialize the extra processor */
-extern void xthal_init_mem_extra(void *);
-/* initialize the TIE coprocessor */
-extern void xthal_init_mem_cp(void *, int);
-
-/* the number of TIE coprocessors contiguous from zero (for Tor2) */
-extern const unsigned int Xthal_num_coprocessors;
-
-/* actual number of coprocessors */
-extern const unsigned char Xthal_cp_num;
-/* index of highest numbered coprocessor, plus one */
-extern const unsigned char Xthal_cp_max;
-/* index of highest allowed coprocessor number, per cfg, plus one */
-/*extern const unsigned char Xthal_cp_maxcfg;*/
-/* bitmask of which coprocessors are present */
-extern const unsigned int Xthal_cp_mask;
-
-/* read & write extra state register */
-/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/
-/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/
-
-/* read & write a TIE coprocessor register */
-/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/
-/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/
-
-/* return coprocessor number based on register */
-/*extern int xthal_which_cp(unsigned reg);*/
-
-
-/*----------------------------------------------------------------------
- Register Windows
- ----------------------------------------------------------------------*/
-
-/* number of registers in register window */
-extern const unsigned int Xthal_num_aregs;
-extern const unsigned char Xthal_num_aregs_log2;
-
-
-/*----------------------------------------------------------------------
- Cache
- ----------------------------------------------------------------------*/
-
-/* size of the cache lines in log2(bytes) */
-extern const unsigned char Xthal_icache_linewidth;
-extern const unsigned char Xthal_dcache_linewidth;
-/* size of the cache lines in bytes (2^linewidth) */
-extern const unsigned short Xthal_icache_linesize;
-extern const unsigned short Xthal_dcache_linesize;
-
-/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */
-extern const unsigned int Xthal_icache_size;
-extern const unsigned int Xthal_dcache_size;
-/* cache features */
-extern const unsigned char Xthal_dcache_is_writeback;
-
-/* invalidate the caches */
-extern void xthal_icache_region_invalidate( void *addr, unsigned size );
-extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
-extern void xthal_icache_line_invalidate(void *addr);
-extern void xthal_dcache_line_invalidate(void *addr);
-/* write dirty data back */
-extern void xthal_dcache_region_writeback( void *addr, unsigned size );
-extern void xthal_dcache_line_writeback(void *addr);
-/* write dirty data back and invalidate */
-extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
-extern void xthal_dcache_line_writeback_inv(void *addr);
-
-/* sync icache and memory */
-extern void xthal_icache_sync( void );
-/* sync dcache and memory */
-extern void xthal_dcache_sync( void );
-
-
-/*----------------------------------------------------------------------
- Debug
- ----------------------------------------------------------------------*/
-
-/* 1 if debug option configured, 0 if not: */
-extern const int Xthal_debug_configured;
-
-/* Set (plant) and remove software breakpoint, both synchronizing cache: */
-extern unsigned int xthal_set_soft_break(void *addr);
-extern void xthal_remove_soft_break(void *addr, unsigned int);
-
-
-/*----------------------------------------------------------------------
- Disassembler
- ----------------------------------------------------------------------*/
-
-/* Max expected size of the return buffer for a disassembled instruction (hint only): */
-#define XTHAL_DISASM_BUFSIZE 80
-
-/* Disassembly option bits for selecting what to return: */
-#define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */
-#define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */
-#define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */
-#define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */
-#define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */
-
-/* routine to get a string for the disassembled instruction */
-extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,
- char *buffer, unsigned buflen, unsigned options );
-
-/* routine to get the size of the next instruction. Returns 0 for
- illegal instruction */
-extern int xthal_disassemble_size( unsigned char *instr_buf );
-
-
-/*----------------------------------------------------------------------
- Instruction/Data RAM/ROM Access
- ----------------------------------------------------------------------*/
-
-extern void* xthal_memcpy(void *dst, const void *src, unsigned len);
-extern void* xthal_bcopy(const void *src, void *dst, unsigned len);
-
-
-/*----------------------------------------------------------------------
- MP Synchronization
- ----------------------------------------------------------------------*/
-
-extern int xthal_compare_and_set( int *addr, int test_val, int compare_val );
-
-/*extern const char Xthal_have_s32c1i;*/
-
-
-/*----------------------------------------------------------------------
- Miscellaneous
- ----------------------------------------------------------------------*/
-
-extern const unsigned int Xthal_release_major;
-extern const unsigned int Xthal_release_minor;
-extern const char * const Xthal_release_name;
-extern const char * const Xthal_release_internal;
-
-extern const unsigned char Xthal_memory_order;
-extern const unsigned char Xthal_have_windowed;
-extern const unsigned char Xthal_have_density;
-extern const unsigned char Xthal_have_booleans;
-extern const unsigned char Xthal_have_loops;
-extern const unsigned char Xthal_have_nsa;
-extern const unsigned char Xthal_have_minmax;
-extern const unsigned char Xthal_have_sext;
-extern const unsigned char Xthal_have_clamps;
-extern const unsigned char Xthal_have_mac16;
-extern const unsigned char Xthal_have_mul16;
-extern const unsigned char Xthal_have_fp;
-extern const unsigned char Xthal_have_speculation;
-extern const unsigned char Xthal_have_threadptr;
-
-extern const unsigned char Xthal_have_pif;
-extern const unsigned short Xthal_num_writebuffer_entries;
-
-extern const unsigned int Xthal_build_unique_id;
-/* Version info for hardware targeted by software upgrades: */
-extern const unsigned int Xthal_hw_configid0;
-extern const unsigned int Xthal_hw_configid1;
-extern const unsigned int Xthal_hw_release_major;
-extern const unsigned int Xthal_hw_release_minor;
-extern const char * const Xthal_hw_release_name;
-extern const char * const Xthal_hw_release_internal;
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
-
-
-
-
-
-/****************************************************************************
- Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
- Constant Definitions (shared with assembly)
- ----------------------------------------------------------------------*/
-
-/*
- * Architectural limits, independent of configuration.
- * Note that these are ISA-defined limits, not micro-architecture implementation
- * limits enforced by the Xtensa Processor Generator (which may be stricter than
- * these below).
- */
-#define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */
-#define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */
- /* (as of T1040, implementation limit is 7: 0..6) */
-#define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */
- /* (as of T1040, implementation limit is 3: 0..2) */
-
-/* Interrupt types: */
-#define XTHAL_INTTYPE_UNCONFIGURED 0
-#define XTHAL_INTTYPE_SOFTWARE 1
-#define XTHAL_INTTYPE_EXTERN_EDGE 2
-#define XTHAL_INTTYPE_EXTERN_LEVEL 3
-#define XTHAL_INTTYPE_TIMER 4
-#define XTHAL_INTTYPE_NMI 5
-#define XTHAL_INTTYPE_WRITE_ERROR 6
-#define XTHAL_MAX_INTTYPES 7 /* number of interrupt types */
-
-/* Timer related: */
-#define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */
-#define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */
-
-/* Local Memory ECC/Parity: */
-#define XTHAL_MEMEP_PARITY 1
-#define XTHAL_MEMEP_ECC 2
-/* Flags parameter to xthal_memep_inject_error(): */
-#define XTHAL_MEMEP_F_LOCAL 0 /* local memory (default) */
-#define XTHAL_MEMEP_F_DCACHE_DATA 4 /* data cache data */
-#define XTHAL_MEMEP_F_DCACHE_TAG 5 /* data cache tag */
-#define XTHAL_MEMEP_F_ICACHE_DATA 6 /* instruction cache data */
-#define XTHAL_MEMEP_F_ICACHE_TAG 7 /* instruction cache tag */
-#define XTHAL_MEMEP_F_CORRECTABLE 16 /* inject correctable error
- (default is non-corr.) */
-
-
-/* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */
-#define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none
- exception on any access (aka "illegal") */
-#define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI)
- [or H HC] way from tag match;
- [or U UC] (ISA: same except Isolate case) */
-#define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none
- [or F FI fill] refill cache on miss, way from LRU
- (ISA: Read/Write Miss Refill) */
-#define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT
- store immediately to memory (ISA: same) */
-#define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none
- use cache regardless of hit-vs-miss,
- way from vaddr (ISA: use-cache-on-miss+hit) */
-#define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G *
- non-speculative; spec/replay refs not permitted */
-#if 0
-#define XTHAL_AMB_COHERENT 6 /* 040 M MC ?ls: Mem/MP Coherent M
- on read, other CPU/bus-master may need to supply data;
- on write, maybe redirect to or flush other CPU dirty line; etc */
-#define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G *
- mem accesses cannot be out of order */
-#define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none
- allow combining/merging multiple writes
- (to same datapath data unit) into one
- (implied by writeback) */
-#define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none
- memory will not bus error (if it does,
- handle as fatal imprecise interrupt) */
-#define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none
- on refill, read line+1 into prefetch buffers */
-#define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none
- access one of N stream buffers */
-#endif /*0*/
-
-#define XTHAL_AM_EXCEPTION (1<<XTHAL_AMB_EXCEPTION)
-#define XTHAL_AM_HITCACHE (1<<XTHAL_AMB_HITCACHE)
-#define XTHAL_AM_ALLOCATE (1<<XTHAL_AMB_ALLOCATE)
-#define XTHAL_AM_WRITETHRU (1<<XTHAL_AMB_WRITETHRU)
-#define XTHAL_AM_ISOLATE (1<<XTHAL_AMB_ISOLATE)
-#define XTHAL_AM_GUARD (1<<XTHAL_AMB_GUARD)
-#if 0
-#define XTHAL_AM_ORDERED (1<<XTHAL_AMB_ORDERED)
-#define XTHAL_AM_FUSEWRITES (1<<XTHAL_AMB_FUSEWRITES)
-#define XTHAL_AM_COHERENT (1<<XTHAL_AMB_COHERENT)
-#define XTHAL_AM_TRUSTED (1<<XTHAL_AMB_TRUSTED)
-#define XTHAL_AM_PREFETCH (1<<XTHAL_AMB_PREFETCH)
-#define XTHAL_AM_STREAM (1<<XTHAL_AMB_STREAM)
-#endif /*0*/
-
-/*
- * Allowed Access Modes (bit combinations).
- *
- * Columns are:
- * "FOGIWACE"
- * Access mode bits (see XTHAL_AMB_xxx above).
- * <letter> = bit is set
- * '-' = bit is clear
- * '.' = bit is irrelevant / don't care, as follows:
- * E=1 makes all others irrelevant
- * W,F relevant only for stores
- * "2345"
- * Indicates which Xtensa releases support the corresponding
- * access mode. Releases for each character column are:
- * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1
- * 3 = T1020.2 and later: T1020.2+, T1030
- * 4 = T1040
- * 5 = T1050 (maybe), LX1, LX2, LX2.1
- * 7 = LX2.2
- * And the character column contents are:
- * <number> = support by release(s)
- * "." = unsupported by release(s)
- * "?" = support unknown
- */
- /* FOMGIWACE 23457 */
-/* For instruction fetch: */
-#define XTHAL_FAM_EXCEPTION 0x001 /* ........E 23457 exception */
-#define XTHAL_FAM_ISOLATE 0x012 /* .---I.-C- ..... isolate */
-#define XTHAL_FAM_BYPASS 0x000 /* .----.--- 23457 bypass */
-#define XTHAL_FAM_NACACHED 0x002 /* .----.-C- ..... cached no-allocate (frozen) */
-#define XTHAL_FAM_CACHED 0x006 /* .----.AC- 23457 cached */
-/* For data load: */
-#define XTHAL_LAM_EXCEPTION 0x001 /* ........E 23457 exception */
-#define XTHAL_LAM_ISOLATE 0x012 /* .---I.-C- 23457 isolate */
-#define XTHAL_LAM_BYPASS 0x000 /* .O---.--- 2.... bypass speculative */
-#define XTHAL_LAM_BYPASSG 0x020 /* .O-G-.--- .3457 bypass guarded */
-#define XTHAL_LAM_NACACHED 0x002 /* .O---.-C- 2.... cached no-allocate speculative */
-#define XTHAL_LAM_NACACHEDG 0x022 /* .O-G-.-C- .3457 cached no-allocate guarded */
-#define XTHAL_LAM_CACHED 0x006 /* .----.AC- 23457 cached speculative */
-#define XTHAL_LAM_CACHEDG 0x026 /* .?-G-.AC- ..... cached guarded */
-#define XTHAL_LAM_CACHEDM 0x046 /* .-M--.AC- ....7 cached MP-coherent (experimental) */
-/* For data store: */
-#define XTHAL_SAM_EXCEPTION 0x001 /* ........E 23457 exception */
-#define XTHAL_SAM_ISOLATE 0x032 /* .--GI--C- 23457 isolate */
-#define XTHAL_SAM_BYPASS 0x028 /* -O-G-W--- 23457 bypass */
-/*efine XTHAL_SAM_BYPASSF 0x028*/ /* F--G-W--- ..... bypass write-combined */
-#define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 23457 writethrough */
-/*efine XTHAL_SAM_WRITETHRUF 0x02A*/ /* F--G-W-C- ..... writethrough write-combined */
-#define XTHAL_SAM_WRITEALLOC 0x02E /* -O-G-WAC- ..... writethrough-allocate */
-/*efine XTHAL_SAM_WRITEALLOCF 0x02E*/ /* F--G-WAC- ..... writethrough-allocate write-combined */
-#define XTHAL_SAM_WRITEBACK 0x066 /* F-MG--AC- ...57 writeback (MP-coherent if configured) */
-
-#if 0
-/*
- Cache attribute encoding for CACHEATTR (per ISA):
- (Note: if this differs from ISA Ref Manual, ISA has precedence)
-
- Inst-fetches Loads Stores
- ------------- ------------ -------------
-0x0 FCA_EXCEPTION ?LCA_NACACHED_G* SCA_WRITETHRU "uncached" (cached no-allocate)
-0x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached
-0x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass
-0x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate
- or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
-0x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK write-back
- or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
-0x5..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved)
-0xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate
-0xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal
- * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)
-*/
-#endif /*0*/
-
-
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/*----------------------------------------------------------------------
- Register Windows
- ----------------------------------------------------------------------*/
-
-/* This spill any live register windows (other than the caller's):
- * (NOTE: current implementation require privileged code, but
- * a user-callable implementation is possible.) */
-extern void xthal_window_spill( void );
-
-
-/*----------------------------------------------------------------------
- Optional/Custom Processor State
- ----------------------------------------------------------------------*/
-
-/* validate & invalidate the TIE register file */
-extern void xthal_validate_cp(int);
-extern void xthal_invalidate_cp(int);
-
-/* read and write cpenable register */
-extern void xthal_set_cpenable(unsigned);
-extern unsigned xthal_get_cpenable(void);
-
-
-/*----------------------------------------------------------------------
- Interrupts
- ----------------------------------------------------------------------*/
-
-/* the number of interrupt levels */
-extern const unsigned char Xthal_num_intlevels;
-/* the number of interrupts */
-extern const unsigned char Xthal_num_interrupts;
-
-/* mask for level of interrupts */
-extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];
-/* mask for level 0 to N interrupts */
-extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];
-
-/* level of each interrupt */
-extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];
-
-/* type per interrupt */
-extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];
-
-/* masks of each type of interrupt */
-extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];
-
-/* interrupt numbers assigned to each timer interrupt */
-extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];
-
-/* INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions: */
-extern unsigned xthal_get_intenable( void );
-extern void xthal_set_intenable( unsigned );
-extern unsigned xthal_get_interrupt( void );
-#define xthal_get_intread xthal_get_interrupt /* backward compatibility */
-extern void xthal_set_intset( unsigned );
-extern void xthal_set_intclear( unsigned );
-
-
-/*----------------------------------------------------------------------
- Debug
- ----------------------------------------------------------------------*/
-
-/* Number of instruction and data break registers: */
-extern const int Xthal_num_ibreak;
-extern const int Xthal_num_dbreak;
-
-
-/*----------------------------------------------------------------------
- Core Counter
- ----------------------------------------------------------------------*/
-
-/* counter info */
-extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */
-extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */
-
-/* get CCOUNT register (if not present return 0) */
-extern unsigned xthal_get_ccount(void);
-
-/* set and get CCOMPAREn registers (if not present, get returns 0) */
-extern void xthal_set_ccompare(int, unsigned);
-extern unsigned xthal_get_ccompare(int);
-
-
-/*----------------------------------------------------------------------
- Miscellaneous
- ----------------------------------------------------------------------*/
-
-extern const unsigned char Xthal_have_prid;
-extern const unsigned char Xthal_have_exceptions;
-extern const unsigned char Xthal_xea_version;
-extern const unsigned char Xthal_have_interrupts;
-extern const unsigned char Xthal_have_highlevel_interrupts;
-extern const unsigned char Xthal_have_nmi;
-
-extern unsigned xthal_get_prid( void );
-
-
-/*----------------------------------------------------------------------
- Virtual interrupt prioritization (DEPRECATED)
- ----------------------------------------------------------------------*/
-
-/* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */
-extern unsigned xthal_vpri_to_intlevel(unsigned vpri);
-extern unsigned xthal_intlevel_to_vpri(unsigned intlevel);
-
-/* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */
-extern unsigned xthal_int_enable(unsigned);
-extern unsigned xthal_int_disable(unsigned);
-
-/* Set/get virtual priority of an interrupt: */
-extern int xthal_set_int_vpri(int intnum, int vpri);
-extern int xthal_get_int_vpri(int intnum);
-
-/* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */
-extern void xthal_set_vpri_locklevel(unsigned intlevel);
-extern unsigned xthal_get_vpri_locklevel(void);
-
-/* Set/get current virtual interrupt priority: */
-extern unsigned xthal_set_vpri(unsigned vpri);
-extern unsigned xthal_get_vpri(void);
-extern unsigned xthal_set_vpri_intlevel(unsigned intlevel);
-extern unsigned xthal_set_vpri_lock(void);
-
-
-/*----------------------------------------------------------------------
- Generic Interrupt Trampolining Support (DEPRECATED)
- ----------------------------------------------------------------------*/
-
-typedef void (XtHalVoidFunc)(void);
-
-/* Bitmask of interrupts currently trampolining down: */
-extern unsigned Xthal_tram_pending;
-
-/*
- * Bitmask of which interrupts currently trampolining down synchronously are
- * actually enabled; this bitmask is necessary because INTENABLE cannot hold
- * that state (sync-trampolining interrupts must be kept disabled while
- * trampolining); in the current implementation, any bit set here is not set
- * in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level
- * one), its enable bit must be moved from here to INTENABLE:
- */
-extern unsigned Xthal_tram_enabled;
-
-/* Bitmask of interrupts configured for sync trampolining: */
-extern unsigned Xthal_tram_sync;
-
-/* Trampoline support functions: */
-extern unsigned xthal_tram_pending_to_service( void );
-extern void xthal_tram_done( unsigned serviced_mask );
-extern int xthal_tram_set_sync( int intnum, int sync );
-extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );
-
-
-/*----------------------------------------------------------------------
- Internal Memories
- ----------------------------------------------------------------------*/
-
-extern const unsigned char Xthal_num_instrom;
-extern const unsigned char Xthal_num_instram;
-extern const unsigned char Xthal_num_datarom;
-extern const unsigned char Xthal_num_dataram;
-extern const unsigned char Xthal_num_xlmi;
-
-/* Each of the following arrays contains at least one entry,
- * or as many entries as needed if more than one: */
-extern const unsigned int Xthal_instrom_vaddr[];
-extern const unsigned int Xthal_instrom_paddr[];
-extern const unsigned int Xthal_instrom_size [];
-extern const unsigned int Xthal_instram_vaddr[];
-extern const unsigned int Xthal_instram_paddr[];
-extern const unsigned int Xthal_instram_size [];
-extern const unsigned int Xthal_datarom_vaddr[];
-extern const unsigned int Xthal_datarom_paddr[];
-extern const unsigned int Xthal_datarom_size [];
-extern const unsigned int Xthal_dataram_vaddr[];
-extern const unsigned int Xthal_dataram_paddr[];
-extern const unsigned int Xthal_dataram_size [];
-extern const unsigned int Xthal_xlmi_vaddr[];
-extern const unsigned int Xthal_xlmi_paddr[];
-extern const unsigned int Xthal_xlmi_size [];
-
-
-/*----------------------------------------------------------------------
- Cache
- ----------------------------------------------------------------------*/
-
-/* number of cache sets in log2(lines per way) */
-extern const unsigned char Xthal_icache_setwidth;
-extern const unsigned char Xthal_dcache_setwidth;
-/* cache set associativity (number of ways) */
-extern const unsigned int Xthal_icache_ways;
-extern const unsigned int Xthal_dcache_ways;
-/* cache features */
-extern const unsigned char Xthal_icache_line_lockable;
-extern const unsigned char Xthal_dcache_line_lockable;
-
-/* cache attribute register control (used by other HAL routines) */
-extern unsigned xthal_get_cacheattr( void );
-extern unsigned xthal_get_icacheattr( void );
-extern unsigned xthal_get_dcacheattr( void );
-extern void xthal_set_cacheattr( unsigned );
-extern void xthal_set_icacheattr( unsigned );
-extern void xthal_set_dcacheattr( unsigned );
-/* set cache attribute (access modes) for a range of memory */
-extern int xthal_set_region_attribute( void *addr, unsigned size,
- unsigned cattr, unsigned flags );
-/* Bits of flags parameter to xthal_set_region_attribute(): */
-#define XTHAL_CAFLAG_EXPAND 0x000100 /* only expand allowed access to range, don't reduce it */
-#define XTHAL_CAFLAG_EXACT 0x000200 /* return error if can't apply change to exact range specified */
-#define XTHAL_CAFLAG_NO_PARTIAL 0x000400 /* don't apply change to regions partially covered by range */
-#define XTHAL_CAFLAG_NO_AUTO_WB 0x000800 /* don't writeback data after leaving writeback attribute */
-#define XTHAL_CAFLAG_NO_AUTO_INV 0x001000 /* don't invalidate after disabling cache (entering bypass) */
-
-/* enable caches */
-extern void xthal_icache_enable( void ); /* DEPRECATED */
-extern void xthal_dcache_enable( void ); /* DEPRECATED */
-/* disable caches */
-extern void xthal_icache_disable( void ); /* DEPRECATED */
-extern void xthal_dcache_disable( void ); /* DEPRECATED */
-
-/* invalidate the caches */
-extern void xthal_icache_all_invalidate( void );
-extern void xthal_dcache_all_invalidate( void );
-/* write dirty data back */
-extern void xthal_dcache_all_writeback( void );
-/* write dirty data back and invalidate */
-extern void xthal_dcache_all_writeback_inv( void );
-/* prefetch and lock specified memory range into cache */
-extern void xthal_icache_region_lock( void *addr, unsigned size );
-extern void xthal_dcache_region_lock( void *addr, unsigned size );
-extern void xthal_icache_line_lock(void *addr);
-extern void xthal_dcache_line_lock(void *addr);
-/* unlock from cache */
-extern void xthal_icache_all_unlock( void );
-extern void xthal_dcache_all_unlock( void );
-extern void xthal_icache_region_unlock( void *addr, unsigned size );
-extern void xthal_dcache_region_unlock( void *addr, unsigned size );
-extern void xthal_icache_line_unlock(void *addr);
-extern void xthal_dcache_line_unlock(void *addr);
-
-
-
-/*----------------------------------------------------------------------
- Local Memory ECC/Parity
- ----------------------------------------------------------------------*/
-
-/* Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx: */
-extern void xthal_memep_inject_error(void *addr, int size, int flags);
-
-
-
-/*----------------------------------------------------------------------
- Memory Management Unit
- ----------------------------------------------------------------------*/
-
-extern const unsigned char Xthal_have_spanning_way;
-extern const unsigned char Xthal_have_identity_map;
-extern const unsigned char Xthal_have_mimic_cacheattr;
-extern const unsigned char Xthal_have_xlt_cacheattr;
-extern const unsigned char Xthal_have_cacheattr;
-extern const unsigned char Xthal_have_tlbs;
-
-extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */
-extern const unsigned char Xthal_mmu_asid_kernel;
-extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
-extern const unsigned char Xthal_mmu_ring_bits;
-extern const unsigned char Xthal_mmu_sr_bits;
-extern const unsigned char Xthal_mmu_ca_bits;
-extern const unsigned int Xthal_mmu_max_pte_page_size;
-extern const unsigned int Xthal_mmu_min_pte_page_size;
-
-extern const unsigned char Xthal_itlb_way_bits;
-extern const unsigned char Xthal_itlb_ways;
-extern const unsigned char Xthal_itlb_arf_ways;
-extern const unsigned char Xthal_dtlb_way_bits;
-extern const unsigned char Xthal_dtlb_ways;
-extern const unsigned char Xthal_dtlb_arf_ways;
-
-/* Convert between virtual and physical addresses (through static maps only): */
-/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/
-extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
-extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
-
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-
-
-/****************************************************************************
- EXPERIMENTAL and DEPRECATED Definitions
- ****************************************************************************/
-
-
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef INCLUDE_DEPRECATED_HAL_CODE
-extern const unsigned char Xthal_have_old_exc_arch;
-extern const unsigned char Xthal_have_mmu;
-extern const unsigned int Xthal_num_regs;
-extern const unsigned char Xthal_num_iroms;
-extern const unsigned char Xthal_num_irams;
-extern const unsigned char Xthal_num_droms;
-extern const unsigned char Xthal_num_drams;
-extern const unsigned int Xthal_configid0;
-extern const unsigned int Xthal_configid1;
-#endif
-
-#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
-#define XTHAL_24_BIT_BREAK 0x80000000
-#define XTHAL_16_BIT_BREAK 0x40000000
-extern const unsigned short Xthal_ill_inst_16[16];
-#define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */
-#define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */
-#define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */
-#define XTHAL_RFW_INST 0x00000800
-#define XTHAL_RFUE_INST 0x00000400
-#define XTHAL_RFI_INST 0x00000200
-#define XTHAL_RFE_INST 0x00000100
-#define XTHAL_RET_INST 0x00000080
-#define XTHAL_BREAK_INST 0x00000040
-#define XTHAL_SYSCALL_INST 0x00000020
-#define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */
-#define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */
-#define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */
-#define XTHAL_24_BIT_INST 0x00000002
-#define XTHAL_16_BIT_INST 0x00000001
-typedef struct xthal_state {
- unsigned pc;
- unsigned ar[16];
- unsigned lbeg;
- unsigned lend;
- unsigned lcount;
- unsigned extra_ptr;
- unsigned cpregs_ptr[XTHAL_MAX_CPS];
-} XTHAL_STATE;
-extern unsigned int xthal_inst_type(void *addr);
-extern unsigned int xthal_branch_addr(void *addr);
-extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);
-#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
-
-#endif /*XTENSA_HAL_H*/
+++ /dev/null
-/*
- * xtruntime.h -- general C definitions for single-threaded run-time
- *
- * Copyright (c) 2002-2006 by Tensilica Inc. ALL RIGHTS RESERVED.
- * These coded instructions, statements, and computer programs are the
- * copyrighted works and confidential proprietary information of Tensilica Inc.
- * They may not be modified, copied, reproduced, distributed, or disclosed to
- * third parties in any manner, medium, or form, in whole or in part, without
- * the prior written consent of Tensilica Inc.
- */
-
-#ifndef XTRUNTIME_H
-#define XTRUNTIME_H
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-
-#ifndef XTSTR
-#define _XTSTR(x) # x
-#define XTSTR(x) _XTSTR(x)
-#endif
-
-#define _xtos_set_execption_handler _xtos_set_exception_handler /* backward compatibility */
-#define _xtos_set_saved_intenable _xtos_ints_on /* backward compatibility */
-#define _xtos_clear_saved_intenable _xtos_ints_off /* backward compatibility */
-
-#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*typedef void (_xtos_timerdelta_func)(int);*/
-#ifdef __cplusplus
-typedef void (_xtos_handler_func)(...);
-#else
-typedef void (_xtos_handler_func)();
-#endif
-typedef _xtos_handler_func *_xtos_handler;
-
-/*
- * unsigned XTOS_SET_INTLEVEL(int intlevel);
- * This macro sets the current interrupt level.
- * The 'intlevel' parameter must be a constant.
- * This macro returns a 32-bit value that must be passed to
- * XTOS_RESTORE_INTLEVEL() to restore the previous interrupt level.
- * XTOS_RESTORE_JUST_INTLEVEL() also does this, but in XEA2 configs
- * it restores only PS.INTLEVEL rather than the entire PS register
- * and thus is slower.
- */
-#if !XCHAL_HAVE_INTERRUPTS
-# define XTOS_SET_INTLEVEL(intlevel)
-# define XTOS_SET_MIN_INTLEVEL(intlevel)
-# define XTOS_RESTORE_INTLEVEL(restoreval)
-# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)
-#elif XCHAL_HAVE_XEA2
-/* In XEA2, we can simply safely set PS.INTLEVEL directly: */
-/* NOTE: these asm macros don't modify memory, but they are marked
- * as such to act as memory access barriers to the compiler because
- * these macros are sometimes used to delineate critical sections;
- * function calls are natural barriers (the compiler does not know
- * whether a function modifies memory) unless declared to be inlined. */
-# define XTOS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \
- __asm__ __volatile__( "rsil %0, " XTSTR(intlevel) "\n" \
- : "=a" (__tmp) : : "memory" ); \
- __tmp;})
-# define XTOS_SET_MIN_INTLEVEL(intlevel) ({ unsigned __tmp, __tmp2, __tmp3; \
- __asm__ __volatile__( "rsr %0, " XTSTR(PS) "\n" /* get old (current) PS.INTLEVEL */ \
- "movi %2, " XTSTR(intlevel) "\n" \
- "extui %1, %0, 0, 4\n" /* keep only INTLEVEL bits of parameter */ \
- "blt %2, %1, 1f\n" \
- "rsil %0, " XTSTR(intlevel) "\n" \
- "1:\n" \
- : "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \
- __tmp;})
-# define XTOS_RESTORE_INTLEVEL(restoreval) do{ unsigned __tmp = (restoreval); \
- __asm__ __volatile__( "wsr %0, " XTSTR(PS) " ; rsync\n" \
- : : "a" (__tmp) : "memory" ); \
- }while(0)
-# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_intlevel(restoreval)
-#else
-/* In XEA1, we have to rely on INTENABLE register virtualization: */
-extern unsigned _xtos_set_vpri( unsigned vpri );
-extern unsigned _xtos_vpri_enabled; /* current virtual priority */
-# define XTOS_SET_INTLEVEL(intlevel) _xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
-# define XTOS_SET_MIN_INTLEVEL(intlevel) _xtos_set_vpri(_xtos_vpri_enabled & ~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
-# define XTOS_RESTORE_INTLEVEL(restoreval) _xtos_set_vpri(restoreval)
-# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_vpri(restoreval)
-#endif
-
-/*
- * The following macros build upon the above. They are generally used
- * instead of invoking the SET_INTLEVEL and SET_MIN_INTLEVEL macros directly.
- * They all return a value that can be used with XTOS_RESTORE_INTLEVEL()
- * or _xtos_restore_intlevel() or _xtos_restore_just_intlevel() to restore
- * the effective interrupt level to what it was before the macro was invoked.
- * In XEA2, the DISABLE macros are much faster than the MASK macros
- * (in all configs, DISABLE sets the effective interrupt level, whereas MASK
- * makes ensures the effective interrupt level is at least the level given
- * without lowering it; in XEA2 with INTENABLE virtualization, these macros
- * affect PS.INTLEVEL only, not the virtual priority, so DISABLE has partial
- * MASK semantics).
- *
- * A typical critical section sequence might be:
- * unsigned rval = XTOS_DISABLE_EXCM_INTERRUPTS;
- * ... critical section ...
- * XTOS_RESTORE_INTLEVEL(rval);
- */
-/* Enable all interrupts (those activated with _xtos_ints_on()): */
-#define XTOS_ENABLE_INTERRUPTS XTOS_SET_INTLEVEL(0)
-/* Disable low priority level interrupts (they can interact with the OS): */
-#define XTOS_DISABLE_LOWPRI_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
-#define XTOS_MASK_LOWPRI_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
-/* Disable interrupts that can interact with the OS: */
-#define XTOS_DISABLE_EXCM_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL)
-#define XTOS_MASK_EXCM_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_EXCM_LEVEL)
-#if 0 /* XTOS_LOCK_LEVEL is not exported to applications */
-/* Disable interrupts that can interact with the OS, or manipulate virtual INTENABLE: */
-#define XTOS_DISABLE_LOCK_INTERRUPTS XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL)
-#define XTOS_MASK_LOCK_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XTOS_LOCK_LEVEL)
-#endif
-/* Disable ALL interrupts (not for common use, particularly if one's processor
- * configuration has high-level interrupts and one cares about their latency): */
-#define XTOS_DISABLE_ALL_INTERRUPTS XTOS_SET_INTLEVEL(15)
-
-
-extern unsigned int _xtos_ints_off( unsigned int mask );
-extern unsigned int _xtos_ints_on( unsigned int mask );
-extern unsigned _xtos_set_intlevel( int intlevel );
-extern unsigned _xtos_set_min_intlevel( int intlevel );
-extern unsigned _xtos_restore_intlevel( unsigned restoreval );
-extern unsigned _xtos_restore_just_intlevel( unsigned restoreval );
-extern _xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f );
-extern _xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg );
-extern _xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f );
-
-extern void _xtos_memep_initrams( void );
-extern void _xtos_memep_enable( int flags );
-
-/* Deprecated (but kept because they were documented): */
-extern unsigned int _xtos_read_ints( void ); /* use xthal_get_interrupt() instead */
-extern void _xtos_clear_ints( unsigned int mask ); /* use xthal_set_intclear() instead */
-
-#if XCHAL_NUM_CONTEXTS > 1
-extern unsigned _xtos_init_context(int context_num, int stack_size,
- _xtos_handler_func *start_func, int arg1);
-#endif
-
-/* Deprecated: */
-#if XCHAL_NUM_TIMERS > 0
-extern void _xtos_timer_0_delta( int cycles );
-#endif
-#if XCHAL_NUM_TIMERS > 1
-extern void _xtos_timer_1_delta( int cycles );
-#endif
-#if XCHAL_NUM_TIMERS > 2
-extern void _xtos_timer_2_delta( int cycles );
-#endif
-#if XCHAL_NUM_TIMERS > 3
-extern void _xtos_timer_3_delta( int cycles );
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */
-
-#endif /* XTRUNTIME_H */
projects / open-ath9k-htc-firmware.git / commitdiff