*/
#include <stdio.h>
#include <string.h>
+#include <stdint.h>
#define MAX_READ_SIZE 80
-unsigned long checksum = 0;
+uint32_t checksum = 0;
-void write_file(FILE *out, unsigned char *buf, unsigned long size, unsigned char *endian, unsigned char nl)
+void write_file(FILE *out, unsigned char *buf, uint32_t size, unsigned char *endian, unsigned char nl)
{
int i=0;
unsigned char tmp_buf[4];
tmp_buf[2] = buf[i+2];
tmp_buf[3] = buf[i+3];
- fprintf(out, "0x%08X, ", *((unsigned long *)(&tmp_buf[0])));
+ fprintf(out, "0x%08X, ", *((uint32_t *)(&tmp_buf[0])));
} else {
tmp_buf[1] = buf[i+2];
tmp_buf[2] = buf[i+1];
tmp_buf[3] = buf[i+0];
- fprintf(out, "0x%08X, ", *((unsigned long *)(&tmp_buf[0])));
+ fprintf(out, "0x%08X, ", *((uint32_t *)(&tmp_buf[0])));
}
- checksum = checksum ^ *((unsigned long *)(&tmp_buf[0]));
+ checksum = checksum ^ *((uint32_t *)(&tmp_buf[0]));
}
}
}
fprintf(out, "};\n");
- fprintf(out, "\nconst unsigned long zcFwImageSize=%ld;\n", file_size);
+ fprintf(out, "\nconst uint32_t zcFwImageSize=%ld;\n", file_size);
goto ERR_DONE;
}
file_size += 4;
fprintf(out, "};\n");
- fprintf(out, "\nconst unsigned long zcFwImageSize=%ld;\n", file_size);
+ fprintf(out, "\nconst uint32_t zcFwImageSize=%ld;\n", file_size);
goto ERR_DONE;
}
}
/* move a memory buffer */
-static inline void __adf_os_mem_copy(void *dst, void *src, adf_os_size_t size)
+static inline void __adf_os_mem_copy(void *dst, const void *src, adf_os_size_t size)
{
A_MEMCPY(dst,src,size);
}
* @param[in] size buffer size
*/
static inline void
-adf_os_mem_copy(void *dst, void *src, adf_os_size_t size)
+adf_os_mem_copy(void *dst, const void *src, adf_os_size_t size)
{
__adf_os_mem_copy(dst, src, size);
}
void
change_magpie_clk(void)
{
- volatile uint32_t i=0, rd_data;
+ volatile uint32_t rd_data;
HAL_WORD_REG_WRITE(0x00056004, 0x11);
rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1;
AR6002_fatal_exception_handler_patch(CPU_exception_frame_t *exc_frame)
{
struct register_dump_s dump;
- void (*reset_func)(void) = (void*)(RESET_VECTOR_ADDRESS);
uint32_t exc_cause, exc_vaddr;
asm volatile("rsr %0,%1" : "=r" (exc_cause) : "n" (EXCCAUSE));
asm volatile("rsr %0,%1" : "=r" (exc_vaddr) : "n" (EXCVADDR));
static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command,
A_UINT16 SeqNo, A_UINT8 *buffer, int Length);
+#if MAGPIE_ENABLE_WLAN == 0
static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] =
{
{dispatch_magpie_sys_cmds, WMI_ECHO_CMDID, 0},
};
static WMI_DECLARE_DISPATCH_TABLE(Magpie_Sys_Commands_Tbl, Magpie_Sys_DispatchEntries);
+#endif
htc_handle_t htc_handle;
#endif
#define AR5416_DEVID_PCIE 0x0024 /* AR5416 PCI-E (XB) (Owl) */
+#define HAL_RATE_TABLE_SIZE 33
typedef enum {
HAL_OK = 0, /* No error */
typedef struct {
a_int32_t rateCount;
- a_uint8_t rateCodeToIndex[32];
+ a_uint8_t rateCodeToIndex[HAL_RATE_TABLE_SIZE];
struct {
a_uint8_t valid;
a_uint8_t phy;
a_uint8_t controlRate;
a_uint16_t lpAckDuration;
a_uint16_t spAckDuration;
- } info[32];
+ } info[HAL_RATE_TABLE_SIZE];
} HAL_RATE_TABLE;
typedef struct {
typedef struct {
a_int32_t rateCount;
- a_uint8_t rateCodeToIndex[32];
+ a_uint8_t rateCodeToIndex[HAL_RATE_TABLE_SIZE];
struct {
a_uint8_t valid;
a_uint8_t phy;
a_uint8_t controlRate;
a_uint16_t lpAckDuration;
a_uint16_t spAckDuration;
- } info[32];
+ } info[HAL_RATE_TABLE_SIZE];
} HAL_RATE_TABLE;
#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
/* Target receive Functions */
a_uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
void __ahdecl(*ah_setRxDP)(struct ath_hal*, a_uint32_t rxdp);
- HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
+ HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_rx_desc *,
a_uint32_t size, a_uint32_t flags);
HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *,
a_uint32_t phyAddr, struct ath_desc *next, u_int64_t tsf);
HAL_STATUS __ahdecl(*ah_procRxDescFast)(struct ath_hal *ah,
- struct ath_desc *ds, a_uint32_t pa,
+ struct ath_rx_desc *ds, a_uint32_t pa,
struct ath_desc *nds,
struct ath_rx_status *rx_stats);
HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
#define HAL_RXKEYIX_INVALID ((a_uint8_t) -1)
-#define HAL_TXKEYIX_INVALID ((a_uint32_t) -1)
+#define HAL_TXKEYIX_INVALID ((a_uint8_t) -1)
/*
* The following definitions are passed directly
}
void * __ahdecl
-ath_hal_memcpy(void *dst, void *src, adf_os_size_t n)
+ath_hal_memcpy(void *dst, const void *src, adf_os_size_t n)
{
adf_os_mem_copy(dst, src, n);
return 0;
#define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n))
extern void __ahdecl ath_hal_memzero(void *, size_t);
#define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n)
-extern void * __ahdecl ath_hal_memcpy(void *, void *, size_t);
+extern void * __ahdecl ath_hal_memcpy(void *, const void *, size_t);
#ifndef abs
#define abs(_a) __builtin_abs(_a)
extern a_uint32_t __ahdecl ath_hal_getuptime(struct ath_hal *);
#define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah)
-/*
- * Byte order/swapping support.
- */
-#define AH_LITTLE_ENDIAN 1234
-#define AH_BIG_ENDIAN 4321
-
-#if AH_BYTE_ORDER == AH_BIG_ENDIAN
-/*
- * This could be optimized but since we only use it for
- * a few registers there's little reason to do so.
- */
-#ifndef __bswap32
-static inline a_uint32_t
-__bswap32(a_uint32_t _x)
-{
- return ((a_uint32_t)(
- (((const a_uint8_t *)(&_x))[0] ) |
- (((const a_uint8_t *)(&_x))[1]<< 8) |
- (((const a_uint8_t *)(&_x))[2]<<16) |
- (((const a_uint8_t *)(&_x))[3]<<24))
- );
-}
-#endif
-#ifndef __bswap16
-#define __bswap16(_x) ( (a_uint16_t)( (((const a_uint8_t *)(&_x))[0] ) |\
- ( ( (const a_uint8_t *)( &_x ) )[1]<< 8) ) )
-#endif
-#else
#ifndef __bswap32
#define __bswap32(_x) (_x)
#endif
#ifndef __bswap16
#define __bswap16(_x) (_x)
#endif
-#endif
#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write_target(_ah, _reg, _val)
#define OS_REG_READ(_ah, _reg) ath_hal_reg_read_target(_ah, _reg)
#define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
struct ar5416_desc *ads = AR5416DESC(ds);
- struct ath_hal_5416 *ahp = AH5416(ah);
(void) hdrLen;
a_uint32_t flags)
{
struct ar5416_desc *ads = AR5416DESC(ds);
- struct ath_hal_5416 *ahp = AH5416(ah);
HALASSERT(isValidPktType(type));
HALASSERT(isValidKeyType(keyType));
a_uint32_t flags)
{
struct ar5416_desc *ads = AR5416DESC(ds);
- struct ar5416_desc_20 *ads_20 = AR5416DESC_20(ds);
a_uint32_t ds_ctl0;
- a_int16_t txpower;
- a_uint32_t count;
- struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
HALASSERT(nseries == 4);
(void)nseries;
},
};
-adf_os_export_symbol(ar5416_11na_table);
-
#undef OFDM
#undef CCK
#undef TURBO
a_uint8_t schan; /* starting channel */
a_uint8_t nchan; /* number channels */
a_uint8_t maxtxpwr; /* tx power cap */
- } band[4] adf_os_packed; /* up to 4 sub bands */
+ } adf_os_packed band[4]; /* up to 4 sub bands */
} adf_os_packed;
#define IEEE80211_CHALLENGE_LEN 128
#define UAPSDQ_NUM 9
#define CABQ_NUM 8
-void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id, A_UINT8 *buffer, a_int32_t Length);
void owl_tgt_tx_tasklet(TQUEUE_ARG data);
static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
-void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length);
static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
-extern struct ath_buf * ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
+extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
extern void ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq, owl_txq_state_t txqstate);
}
void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
- A_UINT8 *buffer, a_int32_t Length)
+ void *buffer, a_int32_t Length)
{
adf_nbuf_t netbuf = ADF_NBUF_NULL;
a_uint8_t *pData;
}
void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo,
- A_UINT8 *buffer, a_int32_t Length)
+ void *buffer, a_int32_t Length)
{
adf_nbuf_t netbuf = ADF_NBUF_NULL;
A_UINT8 *pData;
break;
}
- if (ds->ds_link == NULL) {
+ if (ds->ds_link == 0) {
break;
}
bf->bf_status |= ATH_BUFSTATUS_DONE;
- bf = asf_tailq_next(bf, bf_list);
+ bf = (struct ath_rx_buf *)asf_tailq_next(bf, bf_list);
}
else {
ds = asf_tailq_next(ds, ds_list);
struct ath_rx_buf *bf = NULL;
struct ath_hal *ah = sc->sc_ah;
struct rx_frame_header *rxhdr;
- struct ieee80211_frame *wh;
struct ath_rx_status *rxstats;
adf_nbuf_t skb = ADF_NBUF_NULL;
HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb);
sc->sc_rx_stats.ast_rx_send++;
- next_buf:
bf->bf_status &= ~ATH_BUFSTATUS_DONE;
asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list);
* FIXME: Short Preamble.
*/
static void ath_beacon_setup(struct ath_softc_tgt *sc,
- struct ath_buf *bf,
+ struct ath_tx_buf *bf,
struct ath_vap_target *avp)
{
adf_nbuf_t skb = bf->bf_skb;
struct ath_hal *ah = sc->sc_ah;
struct ath_desc *ds;
- a_int32_t flags, antenna;
+ a_int32_t flags;
const HAL_RATE_TABLE *rt;
a_uint8_t rix, rate;
HAL_11N_RATE_SERIES series[4] = {{ 0 }};
vap_index = bhdr->vap_index;
adf_os_assert(vap_index < TARGET_VAP_MAX);
- vap = &sc->sc_vap[vap_index];
+ vap = &sc->sc_vap[vap_index].av_vap;
wh = (struct ieee80211_frame *)adf_nbuf_pull_head(nbuf,
sizeof(ath_beacon_hdr_t));
ath_bufhead *head, a_int32_t dir)
{
struct ath_tx_buf *bf;
- struct ieee80211_node *ni;
+ struct ieee80211_node_target *ni;
asf_tailq_foreach(bf, head, bf_list) {
if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
{
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl;
struct ath_hal *ah = sc->sc_ah;
- struct ieee80211com_target *ic = &sc->sc_ic;
HAL_INT status;
if (sc->sc_invalid)
{
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
a_uint16_t mode;
- struct ath_hal *ah = sc->sc_ah;
mode= *((a_uint16_t *)data);
mode = adf_os_ntohs(mode);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
-static a_uint32_t ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
+static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
A_UINT8 *data, a_int32_t datalen)
{
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
{
}
-static char *dev_info = "ath_pci_tgt";
-
void
bus_read_cachesize(struct ath_softc *sc, a_uint8_t *csz)
{
struct ath_desc;
struct ieee80211vap;
struct ieee80211com_target;
+struct ath_tx_desc;
struct ath_ratectrl {
size_t arc_space; /* space required for per-node state */
#define TARGET_NODE_MAX ATH_NODE_MAX
#define TARGET_VAP_MAX ATH_VAP_MAX
-#define ATH_NODE_TARGET(_n) ((struct ath_node *)(_n))
-
#define MAX_RATE_POWER 63
#define ATH_COMP_PROC_NO_COMP_NO_CCS 3
ath_deschead sc_rxdesc_idle;
ath_deschead sc_rxdesc;
- struct ath_desc *sc_rxdesc_held;
+ struct ath_rx_desc *sc_rxdesc_held;
struct ath_buf *sc_txbuf_held;
a_uint8_t format_id;
a_uint8_t class;
a_uint8_t window_x2;
- } type_u adf_os_packed;
+ } adf_os_packed type_u;
struct {
a_uint8_t num_snd_x2;
a_uint8_t num_rcv_x2;
- } type_i adf_os_packed;
+ } adf_os_packed type_i;
struct {
a_uint8_t control;
a_uint8_t num_rcv_x2;
- } type_s adf_os_packed;
+ } adf_os_packed type_s;
struct {
a_uint8_t control;
/*
a_uint8_t frmr_control;
a_uint8_t frmr_control_ext;
a_uint8_t frmr_cause;
- } type_frmr adf_os_packed;
+ } adf_os_packed type_frmr;
struct {
a_uint8_t control;
a_uint8_t org_code[3];
a_uint16_t ether_type;
- } type_snap adf_os_packed;
+ } adf_os_packed type_snap;
struct {
a_uint8_t control;
a_uint8_t control_ext;
- } type_raw adf_os_packed;
+ } adf_os_packed type_raw;
} llc_un /* XXX adf_os_packed ??? */;
} adf_os_packed;
void adf_print_buf(adf_nbuf_t buf);
static void ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid);
-struct ath_buf * ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
- adf_nbuf_t skb, ath_data_hdr_t *dh);
void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb);
static void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
static void ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
-static struct ath_node_target * owltarget_findnode(struct tx_frame_heade *dh,
- struct ath_softc_tgt *sc,
- struct adf_nbuf_t *skb);
extern a_int32_t ath_chainmask_sel_logic(void *);
static a_int32_t ath_get_pktlen(struct ath_buf *bf, a_int32_t hdrlen);
static void ath_tgt_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
return duration;
}
-static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_buf *bf)
+static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
adf_nbuf_t skb = bf->bf_skb;
adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
}
-static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_buf *bf)
+static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
adf_nbuf_t skb = bf->bf_skb;
static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
- struct ath_desc *ds0, *ds = bf->bf_desc;
- adf_nbuf_t skb;
- adf_nbuf_queue_t skbhead;
- a_int32_t i, dscnt = 0;
+ struct ath_desc *ds = bf->bf_desc;
switch (bf->bf_protmode) {
case IEEE80211_PROT_RTSCTS:
HAL_11N_RATE_SERIES series[4];
a_int32_t i, flags;
a_uint8_t rix, cix, rtsctsrate;
- a_uint32_t aggr_limit_with_rts;
a_uint32_t ctsduration = 0;
a_int32_t prot_mode = AH_FALSE;
}
}
- ath_hal_getrtsaggrlimit(sc->sc_ah, &aggr_limit_with_rts);
-
- if (bf->bf_isaggr && aggr_limit_with_rts &&
- bf->bf_al > aggr_limit_with_rts) {
- flags &= ~(HAL_TXDESC_RTSENA);
- }
-
adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES) * 4);
for (i = 0; i < 4; i++) {
void owl_tgt_node_init(struct ath_node_target * an)
{
struct ath_atx_tid *tid;
- int tidno, i;
+ int tidno;
for (tidno = 0, tid = &an->tid[tidno]; tidno < WME_NUM_TID;tidno++, tid++) {
tid->tidno = tidno;
}
}
-struct WMI_TXSTATUS_EVENT* ath_tx_status_get(struct ath_softc_tgt *sc)
+static WMI_TXSTATUS_EVENT *ath_tx_status_get(struct ath_softc_tgt *sc)
{
WMI_TXSTATUS_EVENT *txs = NULL;
int i;
{
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
a_int32_t i;
- a_uint32_t qcumask = ((1 << HAL_NUM_TX_QUEUES) - 1);
struct ath_txq *txq;
- ath_data_hdr_t *dh;
ath_tx_status_clear(sc);
struct ath_tx_buf *bf)
{
struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
- struct ath_desc *ds = bf->bf_lastds;
ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
if (tid->flag & TID_CLEANUP_INPROGRES) {
a_int32_t node_index)
{
struct ath_node_target *an;
- a_int32_t i;
struct ieee80211_node_target *ni;
if (node_index > TARGET_NODE_MAX)
return bf;
}
-struct ath_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
+struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
adf_nbuf_t skb, ath_data_hdr_t *dh)
{
struct ath_tx_buf *bf;
- struct ath_txq *txq;
struct ieee80211_node_target *ni;
- a_uint32_t flags = adf_os_ntohl(dh->flags);
struct ath_atx_tid *tid;
ni = ath_tgt_find_node(sc, dh->ni_index);
struct ath_tx_buf *bf)
{
struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
- const struct ieee80211_cipher *cip;
- struct ieee80211_key *k;
if (!(wh->i_fc[1] & IEEE80211_FC1_WEP)) {
bf->bf_keytype = HAL_KEY_TYPE_CLEAR;
{
struct ath_hal *ah = sc->sc_ah;
struct ath_txq *txq;
- struct ath_node_target *an;
HAL_STATUS status;
- static a_int32_t count = 0,i;
volatile a_int32_t txe_val;
adf_os_assert(bf);
ath_tgt_rate_findrate(sc, an, shortPreamble,
0, 0, 0, 0, 0,
rcs, &isProbe);
- memcpy(bf->bf_rcs, rcs, sizeof(rcs));
+ ath_hal_memcpy(bf->bf_rcs, rcs, sizeof(rcs));
} else {
mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0;
mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0;
mrcs[0].rix = 0;
mrcs[0].tries = 1;
mrcs[0].flags = 0;
- memcpy(bf->bf_rcs, mrcs, sizeof(mrcs));
+ ath_hal_memcpy(bf->bf_rcs, mrcs, sizeof(mrcs));
}
ath_buf_set_rate(sc, bf);
static void
ath_update_stats(struct ath_softc_tgt *sc, struct ath_buf *bf)
{
- struct ieee80211_node_target *ni = bf->bf_node;
struct ath_tx_desc *ds = bf->bf_desc;
- struct ath_node_target *an = ATH_NODE_TARGET(ni);
u_int32_t sr, lr;
- struct ieee80211_cb *cb;
if (ds->ds_txstat.ts_status == 0) {
if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
struct ath_vap_target *avp;
struct ath_hal *ah = sc->sc_ah;
a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
- a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration, fval;
+ a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration;
a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
- struct ath_desc *ds=NULL, *ds0=NULL;
+ struct ath_desc *ds=NULL;
struct ath_txq *txq=NULL;
struct ath_tx_buf *bf;
HAL_PKT_TYPE atype;
struct ath_rc_series rcs[4];
HAL_11N_RATE_SERIES series[4];
ath_mgt_hdr_t *mh;
- struct ieee80211com_target *ic = &sc->sc_ic;
a_int8_t keyix;
if (!hdr_buf) {
{
ath_atx_tid_t *tid;
struct ath_node_target *an;
- struct ath_desc *ds;
- struct ath_txq *txq = bf->bf_txq;
- a_bool_t queue_frame;
an = (struct ath_node_target *)bf->bf_node;
adf_os_assert(an);
{
struct ath_atx_tid *tid;
u_int8_t bdone;
- HAL_STATUS status;
- u_int8_t smps_mode;
- struct ieee80211_node *ieee_node;
- u_int32_t aggr_limit_with_rts;
bdone = AH_FALSE;
{
ath_atx_tid_t *tid;
struct ath_node_target *an;
- struct ath_desc *ds;
struct ath_txq *txq = bf->bf_txq;
a_bool_t queue_frame, within_baw;