OUTPUT fw.bin
DEPENDS fw.elf
COMMAND ${CMAKE_OBJCOPY}
+ --change-section-lma .boot-0x400000
+ --change-section-vma .boot-0x400000
--change-section-lma .text-0x400000
--change-section-vma .text-0x400000
-O binary fw.elf fw.bin
(((x) & 0x0000ff00) << 8) | \
(((x) & 0x000000ff) << 24))
-#if 0
-static __inline __uint64_t
-__bswap64(__uint64_t _x)
-{
-
- return ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) |
- ((_x >> 8) & 0xff000000) | ((_x << 8) & ((__uint64_t)0xff << 32)) |
- ((_x << 24) & ((__uint64_t)0xff << 40)) |
- ((_x << 40) & ((__uint64_t)0xff << 48)) | ((_x << 56)));
-}
-#endif
-
-#define __adf_os_reg_read8(_dev, _addr) oops no implementation...
-
-#define __adf_os_reg_read16(_dev, _addr) oops no implementation...
-
-#define __adf_os_reg_read32(_dev, _addr) *((a_uint32_t *)(WLAN_BASE_ADDRESS + _addr))
-
-#define __adf_os_reg_read64(_dev, _addr) oops no implementation...
-
-#define __adf_os_reg_write8(_dev, _addr, _val) oops no implementation...
-
-#define __adf_os_reg_write16(_dev, _addr, _val) oops no implementation...
-
-// RAY: The delay is required. But needs to know why??
-//#define __adf_os_reg_write32(_dev, _addr, _val) *((a_uint32_t *)(0x10ff0000 + _addr)) = _val; A_DELAY_USECS(100);
-//RAY 0806: Move the delay (100us) to the host side because of throughput issue
-#define __adf_os_reg_write32(_dev, _addr, _val) *((a_uint32_t *)(WLAN_BASE_ADDRESS + _addr)) = _val;
-
-#define __adf_os_reg_write64(_dev, _addr, _val) oops no implementation...
-
#define __adf_os_ntohs(x) x
#define __adf_os_ntohl(x) x
#define __adf_os_htonl(x) x
#define __adf_os_cpu_to_le16(x) __bswap16(x)
-#define __adf_os_cpu_to_le32(x) __bswap32(x)
-#define __adf_os_cpu_to_le64(x) x
-
-#define __adf_os_cpu_to_be16(x) x
-#define __adf_os_cpu_to_be32(x) x
-#define __adf_os_cpu_to_be64(x) x
-
-#define __adf_os_le16_to_cpu(x) __bswap16(x)
-#define __adf_os_le32_to_cpu(x) __bswap32(x)
-#define __adf_os_le64_to_cpu(x) x
-
-#define __adf_os_be16_to_cpu(x) x
-#define __adf_os_be32_to_cpu(x) x
-#define __adf_os_be64_to_cpu(x) x
#endif
#if SYSTEM_MODULE_SFLASH
+#include "adf_os_io.h"
+
#include "reg_defs.h"
#include "sflash_api.h"
do
{
- poldata = HAL_WORD_REG_READ(SPI_CS_ADDRESS);
+ poldata = ioread32(SPI_CS_ADDRESS);
flg = SPI_CS_BUSY_GET(poldata);
} while (flg != 0x0);
LOCAL void
_cmnos_sflash_WaitTillNotWriteInProcess(void)
{
- A_UINT32 poldata;
A_UINT32 flg;
do
{
_cmnos_sflash_WaitTillTransactionOver();
- HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR) );
- HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1) );
+ iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR));
+ iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1));
_cmnos_sflash_WaitTillTransactionOver();
- poldata = HAL_WORD_REG_READ(SPI_D_ADDRESS);
- flg = poldata & ZM_SFLASH_STATUS_REG_WIP;
+ flg = ioread32(SPI_D_ADDRESS) & ZM_SFLASH_STATUS_REG_WIP;
} while (flg != 0x0);
}
{
_cmnos_sflash_WaitTillNotWriteInProcess();
- HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_WREN) );
- HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) );
+ iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_WREN));
+ iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1));
_cmnos_sflash_WaitTillTransactionOver();
}
cmnos_sflash_init(void)
{
/* Switch the function of I/O pin 19~22 to act as SPI pins */
- HAL_WORD_REG_WRITE( MAGPIE_REG_CLOCK_CTRL_ADDR, HAL_WORD_REG_READ(MAGPIE_REG_CLOCK_CTRL_ADDR)|BIT8 );
+ io32_set(MAGPIE_REG_CLOCK_CTRL_ADDR, BIT8);
/* "Autosize-determination of the address size of serial flash" is obsolete according to Brian Yang's mail :
* The designers reached an conclusion that the spi master (the apb_spi interface control) will be
*/
/* Force SPI address size to 24 bits */
- HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_AUTOSIZ_OVR_SET(2) );
+ iowrite32(SPI_CS_ADDRESS, SPI_CS_AUTOSIZ_OVR_SET(2));
}
/************************************************************************/
_cmnos_sflash_WriteEnable();
_cmnos_sflash_WaitTillNotWriteInProcess();
- HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(erase_opcode) | SPI_AO_ADDR_SET(addr) );
- HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(tx_len) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) );
+ iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(erase_opcode) | SPI_AO_ADDR_SET(addr));
+ iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(tx_len) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1));
#if 0
/* Do not wait(let it be completed in background) */
_cmnos_sflash_WriteEnable();
_cmnos_sflash_WaitTillNotWriteInProcess();
- HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_PP) | SPI_AO_ADDR_SET(s_addr) );
- HAL_WORD_REG_WRITE( SPI_D_ADDRESS, SPI_D_DATA_SET(t_word_data) );
- HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(4 + write_byte) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) );
+ iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_PP) | SPI_AO_ADDR_SET(s_addr));
+ iowrite32(SPI_D_ADDRESS, SPI_D_DATA_SET(t_word_data));
+ iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(4 + write_byte) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1));
_cmnos_sflash_WaitTillTransactionOver();
_cmnos_sflash_WaitTillNotWriteInProcess();
- HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(read_opcode) | SPI_AO_ADDR_SET(addr + i*4) );
- HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(write_byte) | SPI_CS_RXBCNT_SET(read_byte) | SPI_CS_XCNSTART_SET(1) );
+ iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(read_opcode) | SPI_AO_ADDR_SET(addr + i*4));
+ iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(write_byte) | SPI_CS_RXBCNT_SET(read_byte) | SPI_CS_XCNSTART_SET(1));
_cmnos_sflash_WaitTillTransactionOver();
_cmnos_sflash_WaitTillTransactionOver();
- HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR) );
- HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1) );
+ iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR));
+ iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1));
_cmnos_sflash_WaitTillTransactionOver();
- word_data = HAL_WORD_REG_READ(SPI_D_ADDRESS) & 0x000000FF;
+ word_data = ioread32(SPI_D_ADDRESS) & 0x000000FF;
return word_data;
}
#include "sys_cfg.h"
#include "athos_api.h"
+#include "adf_os_io.h"
+
#if defined(PROJECT_K2)
#if SYSTEM_MODULE_SFLASH
#include "sflash_api.h"
addr &= 0xfffffffc;
//val = *(unsigned long *)addr;
- val = HAL_WORD_REG_READ(addr);
+ val = ioread32(addr);
}
else if (strcmp(cmd, "LDRH") == 0)
{
addr &= 0xfffffffe;
- val = HAL_HALF_WORD_REG_READ(addr);
+ val = ioread16(addr);
}
else if (strcmp(cmd, "LDRB") == 0)
{
if (strcmp(cmd, "STR") == 0)
{
addr &= 0xfffffffc;
- //HAL_WORD_REG_WRITE(addr, val);
- HAL_WORD_REG_WRITE(addr, val);
- //*(volatile unsigned long *)(addr & 0xfffffffc) = (unsigned long)val;
+ iowrite32(addr, val);
}
else if (strcmp(cmd, "STRH") == 0)
{
addr &= 0xfffffffe;
//*(volatile unsigned short *)(addr & 0xfffffffe) = (unsigned short)val;
- HAL_HALF_WORD_REG_WRITE(addr, val);
+ iowrite16(addr, val);
}
else if (strcmp(cmd, "STRB") == 0)
{
if( addr & 0x00f00000 )
- HAL_BYTE_REG_WRITE(addr, val);
+ iowrite8(addr, val);
else
- HAL_BYTE_REG_WRITE(addr^3, val);
+ iowrite8(addr^3, val);
//*(volatile unsigned char *)addr = (unsigned char)val;
}
break;
}
- HAL_WORD_REG_WRITE(0x50040, (0x300|clk_sel|(ratio>>1)<<12));
+ iowrite32(0x50040, (0x300|clk_sel|(ratio>>1)<<12));
A_UART_HWINIT((clk*1000*1000)/ratio, baud);
}
else if( strcmp(param1, "event") == 0 )
{
uint32_t event= 0x00123400;
-#define USB_BYTE_REG_WRITE(addr, val) HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val))
-#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3))
-
-#define USB_WORD_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val))
-#define USB_WORD_REG_READ(addr) HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr))
- // disable ep3 intr
- USB_BYTE_REG_WRITE(0x17, USB_BYTE_REG_READ(0x17)|0xc0);
+ /* disable ep3 intr */
+ iowrite8_usb(0x17, ioread8_usb(0x17)|0xc0);
- //ZM_CBUS_FIFO_SIZE_REG = 0xf;
- USB_WORD_REG_WRITE(0x100, 0x0f);
+ /* ZM_CBUS_FIFO_SIZE_REG = 0xf */
+ iowrite32_usb(0x100, 0x0f);
- //ZM_EP3_DATA_REG = event;
- USB_WORD_REG_WRITE(0xF8, event);
+ /* ZM_EP3_DATA_REG = event; */
+ iowrite32_usb(0xF8, event);
- // tx done
- USB_BYTE_REG_WRITE(0xAE, USB_BYTE_REG_READ(0xAE)|0x08);
+ /* tx done */
+ iowrite8_usb(0xAE, ioread8_usb(0xAE) | 0x08);
- // enable ep3 intr
- USB_BYTE_REG_WRITE(0x17, USB_BYTE_REG_READ(0x17)&0xbf);
+ /* enable ep3 intr */
+ iowrite8_usb(0x17, ioread8_usb(0x17) & 0xbf);
}
}
#include "athos_api.h"
#include "usbfifo_api.h"
+#include "adf_os_io.h"
#include "sys_cfg.h"
extern USB_FIFO_CONFIG usbFifoConf;
#if SYSTEM_MODULE_USB
-#define vUsb_ep0end(void) \
-{ \
- eUsbCxCommand = CMD_VOID; \
- USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); \
-}
-
-#define vUsb_ep0fail(void) USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04)
-
-#define vUsb_rst() \
-{ \
- USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
- (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT1)); \
- UsbChirpFinish = FALSE; \
-}
-
-#define vUsb_suspend() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
- (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT2))
-
-#define vUsb_resm() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
- (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT3))
#define CHECK_SOF_LOOP_CNT 50
volatile uint32_t t = 0;
volatile uint32_t sof_no=0,sof_no_new=0;
/* Set GO_TO_SUSPEND bit to USB main control register */
- vUsb_suspend();
+ io8_clr_usb(ZM_INTR_SOURCE_7_OFFSET, BIT2);
A_PRINTF("!USB suspend\n\r");
/* keep the record of suspend */
#if defined(PROJECT_MAGPIE)
- *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = SUS_MAGIC_PATTERN;
+ iowrite32(WATCH_DOG_MAGIC_PATTERN_ADDR, SUS_MAGIC_PATTERN);
#elif defined(PROJECT_K2)
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
+ iowrite32(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
#endif /* #if defined(PROJECT_MAGPIE) */
/* Reset USB FIFO */
DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1000;
+#if 0
/* reset ep3/ep4 fifo in case there
* is data which might affect resuming */
-// HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
-// HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10));
-
- {
- /* config gpio to input before goto suspend */
+ iowrite8(0x100ae, ioread8(0x100ae) | 0x10);
+ iowrite8(0x100ae, ioread8(0x100af) | 0x10);
- /* disable JTAG/ICE */
- //jtag = HAL_WORD_REG_READ(0x10004054);
- //HAL_WORD_REG_WRITE(0x10004054, (jtag|BIT17));
+ /* config gpio to input before goto suspend */
- /* disable SPI */
- //spi = HAL_WORD_REG_READ(0x50040);
- //HAL_WORD_REG_WRITE(0x50040, (spi&~(BIT8)));
+ /* disable JTAG/ICE */
+ jtag = ioread32(0x10004054);
+ iowrite32(0x10004054, jtag | BIT17);
- /* set all GPIO to input */
- gpio_in = HAL_WORD_REG_READ(0x1000404c);
- HAL_WORD_REG_WRITE(0x1000404c, 0x0);
+ /* disable SPI */
+ spi = ioread32(0x50040);
+ iowrite32(0x50040, spi & ~BIT8);
+#endif
+ /* set all GPIO to input */
+ gpio_in = ioread32(0x1000404c);
+ iowrite32(0x1000404c, 0x0);
- /* set PU/PD for all GPIO except two UART pins */
- pupd = HAL_WORD_REG_READ(0x10004088);
- HAL_WORD_REG_WRITE(0x10004088, 0xA982AA6A);
- }
+ /* set PU/PD for all GPIO except two UART pins */
+ pupd = ioread32(0x10004088);
+ iowrite32(0x10004088, 0xA982AA6A);
- sof_no= HAL_WORD_REG_READ(0x10004);
+ sof_no = ioread32(0x10004);
for (t = 0; t < CHECK_SOF_LOOP_CNT; t++)
{
A_DELAY_USECS(1000); /* delay 1ms */
- sof_no_new = HAL_WORD_REG_READ(0x10004);
+ sof_no_new = ioread32(0x10004);
if(sof_no_new == sof_no)
break;
* setting the go suspend here, power down right away!!!
*/
if (t != CHECK_SOF_LOOP_CNT) /* not time out */
- HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8));
+ io32_set(0x10000, BIT3);
DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1100;
#if 0 /* pll unstable, h/w bug? */
- HAL_WORD_REG_WRITE(0x50040, (0x300|6|(1>>1)<<12));
+ iowrite32(0x50040, 0x300 | 6 | (1>>1) << 12);
A_UART_HWINIT((40*1000*1000)/1, 19200);
-#endif
+
/* restore gpio setting */
- //HAL_WORD_REG_WRITE(0x10004054, jtag);
- //HAL_WORD_REG_WRITE(0x50040, spi);
- HAL_WORD_REG_WRITE(0x1000404c, gpio_in);
- HAL_WORD_REG_WRITE(0x10004088, pupd);
+ iowrite32(0x10004054, jtag);
+ iowrite32(0x50040, spi);
+#endif
+ iowrite32(0x1000404c, gpio_in);
+ iowrite32(0x10004088, pupd);
DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1200;
* so that reset mac can't be done in ResetFifo function,
* move to here... whole mac control reset.... (bit1)
*/
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT1));
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0));
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT1);
+ io32_set(MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0);
+ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0);
A_DELAY_USECS(1000);
- //A_PRINTF("reg(0x10020)=(%x)\n", HAL_WORD_REG_READ(0x10020));
/* disable ep3 int enable, so that resume back won't
* send wdt magic pattern out!!! */
mUSB_STATUS_IN_INT_DISABLE();
if (((DEBUG_SYSTEM_STATE&~(0x0000ffff))>>16 == 0x5342)) {
/* UART_SEL and SPI_SEL */
- HAL_WORD_REG_WRITE(0x50040, (0x300|0|(1>>1)<<12));
+ iowrite32(0x50040, 0x300 | 0 | (1 >> 1) << 12);
}
/* Jump to boot code */
register uint8_t usb_interrupt_level1;
register uint8_t usb_interrupt_level2;
- usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET);
+ usb_interrupt_level1 = ioread8_usb(ZM_INTR_GROUP_OFFSET);
#if 0 /* these endpoints are handled by DMA */
if (usb_interrupt_level1 & BIT5)
{
#endif
if (usb_interrupt_level1 & BIT4) {
usb_interrupt_level2 =
- USB_BYTE_REG_READ(ZM_INTR_SOURCE_4_OFFSET);
+ ioread8_usb(ZM_INTR_SOURCE_4_OFFSET);
if(usb_interrupt_level2 & BIT6)
A_USB_REG_OUT(); /* vUsb_Reg_Out() */
if (usb_interrupt_level1 & BIT6) {
/* zfGenWatchDogEvent(); ?? */
usb_interrupt_level2 =
- USB_BYTE_REG_READ(ZM_INTR_SOURCE_6_OFFSET);
+ ioread8_usb(ZM_INTR_SOURCE_6_OFFSET);
if(usb_interrupt_level2 & BIT6)
A_USB_STATUS_IN(); /* vUsb_Status_In() */
}
if (usb_interrupt_level1 & BIT0) {
usb_interrupt_level2 =
- USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET);
+ ioread8_usb(ZM_INTR_SOURCE_0_OFFSET);
/* refer to FUSB200, p 48, offset:21H, bit7 description,
* should clear the command abort interrupt first!?
*/
if (usb_interrupt_level2 & BIT7) {
/* Handle command abort */
- USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET,
- (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)
- & ~BIT7));
+ io8_clr_usb(ZM_INTR_SOURCE_0_OFFSET, BIT7);
A_PRINTF("![SOURCE_0] bit7 on\n\r");
}
/* vWriteUSBFakeData() */
}
- if (usb_interrupt_level2 & BIT3)
- vUsb_ep0end();
+ if (usb_interrupt_level2 & BIT3) {
+ /* vUsb_ep0end */
+ eUsbCxCommand = CMD_VOID;
+ iowrite8_usb(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
+ }
+ /* EP0 fail */
if (usb_interrupt_level2 & BIT4)
- vUsb_ep0fail();
+ iowrite8_usb(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
if (eUsbCxFinishAction == ACT_STALL) {
/* set CX_STL to stall Endpoint0 &
* will also clear FIFO0 */
- USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
+ iowrite8_usb(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
} else if (eUsbCxFinishAction == ACT_DONE) {
/* set CX_DONE to indicate the transmistion
* of control frame */
- USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
+ iowrite8_usb(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
}
eUsbCxFinishAction = ACT_IDLE;
}
if (usb_interrupt_level1 & BIT7) {
usb_interrupt_level2 =
- USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET);
+ ioread8_usb(ZM_INTR_SOURCE_7_OFFSET);
#if 0
if (usb_interrupt_level2 & BIT7)
#endif
if (usb_interrupt_level2 & BIT1) {
- vUsb_rst();
+ io8_clr_usb(ZM_INTR_SOURCE_7_OFFSET, BIT1);
+ UsbChirpFinish = FALSE;
A_PRINTF("!USB reset\n\r");
-// A_PRINTF("![0x1012c]: %\n\r", USB_WORD_REG_READ(0x12c));
}
if (usb_interrupt_level2 & BIT2) {
/* TBD: the suspend resume code should put here,
_fw_usb_suspend_reboot();
}
if (usb_interrupt_level2 & BIT3) {
- vUsb_resm();
+ io8_clr_usb(ZM_INTR_SOURCE_7_OFFSET, BIT3);
A_PRINTF("!USB resume\n\r");
}
}
void _fw_usb_reset_fifo(void)
{
- volatile uint32_t *reg_data;
-
- HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
- HAL_BYTE_REG_WRITE(0x100af, (HAL_BYTE_REG_READ(0x100af)|0x10));
+ io8_set(0x100ae, 0x10);
+ io8_set(0x100af, 0x10);
/* disable ep3 int enable, so that resume back won't
* send wdt magic pattern out!!!
* k2: MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR
* magpie: MAGPIE_REG_RST_STATUS_ADDR
*/
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
+ iowrite32(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
/*
* Before USB suspend, USB DMA must be reset(refer to Otus)
* Otus runs the following statements only
- * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0|BIT2 );
- * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 );
+ * iowrite32( MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0|BIT2 );
+ * iowrite32( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 );
* K2 must run the following statements additionally
* reg_data = (A_UINT32 *)(USB_CTRL_BASE_ADDRESS + 0x118);
* *reg_data = 0x00000000;
* *reg_data = 0x00000001;
* because of Hardware bug in K2
*/
- USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0);
+ iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0);
/* reset both usb(bit2)/wlan(bit1) dma */
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT2));
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0));
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT2);
+ io32_set(MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0);
+ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
- USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0);
+ iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0);
/* MAC warem reset */
//reg_data = (uint32_t *)(K2_REG_MAC_BASE_ADDR + 0x7000);
A_PRINTF("\n change clock to 22 and go to suspend now!");
/* UART_SEL */
- HAL_WORD_REG_WRITE(0x50040, (0x200|0|(1>>1)<<12));
+ iowrite32(0x50040, 0x200 | 0 | (1 >> 1) << 12);
A_UART_HWINIT((22*1000*1000), 19200);
}
#endif
#include "reg_defs.h"
#include "athos_api.h"
#include "usbfifo_api.h"
-
+#include "adf_os_io.h"
#include "sys_cfg.h"
#define measure_time 0
_fw_restore_dma_fifo();
/* set clock to bypass mode - 40Mhz from XTAL */
- HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4));
+ iowrite32(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, BIT0 | BIT4);
A_DELAY_USECS(100); /* wait for stable */
- HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));
+ iowrite32(MAGPIE_REG_CPU_PLL_ADDR, BIT16);
A_DELAY_USECS(100); /* wait for stable */
A_UART_HWINIT((40*1000*1000), 19200);
{
A_DELAY_USECS(10);
- HAL_WORD_REG_WRITE( 0x10ff4040, default_data[i]);
+ iowrite32(0x10ff4040, default_data[i]);
}
A_DELAY_USECS(10);
- HAL_WORD_REG_WRITE(0x10ff4044, BIT0);
+ iowrite32(0x10ff4044, BIT0);
A_PRINTF("turn_off_merlin_ep_end ......\n");
}
}
{
volatile uint32_t default_data[9];
- volatile uint32_t read_data = 0;
uint32_t i=0;
default_data[0] = 0x9248fd00;
while (1)
{
- read_data=HAL_WORD_REG_READ(0x40028);
- if( read_data & BIT31 )
+ if (ioread32(0x40028) & BIT31)
break;
}
A_DELAY_USECS(1);
- HAL_WORD_REG_WRITE( 0x40024, default_data[i]);
+ iowrite32(0x40024, default_data[i]);
}
- HAL_WORD_REG_WRITE(0x40028, BIT0);
+ iowrite32(0x40028, BIT0);
}
static void turn_off_phy_rc()
{
volatile uint32_t default_data[9];
- volatile uint32_t read_data = 0;
uint32_t i=0;
A_PRINTF("turn_off_phy_rc\n");
while (1)
{
- read_data=HAL_WORD_REG_READ(0x40028);
- if( read_data & BIT31 )
+ if (ioread32(0x40028) & BIT31)
break;
}
A_DELAY_USECS(1);
- HAL_WORD_REG_WRITE( 0x40024, default_data[i]);
+ iowrite32(0x40024, default_data[i]);
}
- HAL_WORD_REG_WRITE(0x40028, BIT0);
+ iowrite32(0x40028, BIT0);
}
volatile uint32_t gpio_func = 0x0;
{
A_PRINTF("+++ goto suspend ......\n");
- // setting the go suspend here, power down right away...
- HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8));
+ /* setting the go suspend here, power down right away */
+ io32_set(0x10000, BIT3);
A_DELAY_USECS(100);
//32clk wait for External ETH PLL stable
A_DELAY_USECS(100);
- HAL_WORD_REG_WRITE(0x52000, 0x70303);//read back 0x703f7
- HAL_WORD_REG_WRITE(0x52008, 0x0e91c);//read back 0x1e948
+ iowrite32(0x52000, 0x70303); /* read back 0x703f7 */
+ iowrite32(0x52008, 0x0e91c); /* read back 0x1e948 */
- HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(BIT0))); //0x56030
+ io32_set(MAGPIE_REG_SUSPEND_ENABLE_ADDR, BIT0);
+
// wake up, and turn on cpu, eth, pcie and usb pll
_fw_power_on();
// restore gpio and other settings
_fw_restore_dma_fifo();
- // clear suspend..................
- HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)&(~BIT0)));
- HAL_WORD_REG_WRITE(0x52028, HAL_WORD_REG_READ(0x52028)&(~(BIT8|BIT12|BIT16)));
+ /* clear suspend */
+ io32_clr(MAGPIE_REG_SUSPEND_ENABLE_ADDR, BIT0);
+ io32_clr(0x52028, BIT8 | BIT12 | BIT16);
}
/*
*/
void zfResetUSBFIFO_patch(void)
{
- A_PRINTF("0x9808 0x%x ......\n", HAL_WORD_REG_READ(0x10ff9808));
- A_PRINTF("0x7890 0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890));
- A_PRINTF("0x7890 0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890));
- A_PRINTF("0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
+ A_PRINTF("0x9808 0x%x ......\n", ioread32(0x10ff9808));
+ A_PRINTF("0x7890 0x%x ......\n", ioread32(0x10ff7890));
+ A_PRINTF("0x7890 0x%x ......\n", ioread32(0x10ff7890));
+ A_PRINTF("0x4088 0x%x ......\n", ioread32(0x10ff4088));
_fw_reset_dma_fifo();
}
static void _fw_reset_dma_fifo()
{
- HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
- HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10));
+ io8_set(0x100ae, 0x10);
+ io8_set(0x100af, 0x10);
A_PRINTF("_fw_reset_dma_fifo\n");
// disable ep3 int enable, so that resume back won't send wdt magic pattern out!!!
mUSB_STATUS_IN_INT_DISABLE();
- // update magic pattern to indicate this is a suspend
- HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, SUS_MAGIC_PATTERN);
+ /* update magic pattern to indicate this is a suspend */
+ iowrite32(WATCH_DOG_MAGIC_PATTERN_ADDR, SUS_MAGIC_PATTERN);
- A_PRINTF("org 0x4048 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048));
- A_PRINTF("org 0x404C 0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C));
- A_PRINTF("org 0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
+ A_PRINTF("org 0x4048 0x%x ......\n", ioread32(0x10ff4048));
+ A_PRINTF("org 0x404C 0x%x ......\n", ioread32(0x10ff404C));
+ A_PRINTF("org 0x4088 0x%x ......\n", ioread32(0x10ff4088));
- HAL_WORD_REG_WRITE(0x10ff4088,0xaaa6a);//1010.1010.1010.0110.1010 for UB94
- HAL_WORD_REG_WRITE(0x10ff404C,0x0);
+ /* 1010.1010.1010.0110.1010 for UB94 */
+ iowrite32(0x10ff4088, 0xaaa6a);
+ iowrite32(0x10ff404C, 0x0);
A_DELAY_USECS(1000);
- A_PRINTF("0x4048 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048));
- A_PRINTF("0x404C 0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C));
- A_PRINTF("0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
+ A_PRINTF("0x4048 0x%x ......\n", ioread32(0x10ff4048));
+ A_PRINTF("0x404C 0x%x ......\n", ioread32(0x10ff404C));
+ A_PRINTF("0x4088 0x%x ......\n", ioread32(0x10ff4088));
// turn off merlin
turn_off_merlin();
// pcie ep
A_PRINTF("turn_off_magpie_ep_start ......\n");
A_DELAY_USECS(measure_time);
- HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)|BIT0|(1<<1)));
+ io32_set(0x40040, BIT0 | BIT1);
turn_off_phy();
- HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&~(BIT0|(1<<1))));
+ io32_clr(0x40040, BIT0 | BIT1);
A_PRINTF("turn_off_magpie_ep_end ......\n");
// pcie rc
A_PRINTF("turn_off_magpie_rc_start ......\n");
A_DELAY_USECS(measure_time);
- HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&(~BIT0)));
+ io32_clr(0x40040, BIT0);
turn_off_phy_rc();
A_PRINTF("turn_off_magpie_rc_end ......down\n");
A_DELAY_USECS(measure_time);
- A_PRINTF("0x4001C %p ......\n", HAL_WORD_REG_READ(0x4001c));
- A_PRINTF("0x40040 %p ......\n", HAL_WORD_REG_READ(0x40040));
+ A_PRINTF("0x4001C %p ......\n", ioread32(0x4001c));
+ A_PRINTF("0x40040 %p ......\n", ioread32(0x40040));
- // turn off pcie_pll - power down (bit16)
- A_PRINTF(" before pwd PCIE PLL CFG:0x5601C %p ......\n", HAL_WORD_REG_READ(0x5601C));
- HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)|(BIT18)));
- A_PRINTF(" after pwd PCIE PLL CFG:0x5601C %p ......\n", HAL_WORD_REG_READ(0x5601C));
+ /* turn off pcie_pll - power down (bit16) */
+ A_PRINTF(" before pwd PCIE PLL CFG:0x5601C: 0x%08x\n",
+ ioread32(0x5601C));
+ io32_set(0x5601C, BIT18);
+ A_PRINTF(" after pwd PCIE PLL CFG:0x5601C: 0x%08x\n",
+ ioread32(0x5601C));
/* set everything to reset state?, requested by Oligo */
- HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)|(BIT13|BIT12|BIT11|BIT9|BIT7|BIT6));
+ io32_set(0x50010, BIT13 | BIT12
+ | BIT11 | BIT9 | BIT7 | BIT6);
- HAL_WORD_REG_WRITE(0x5C000, 0);
+ iowrite32(0x5C000, 0);
A_DELAY_USECS(10);
/* reset usb DMA controller */
- USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0);
+ iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0);
- HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT4)));
+ io32_set(0x50010, BIT4);
A_DELAY_USECS(5);
- HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~BIT4)));
+ io32_clr(0x50010, BIT4);
- USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0);
+ iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0);
}
static void _fw_power_off()
* 5. set SUSPEND_ENABLE
*/
- HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4)); //0x56004
+ iowrite32(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, BIT0 | BIT4);
A_DELAY_USECS(100); // wait for stable
- HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));//0x56000
+ iowrite32(MAGPIE_REG_CPU_PLL_ADDR, BIT16);
A_DELAY_USECS(100); // wait for stable
A_UART_HWINIT((40*1000*1000), 19200);
A_CLOCK_INIT(40);
- HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)|(BIT16))); //0x5600c
+ io32_set(MAGPIE_REG_ETH_PLL_ADDR, BIT16);
- HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)|(BIT4|BIT0))); //0x56010
+ io32_set(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, BIT4 | BIT0);
- HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(0x10<<8))); //0x56030
+ io32_set(MAGPIE_REG_SUSPEND_ENABLE_ADDR, 0x10 << 8);
}
static void _fw_power_on()
* 5. turn on pcie pll
*/
- HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)&(~BIT16)));
+ io32_clr(MAGPIE_REG_ETH_PLL_ADDR, BIT16);
- // deassert eth_pll bypass mode and trigger update bit
- HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)&(~(BIT4|BIT0))));
+ /* deassert eth_pll bypass mode and trigger update bit */
+ io32_clr(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, BIT4 | BIT0);
}
-#define CMD_PCI_RC_RESET_ON() HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \
- (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)| \
- (PCI_RC_PHY_SHIFT_RESET_BIT|PCI_RC_PLL_RESET_BIT|PCI_RC_PHY_RESET_BIT|PCI_RC_RESET_BIT)))
-
static void _fw_restore_dma_fifo(void)
{
- HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)&(~(BIT18))));
+ io32_clr(0x5601C, BIT18);
- // reset pcie_rc shift
- HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~(BIT10|BIT8|BIT7))));
+ /* reset pcie_rc shift */
+ io32_clr(0x50010, BIT10 | BIT8 | BIT7);
A_DELAY_USECS(1);
- HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT10|BIT8|BIT7)));
+ io32_set(0x50010, BIT10 | BIT8 | BIT7);
- // reset pci_rc phy
- CMD_PCI_RC_RESET_ON();
+ /* reset pci_rc phy */
+ io32_set(MAGPIE_REG_RST_RESET_ADDR,
+ PCI_RC_PHY_SHIFT_RESET_BIT
+ | PCI_RC_PLL_RESET_BIT | PCI_RC_PHY_RESET_BIT
+ | PCI_RC_RESET_BIT);
A_DELAY_USECS(20);
// enable dma swap function
#include "athos_api.h"
#include "usbfifo_api.h"
+#include "adf_os_io.h"
+
#include "sys_cfg.h"
#define USB_EP4_MAX_PKT_SIZE bUSB_EP_MAX_PKT_SIZE_64
{
A_PRINTF("Cold reboot initiated.");
#if defined(PROJECT_MAGPIE)
- HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, 0);
+ iowrite32(WATCH_DOG_MAGIC_PATTERN_ADDR, 0);
#elif defined(PROJECT_K2)
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, 0);
+ iowrite32(MAGPIE_REG_RST_STATUS_ADDR, 0);
#endif /* #if defined(PROJECT_MAGPIE) */
A_USB_JUMP_BOOT();
}
/* INT use EP3 */
for (count = 0; count < (reg_buf_len / 4); count++)
{
- USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
+ iowrite32_usb(ZM_EP3_DATA_OFFSET, *regaddr);
regaddr++;
}
if (remainder) {
switch(remainder) {
case 3:
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
+ iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
break;
case 2:
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
+ iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
break;
case 1:
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
+ iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
break;
}
- USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
+ iowrite32_usb(ZM_EP3_DATA_OFFSET, *regaddr);
/* Restore CBus FIFO size to word size */
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
+ iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
}
mUSB_EP3_XFER_DONE();
static BOOLEAN cmd_is_new = TRUE;
/* get the size of this transcation */
- usbfifolen = USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_LOW_OFFSET);
+ usbfifolen = ioread8_usb(ZM_EP4_BYTE_COUNT_LOW_OFFSET);
if (usbfifolen > USB_EP4_MAX_PKT_SIZE) {
A_PRINTF("EP4 FIFO Bug? Buffer is too big: %x\n", usbfifolen);
/* retrieve the data from fifo */
for(ii = 0; ii < usbfifolen; ii++) {
/* read fifo data out */
- ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET);
+ ep4_data = ioread32_usb(ZM_EP4_DATA_OFFSET);
*regaddr = ep4_data;
regaddr++;
}
* but if we return here, the ep4 fifo will be lock out,
* so that we still read them out but just drop it? */
for(ii = 0; ii < usbfifolen; ii++)
- ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET);
+ ep4_data = ioread32_usb(ZM_EP4_DATA_OFFSET);
done:
/* mUSB_STATUS_IN_INT_ENABLE(); */
#include <adf_os_io_pvt.h>
-
-/**
- * @brief Read an 8-bit register value
- *
- * @param[in] osdev platform device object
- * @param[in] addr register addr
- *
- * @return An 8-bit register value.
- */
-#define adf_os_reg_read8(osdev, addr) __adf_os_reg_read8(osdev, addr)
-
-/**
- * @brief Read a 16-bit register value
- *
- * @param[in] osdev platform device object
- * @param[in] addr register addr
- *
- * @return A 16-bit register value.
- */
-#define adf_os_reg_read16(osdev, addr) __adf_os_reg_read16(osdev, addr)
-
-/**
- * @brief Read a 32-bit register value
- *
- * @param[in] osdev platform device object
- * @param[in] addr register addr
- *
- * @return A 32-bit register value.
- */
-#define adf_os_reg_read32(osdev, addr) __adf_os_reg_read32(osdev, addr)
-
-/**
- * @brief Read a 64-bit register value
- *
- * @param[in] osdev platform device object
- * @param[in] addr register addr
- *
- * @return A 64-bit register value.
- */
-#define adf_os_reg_read64(osdev, addr) __adf_os_reg_read64(osdev, addr)
-
-/**
- * @brief Write an 8-bit value into register
- *
- * @param[in] osdev platform device object
- * @param[in] addr register addr
- * @param[in] b the 8-bit value to be written
- */
-#define adf_os_reg_write8(osdev, addr, b) __adf_os_reg_write8(osdev, addr, b)
-
-/**
- * @brief Write a 16-bit value into register
- *
- * @param[in] osdev platform device object
- * @param[in] addr register addr
- * @param[in] w the 16-bit value to be written
- */
-#define adf_os_reg_write16(osdev, addr, w) __adf_os_reg_write16(osdev, addr, w)
-
-/**
- * @brief Write a 32-bit value into register
- *
- * @param[in] osdev platform device object
- * @param[in] addr register addr
- * @param[in] l the 32-bit value to be written
- */
-#define adf_os_reg_write32(osdev, addr, l) __adf_os_reg_write32(osdev, addr, l)
-
-/**
- * @brief Write a 64-bit value into register
- *
- * @param[in] osdev platform device object
- * @param[in] addr register addr
- * @param[in] q the 64-bit value to be written
- */
-#define adf_os_reg_write64(osdev, addr, q) __adf_os_reg_write64(osdev, addr, q)
+static inline uint8_t ioread8(const volatile uint32_t addr)
+{
+ return *(const volatile uint8_t *) addr;
+}
+
+static inline uint16_t ioread16(const volatile uint32_t addr)
+{
+ return *(const volatile uint16_t *) addr;
+}
+
+static inline uint32_t ioread32(const volatile uint32_t addr)
+{
+ return *(const volatile uint32_t *) addr;
+}
+
+static inline void iowrite8(volatile uint32_t addr, const uint8_t b)
+{
+ *(volatile uint8_t *) addr = b;
+}
+
+static inline void iowrite16(volatile uint32_t addr, const uint16_t b)
+{
+ *(volatile uint16_t *) addr = b;
+}
+
+static inline void iowrite32(volatile uint32_t addr, const uint32_t b)
+{
+ *(volatile uint32_t *) addr = b;
+}
+
+static inline void io8_rmw(volatile uint32_t addr,
+ const uint8_t set, const uint8_t clr)
+{
+ uint8_t val;
+
+ val = ioread8(addr);
+ val &= ~clr;
+ val |= set;
+ iowrite8(addr, val);
+}
+
+static inline void io32_rmw(volatile uint32_t addr,
+ const uint32_t set, const uint32_t clr)
+{
+ uint32_t val;
+
+ val = ioread32(addr);
+ val &= ~clr;
+ val |= set;
+ iowrite32(addr, val);
+}
+
+/* generic functions */
+#define io8_set(addr, s) io8_rmw((addr), (s), 0)
+#define io8_clr(addr, c) io8_rmw((addr), 0, (c))
+#define io32_set(addr, s) io32_rmw((addr), (s), 0)
+#define io32_clr(addr, c) io32_rmw((addr), 0, (c))
+
+/* mac specific functions */
+#define ioread32_mac(addr) ioread32(WLAN_BASE_ADDRESS + (addr))
+#define iowrite32_mac(addr, b) iowrite32(WLAN_BASE_ADDRESS + (addr), (b))
+
+/* usb specific functions */
+#define ioread8_usb(addr) ioread8(USB_CTRL_BASE_ADDRESS | (addr)^3)
+#define ioread16_usb(addr) ioread16(USB_CTRL_BASE_ADDRESS | (addr))
+#define ioread32_usb(addr) ioread32(USB_CTRL_BASE_ADDRESS | (addr))
+
+#define iowrite8_usb(addr, b) iowrite8(USB_CTRL_BASE_ADDRESS | (addr)^3, (b))
+#define iowrite16_usb(addr, b) iowrite16(USB_CTRL_BASE_ADDRESS | (addr), (b))
+#define iowrite32_usb(addr, b) iowrite32(USB_CTRL_BASE_ADDRESS | (addr), (b))
+
+#define io8_rmw_usb(addr, s, c) \
+ io8_rmw(USB_CTRL_BASE_ADDRESS | (addr)^3, (s), (c))
+#define io8_set_usb(addr, s) \
+ io8_rmw(USB_CTRL_BASE_ADDRESS | (addr)^3, (s), 0)
+#define io8_clr_usb(addr, c) \
+ io8_rmw(USB_CTRL_BASE_ADDRESS | (addr)^3, 0, (c))
+
+#define io32_rmw_usb(addr, s, c) \
+ io32_rmw(USB_CTRL_BASE_ADDRESS | (addr), (s), (c))
+#define io32_set_usb(addr, s) io32_rmw(USB_CTRL_BASE_ADDRESS | (addr), (s), 0)
+#define io32_clr_usb(addr, c) io32_rmw(USB_CTRL_BASE_ADDRESS | (addr), 0, (c))
/**
* @brief Convert a 16-bit value from network byte order to host byte order
*/
#define adf_os_htonl(x) __adf_os_htonl(x)
-/**
- * @brief Convert a 16-bit value from CPU byte order to big-endian byte order
- */
-#define adf_os_cpu_to_be16(x) __adf_os_cpu_to_be16(x)
-
-/**
- * @brief Convert a 32-bit value from CPU byte order to big-endian byte order
- */
-#define adf_os_cpu_to_be32(x) __adf_os_cpu_to_be32(x)
-
-/**
- * @brief Convert a 64-bit value from CPU byte order to big-endian byte order
- */
-#define adf_os_cpu_to_be64(x) __adf_os_cpu_to_be64(x)
-
/**
* @brief Convert a 16-bit value from CPU byte order to little-endian byte order
*/
#define adf_os_cpu_to_le16(x) __adf_os_cpu_to_le16(x)
-/**
- * @brief Convert a 32-bit value from CPU byte order to little-endian byte order
- */
-#define adf_os_cpu_to_le32(x) __adf_os_cpu_to_le32(x)
-
-/**
- * @brief Convert a 64-bit value from CPU byte order to little-endian byte order
- */
-#define adf_os_cpu_to_le64(x) __adf_os_cpu_to_le64(x)
-
-/**
- * @brief Convert a 16-bit value from big-endian byte order to CPU byte order
- */
-#define adf_os_be16_to_cpu(x) __adf_os_be16_to_cpu(x)
-
-/**
- * @brief Convert a 32-bit value from big-endian byte order to CPU byte order
- */
-#define adf_os_be32_to_cpu(x) __adf_os_be32_to_cpu(x)
-
-/**
- * @brief Convert a 64-bit value from big-endian byte order to CPU byte order
- */
-#define adf_os_be64_to_cpu(x) __adf_os_be64_to_cpu(x)
-
-/**
- * @brief Convert a 16-bit value from little-endian byte order to CPU byte order
- */
-#define adf_os_le16_to_cpu(x) __adf_os_le16_to_cpu(x)
-
-/**
- * @brief Convert a 32-bit value from little-endian byte order to CPU byte order
- */
-#define adf_os_le32_to_cpu(x) __adf_os_le32_to_cpu(x)
-
-/**
- * @brief Convert a 64-bit value from little-endian byte order to CPU byte order
- */
-#define adf_os_le64_to_cpu(x) __adf_os_le64_to_cpu(x)
-
#endif
#define BIT_SET(bit) (1<<bit)
#define BIT_CLR(bit) (0<<bit)
-#define HAL_WORD_REG_WRITE(addr, val) \
- do { \
- (*((volatile uint32_t *)(addr&0xfffffffc))) = (uint32_t)(val); \
- } while (0)
-
-#define HAL_WORD_REG_READ(addr) (*((volatile uint32_t *)(addr&0xfffffffc)))
-
-
-#define HAL_HALF_WORD_REG_WRITE(addr, val) \
- do { \
- (*((volatile uint16_t *)(addr&0xfffffffe))) = (uint16_t)(val); \
- } while (0)
-
-#define HAL_HALF_WORD_REG_READ(addr) (*((volatile uint16_t *)(addr&0xfffffffe)))
-
-
-#define HAL_BYTE_REG_WRITE(addr, val) \
- do { \
- (*((volatile uint8_t *)(addr))) = (uint8_t)(val); \
- } while (0)
-
-#define HAL_BYTE_REG_READ(addr) (*((volatile uint8_t *)(addr)))
-
/***** REGISTER BASE ADDRESS DEFINITION *****/
#define RESET_VECTOR_ADDRESS 0x8e0000
/********************************************/
#include "k2/reg_defs.h"
-/************************* Register Process marco ************************/
-#define UART_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(UART_BASE_ADDRESS|(uint32_t)(addr), (val))
-#define UART_REG_READ(addr) HAL_WORD_REG_READ(UART_BASE_ADDRESS|(uint32_t)(addr))
-
/************************** Register deinition ***************************/
#define RBR_ADDRESS 0x00051000
#define RBR_OFFSET 0x00000000
--- /dev/null
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __SHARED_COMPILER_H
+#define __SHARED_COMPILER_H
+
+#define __noinline __attribute__((noinline))
+#define __noreturn __attribute__((noreturn))
+#define __inline __attribute__((always_inline))
+#define __hot __attribute__((hot))
+#define __cold __attribute__((cold))
+#define __unused __attribute__((unused))
+#define __force __attribute__((force))
+#define __section(s) __attribute__((section("." # s)))
+#define __aligned(a) __attribute__((aligned(a)))
+#define __packed __attribute__((packed))
+#define __visible __attribute__((externally_visible))
+
+#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+#define BUILD_BUG_ON_ZERO(e) (sizeof(char[1 - 2 * !!(e)]) - 1)
+
+#define ALIGN(x, a) __ALIGN_MASK(x, (typeof(x))(a) - 1)
+#define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
+
+#define __roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
+
+#define __must_be_array(a) \
+ BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(typeof(a), typeof(&a[0])))
+#define ARRAY_SIZE(arr) (sizeof((arr)) / sizeof((arr)[0]) + __must_be_array(arr))
+
+#define BIT(b) (1 << (b))
+#define MASK(w) (BIT(w) - 1)
+
+#undef offsetof
+#ifdef __compiler_offsetof
+# define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE, MEMBER)
+#else
+# define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+#endif
+
+#define likely(x) __builtin_expect(!!(x), 1)
+#define unlikely(x) __builtin_expect(!!(x), 0)
+
+#define min(x, y) ({ \
+ typeof(x) _min1 = (x); \
+ typeof(y) _min2 = (y); \
+ (void) (&_min1 == &_min2); \
+ _min1 < _min2 ? _min1 : _min2; })
+
+#define max(x, y) ({ \
+ typeof(x) _max1 = (x); \
+ typeof(y) _max2 = (y); \
+ (void) (&_max1 == &_max2); \
+ _max1 > _max2 ? _max1 : _max2; })
+
+#define min_t(type, x, y) ({ \
+ type __min1 = (x); \
+ type __min2 = (y); \
+ __min1 < __min2 ? __min1 : __min2; })
+
+#define max_t(type, x, y) ({ \
+ type __max1 = (x); \
+ type __max2 = (y); \
+ __max1 > __max2 ? __max1 : __max2; })
+
+
+#define container_of(ptr, type, member) ({ \
+ const typeof(((type *)0)->member) * __mptr = (ptr); \
+ (type *)(((unsigned long)__mptr - offsetof(type, member))); })
+
+#define MAX_ERRNO 4095
+
+#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
+
+static inline void *ERR_PTR(long errornr)
+{
+ return (void *) errornr;
+}
+
+static inline long PTR_ERR(const void *ptr)
+{
+ return (long) ptr;
+}
+
+static inline long IS_ERR(const void *ptr)
+{
+ return IS_ERR_VALUE((unsigned long)ptr);
+}
+
+static inline long IS_ERR_OR_NULL(const void *ptr)
+{
+ return !ptr || IS_ERR_VALUE((unsigned long)ptr);
+}
+#endif /* __SHARED_COMPILER_H */
#define BIT_SET(bit) (1<<bit)\r
#define BIT_CLR(bit) (0<<bit)\r
\r
-#define HAL_WORD_REG_WRITE(addr, val) \\r
- do { \\r
- (*((volatile uint32_t *)(addr&0xfffffffc))) = (uint32_t)(val); \\r
- } while (0)\r
-\r
-#define HAL_WORD_REG_READ(addr) (*((volatile uint32_t *)(addr&0xfffffffc)))\r
-\r
-\r
-#define HAL_HALF_WORD_REG_WRITE(addr, val) \\r
- do { \\r
- (*((volatile uint16_t *)(addr&0xfffffffe))) = (uint16_t)(val); \\r
- } while (0)\r
-\r
-#define HAL_HALF_WORD_REG_READ(addr) (*((volatile uint16_t *)(addr&0xfffffffe))) \r
-\r
-\r
-#define HAL_BYTE_REG_WRITE(addr, val) \\r
- do { \\r
- (*((volatile uint8_t *)(addr))) = (uint8_t)(val); \\r
- } while (0)\r
-\r
-#define HAL_BYTE_REG_READ(addr) (*((volatile uint8_t *)(addr))) \r
-\r
/***** REGISTER BASE ADDRESS DEFINITION *****/\r
#define RESET_VECTOR_ADDRESS 0x8e0000\r
/********************************************/\r
#include "reg_defs.h"
-/************************* Register Process marco ************************/
-#define UART_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(UART_BASE_ADDRESS|(uint32_t)(addr), (val))
-#define UART_REG_READ(addr) HAL_WORD_REG_READ(UART_BASE_ADDRESS|(uint32_t)(addr))
-
/************************** Register deinition ***************************/
#define RBR_ADDRESS 0x00051000
#define RBR_OFFSET 0x00000000
#define mADDR(addr) (*mpADDR(addr))
#define muADDR(addr) ((uint16_t) (&(addr)))
-#define USB_BYTE_REG_WRITE(addr, val) HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val))
-#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3))
-//#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr))
+#define USB_BYTE_REG_WRITE(addr, val) iowrite8_usb(addr, val)
+#define USB_BYTE_REG_READ(addr) ioread8_usb(addr)
-#define USB_HALF_WORD_REG_WRITE(addr, val) HAL_HALF_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr), (val))
-#define USB_HALF_WORD_REG_READ(addr) HAL_HALF_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr))
+#define USB_HALF_WORD_REG_WRITE(addr, val) iowrite16_usb(addr, val)
+#define USB_HALF_WORD_REG_READ(addr) ioread16_usb(addr)
-#define USB_WORD_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val))
-#define USB_WORD_REG_READ(addr) HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr))
+#define USB_WORD_REG_WRITE(addr, val) iowrite32_usb(addr, val)
+#define USB_WORD_REG_READ(addr) ioread32_usb(addr)
/************************** Register Deinition ***************************/
#include "regdump.h"
#include "usb_defs.h"
+#include "adf_os_io.h"
+
#include "init.h"
+#include <linux/compiler.h>
+
// @TODO: Should define the memory region later~
#define ALLOCRAM_START ( ((unsigned int)&_fw_image_end) + 4)
#define ALLOCRAM_SIZE ( SYS_RAM_SZIE - ( ALLOCRAM_START - SYS_D_RAM_REGION_0_BASE) - SYS_D_RAM_STACK_SIZE)
extern BOOLEAN bJumptoFlash;
extern BOOLEAN bEepromExist;
-void app_start()
+
+void __section(boot) __noreturn __visible app_start(void)
{
uint32_t rst_status;
A_HOSTIF hostif;
hostif = A_IS_HOST_PRESENT();
#if defined(PROJECT_MAGPIE)
- rst_status = *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR);
+ rst_status = ioread32(WATCH_DOG_MAGIC_PATTERN_ADDR);
#elif defined(PROJECT_K2)
- rst_status = HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR);
+ rst_status = ioread32(MAGPIE_REG_RST_STATUS_ADDR);
#endif /* #if defined(PROJECT_MAGPIE) */
#if defined(PROJECT_MAGPIE)
*((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR)=WDT_MAGIC_PATTERN;
#elif defined(PROJECT_K2)
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, WDT_MAGIC_PATTERN);
+ iowrite32(MAGPIE_REG_RST_STATUS_ADDR, WDT_MAGIC_PATTERN);
#endif /* #if defined(PROJECT_MAGPIE) */
/* intr enable would left for firmware */
_indir_tbl.htc._HTC_ControlSvcProcessMsg = HTCControlSvcProcessMsg_patch;
#endif
- if (!(USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT6)) {
+ if (!(ioread8_usb(ZM_MAIN_CTRL_OFFSET) & BIT6))
vUSBFIFO_EP6Cfg_FS_patch();
- }
#ifdef FUSION_USB_ENABLE_TX_STREAM
// For K2, enable tx stream mode
A_PRINTF("Enable Tx Stream mode: 0x%x\r\n",
- USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET));
-
- // Patch for K2 USB STREAM mode
- USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))); // disable down stream DMA mode
-
- USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
- ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6)));
+ ioread32_usb(ZM_SOC_USB_MODE_CTRL_OFFSET));
+ /* Patch for K2 USB STREAM mode */
+ /* disable down stream DMA mode */
+ io32_rmw_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, BIT6, BIT0);
#if SYSTEM_MODULE_HP_EP5
- USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
- ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)));
+ io32_set_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, BIT8);
#endif
#if SYSTEM_MODULE_HP_EP6
- USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
- ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)));
+ io32_set_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, BIT9);
#endif
- USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT0))); // enable down stream DMA mode
+ /* enable down stream DMA mode */
+ io32_set_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, BIT0);
#endif
#ifdef FUSION_USB_ENABLE_RX_STREAM
- // Patch for K2 USB STREAM mode
- USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))); // disable upstream DMA mode
- USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))); // enable upstream stream mode
-
- // K2, Set maximum IN transfer to 8K
- USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(0xcf)));
- USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(0x20)));
-
- USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT1))); // enable upstream DMA mode
-
- USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, 0xa0); // set stream mode timeout critirea
+ /* Patch for K2 USB STREAM mode */
+ /* disable upstream DMA mode and enable upstream stream mode */
+ io32_clr_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, BIT1 | BIT3);
+
+ /* K2, Set maximum IN transfer to 8K */
+ io32_rmw_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, 0x20, 0x30);
+
+ /* enable upstream DMA mode */
+ io32_set_usb(ZM_SOC_USB_MODE_CTRL_OFFSET, BIT1);
+
+ /* set stream mode timeout critirea */
+ iowrite32_usb(ZM_SOC_USB_TIME_CTRL_OFFSET, 0xa0);
#if defined(PROJECT_K2)
/*0x10004020 is vaild in k2 but could be invaild in other chip*/
- if ((HAL_WORD_REG_READ(0x10004020) & 0x2000) != 0) {
+ if ((ioread32(0x10004020) & 0x2000) != 0) {
/* disable stream mode for AR9270 */
- USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 0);
+ iowrite32_usb(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 0);
} else {
/* enable stream mode for AR9271 */
- USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 9);
+ iowrite32_usb(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 9);
}
#else
- USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 9);
+ iowrite32_usb(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 9);
#endif
#endif
}
else if (hostif == HIF_PCI )
hif_pci_patch_install(&_indir_tbl.hif);
#endif
- A_PRINTF("USB mode: 0x%x\r\n",
- USB_WORD_REG_READ(0x100));
+ A_PRINTF("USB mode: 0x%x\r\n", ioread32_usb(0x100));
// patch the clock function
if(1) {
Magpie_init();
#if MAGPIE_ENABLE_WLAN == 1
-
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT10|BIT8|BIT7|BIT6))));
+ io32_clr(MAGPIE_REG_RST_RESET_ADDR, BIT10 | BIT8 | BIT7 | BIT6);
#if defined(PROJECT_MAGPIE)
- HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT1));
+ io32_set(MAGPIE_REG_AHB_ARB_ADDR, BIT1);
#endif
wlan_pci_module_init();
#include "athos_api.h"
#include "usb_defs.h"
+#include "adf_os_io.h"
+
#if defined(PROJECT_MAGPIE)
#include "regdump.h"
extern uint32_t *init_htc_handle;
void
change_magpie_clk(void)
{
- volatile uint32_t rd_data;
-
- HAL_WORD_REG_WRITE(0x00056004, 0x11);
- rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1;
+ iowrite32(0x00056004, BIT4 | BIT0);
- /* Wait for the update bit to get cleared */
- while (rd_data)
- rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1;
+ /* Wait for the update bit (BIT0) to get cleared */
+ while (ioread32(0x00056004) & BIT0)
+ ;
/* Put the PLL into reset */
- rd_data = HAL_WORD_REG_READ(0x00050010) | (1<<1);
- HAL_WORD_REG_WRITE(0x00050010,rd_data);
+ io32_set(0x00050010, BIT1);
/*
* XXX: statically set the CPU clock to 200Mhz
*/
- /* Setting of the PLL */
- HAL_WORD_REG_WRITE(0x00056000, 0x325);//400 MHz
+ /* Setting PLL to 400MHz */
+ iowrite32(0x00056000, 0x325);
/* Pull CPU PLL out of Reset */
- rd_data = HAL_WORD_REG_READ(0x00050010) & ~(1<<1);
- HAL_WORD_REG_WRITE(0x00050010,rd_data);
+ io32_clr(0x00050010, BIT1);
A_DELAY_USECS(60); // wait for stable
/*
* AHB clk = ( CPU clk / 2 )
*/
- HAL_WORD_REG_WRITE(0x00056004, ((0x00001 | (1 << 16)|(1 << 8)))); // set plldiv to 2
- rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1;
+ iowrite32(0x00056004, 0x00001 | BIT16 | BIT8); /* set plldiv to 2 */
- while (rd_data)
- rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1;
+ while (ioread32(0x00056004) & BIT0)
+ ;
/* UART Setting */
A_UART_HWINIT((100*1000*1000), 115200);
/* phase II reset */
A_PRINTF("exception reset-phase 2\n");
- *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = WDT_MAGIC_PATTERN;
+ iowrite32(WATCH_DOG_MAGIC_PATTERN_ADDR, WDT_MAGIC_PATTERN);
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR,
- HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|(BIT10|BIT8|BIT7|BIT6));
+ io32_set(MAGPIE_REG_RST_RESET_ADDR, BIT10 | BIT8 | BIT7 | BIT6);
- HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR,
- (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT1));
+ io32_set(MAGPIE_REG_AHB_ARB_ADDR, BIT1);
- USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0);
- HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)|BIT4);
+ iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0);
+ io32_set(0x50010, BIT4);
A_DELAY_USECS(5);
- HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)&~BIT4);
+ io32_clr(0x50010, BIT4);
A_DELAY_USECS(5);
- USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0);
+ iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0);
// set clock to bypass mode - 40Mhz from XTAL
- HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4));
+ iowrite32(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, BIT0 | BIT4);
A_DELAY_USECS(100); // wait for stable
- HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));
+ iowrite32(MAGPIE_REG_CPU_PLL_ADDR, BIT16);
A_UART_HWINIT((40*1000*1000), 115200);
A_PRINTF("Cold reboot initiated.");
#if defined(PROJECT_MAGPIE)
- HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, 0);
+ iowrite32(WATCH_DOG_MAGIC_PATTERN_ADDR, 0);
#elif defined(PROJECT_K2)
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, 0);
+ iowrite32(MAGPIE_REG_RST_STATUS_ADDR, 0);
#endif /* #if defined(PROJECT_MAGPIE) */
A_USB_JUMP_BOOT();
}
{
int i;
- // reset EP4 FIFO
- USB_BYTE_REG_WRITE(ZM_EP4_BYTE_COUNT_HIGH_OFFSET, (USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_HIGH_OFFSET) | BIT4));
+ /* reset EP4 FIFO */
+ io8_set_usb(ZM_EP4_BYTE_COUNT_HIGH_OFFSET, BIT4);
for(i = 0; i < 100; i++) {}
- USB_BYTE_REG_WRITE(ZM_EP4_BYTE_COUNT_HIGH_OFFSET, (USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_HIGH_OFFSET) & ~BIT4));
+ io8_clr_usb(ZM_EP4_BYTE_COUNT_HIGH_OFFSET, BIT4);
}
LOCAL void zfGenExceptionEvent(uint32_t exccause, uint32_t pc, uint32_t badvaddr)
A_PRINTF("<Exception>Tgt Drv send an event 44332211 to Host Drv\n");
mUSB_STATUS_IN_INT_DISABLE();
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
+ iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
- USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, pattern);
- USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, exccause);
- USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, pc);
- USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, badvaddr);
+ iowrite32_usb(ZM_EP3_DATA_OFFSET, pattern);
+ iowrite32_usb(ZM_EP3_DATA_OFFSET, exccause);
+ iowrite32_usb(ZM_EP3_DATA_OFFSET, pc);
+ iowrite32_usb(ZM_EP3_DATA_OFFSET, badvaddr);
mUSB_EP3_XFER_DONE();
}
A_PRINTF("<WrongEPID>Tgt Drv send an event 44332212 to Host Drv\n");
mUSB_STATUS_IN_INT_DISABLE();
- USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
+ iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
- USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, pattern);
- USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, epid);
+ iowrite32_usb(ZM_EP3_DATA_OFFSET, pattern);
+ iowrite32_usb(ZM_EP3_DATA_OFFSET, epid);
mUSB_EP3_XFER_DONE();
}
return;
}
-void wlan_task(void)
+void __noreturn wlan_task(void)
{
loop_low=loop_high=0;
while(1) {
-#if defined(PROJECT_MAGPIE)
- if (bJumptoFlash){
- bJumptoFlash = FALSE;
- break;
- }
-#endif
-
/* update wdt timer */
A_WDT_TASK();
#define ALLOCRAM_SIZE ( SYS_RAM_SZIE - ( ALLOCRAM_START - SYS_D_RAM_REGION_0_BASE) - SYS_D_RAM_STACK_SIZE)
#include "regdump.h"
+#include <linux/compiler.h>
#define SBOOT_PATTERN 0x5342
#define IS_FLASHBOOT() (((DEBUG_SYSTEM_STATE&~(0x0000ffff))>>16==SBOOT_PATTERN))
void fatal_exception_func();
void init_mem();
-void wlan_task();
+void __noreturn wlan_task();
/*_stack_sentry = ALIGN(0x8);*/
} >dram_seg :dram_phdr
+ .boot :
+ { *(.boot) } > iram_seg :iram_phdr
+
.text :
{
_stext = .;
/*_stack_sentry = ALIGN(0x8);*/
} >dram_seg :dram_phdr
+ .boot :
+ { *(.boot) } > iram_seg :iram_phdr
+
.text :
{
_stext = .;
if (ath_hal_getcapability(ah, HAL_CAP_HT) == HAL_OK) {
for (i = 0; i < AH_TIMEOUT_11N; i++) {
- if ((OS_REG_READ(ah, reg) & mask) == val)
+ if ((ioread32_mac(reg) & mask) == val)
return AH_TRUE;
OS_DELAY(10);
}
} else {
for (i = 0; i < AH_TIMEOUT_11G; i++) {
- if ((OS_REG_READ(ah, reg) & mask) == val)
+ if ((ioread32_mac(reg) & mask) == val)
return AH_TRUE;
OS_DELAY(10);
}
#define SM(_v, _f) (((_v) << _f##_S) & _f)
#define MS(_v, _f) (((_v) & _f) >> _f##_S)
#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
- OS_REG_WRITE(_a, _r, \
- (OS_REG_READ(_a, _r) &~ _f) | (((_v) << _f##_S) & _f))
+ iowrite32_mac(_r, \
+ (ioread32_mac(_r) & ~_f) \
+ | (((_v) << _f##_S) & _f))
#define OS_REG_RMW(_a, _r, _set, _clr) \
- OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
+ iowrite32_mac(_r, \
+ (ioread32_mac(_r) & ~(_clr)) | (_set))
#define OS_REG_SET_BIT(_a, _r, _f) \
- OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | _f)
+ iowrite32_mac(_r, ioread32_mac(_r) | _f)
#define OS_REG_CLR_BIT(_a, _r, _f) \
- OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ _f)
+ iowrite32_mac(_r, ioread32_mac(_r) & ~_f)
/* wait for the register contents to have the specified value */
extern void *global_hdl;
-/*
- * Memory-mapped device register read/write. These are here
- * as routines when debugging support is enabled and/or when
- * explicitly configured to use function calls. The latter is
- * for architectures that might need to do something before
- * referencing memory (e.g. remap an i/o window).
- *
- * NB: see the comments in ah_osdep.h about byte-swapping register
- * reads and writes to understand what's going on below.
- */
-void __ahdecl
-ath_hal_reg_write_target(struct ath_hal *ah, a_uint32_t reg, a_uint32_t val)
-{
- adf_os_reg_write32(ah->ah_dev, reg, val);
-}
-
-a_uint32_t __ahdecl
-ath_hal_reg_read_target(struct ath_hal *ah, a_uint32_t reg)
-{
- a_uint32_t val;
-
- val = adf_os_reg_read32(ah->ah_dev, reg);
-
- return val;
-}
-
/*
* Delay n microseconds.
*/
#define __bswap16(_x) (_x)
#endif
-#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write_target(_ah, _reg, _val)
-#define OS_REG_READ(_ah, _reg) ath_hal_reg_read_target(_ah, _reg)
-
-extern void __ahdecl ath_hal_reg_write_target(struct ath_hal *ah,
- a_uint32_t reg, a_uint32_t val);
-extern a_uint32_t __ahdecl ath_hal_reg_read_target(struct ath_hal *ah, a_uint32_t reg);
-
#define AH_USE_EEPROM 0x00000001
extern struct ath_hal *_ath_hal_attach_tgt( a_uint32_t, HAL_SOFTC, adf_os_device_t,
a_uint32_t flags, void* status);
HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
{
- a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
+ a_uint32_t host_isr =
+ ioread32_mac(AR_INTR_ASYNC_CAUSE);
/*
* Some platforms trigger our ISR before applying power to
* the card, so make sure.
HAL_BOOL fatal_int = AH_FALSE;
a_uint32_t sync_cause;
- if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
- if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
+ if (ioread32_mac(AR_INTR_ASYNC_CAUSE)
+ & AR_INTR_MAC_IRQ) {
+ if ((ioread32_mac(AR_RTC_STATUS)
+ & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
*masked = 0;
return AH_FALSE;
}
return AH_FALSE;
}
#endif
- isr = OS_REG_READ(ah, AR_ISR_RAC);
+ isr = ioread32_mac(AR_ISR_RAC);
if (isr == 0xffffffff) {
*masked = 0;
return AH_FALSE;
if (isr & AR_ISR_BCNMISC) {
a_uint32_t s2_s;
- s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
+ s2_s = ioread32_mac(AR_ISR_S2_S);
if (s2_s & AR_ISR_S2_GTT) {
*masked |= HAL_INT_GTT;
a_uint32_t s0_s, s1_s;
*masked |= HAL_INT_TX;
- s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
- s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
+ s0_s = ioread32_mac(AR_ISR_S0_S);
+ s1_s = ioread32_mac(AR_ISR_S1_S);
ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
}
#ifndef AR9100
- sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
+ sync_cause = ioread32_mac(AR_INTR_SYNC_CAUSE);
fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
- (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
- AH_TRUE : AH_FALSE;
+ (sync_cause & (AR_INTR_SYNC_HOST1_FATAL
+ | AR_INTR_SYNC_HOST1_PERR))) ? AH_TRUE : AH_FALSE;
if (AH_TRUE == fatal_int) {
- OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
- (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
+ iowrite32_mac(AR_INTR_SYNC_CAUSE_CLR, sync_cause);
+ (void) ioread32_mac(AR_INTR_SYNC_CAUSE_CLR);
}
#endif
return AH_TRUE;
a_uint32_t mask;
if (omask & HAL_INT_GLOBAL) {
- OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
- (void) OS_REG_READ(ah, AR_IER);
+ iowrite32_mac(AR_IER, AR_IER_DISABLE);
+ (void) ioread32_mac(AR_IER);
}
mask = ints & HAL_INT_COMMON;
mask |= AR_IMR_BCNMISC;
}
- OS_REG_WRITE(ah, AR_IMR, mask);
- (void) OS_REG_READ(ah, AR_IMR);
+ iowrite32_mac(AR_IMR, mask);
+ (void) ioread32_mac(AR_IMR);
ahp->ah_maskReg = ints;
/* Re-enable interrupts if they were enabled before. */
if (ints & HAL_INT_GLOBAL) {
- OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
+ iowrite32_mac(AR_IER, AR_IER_ENABLE);
/* See explanation above... */
- (void) OS_REG_READ(ah, AR_IER);
+ (void) ioread32_mac(AR_IER);
}
- OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
- OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
- OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
+ iowrite32_mac(AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
+ iowrite32_mac(AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+ iowrite32_mac(AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
return omask;
}
{
u_int64_t tsf;
- tsf = OS_REG_READ(ah, AR_TSF_U32);
- tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
+ tsf = ioread32_mac(AR_TSF_U32);
+ tsf = (tsf << 32) | ioread32_mac(AR_TSF_L32);
return tsf;
}
/******/
void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
{
- OS_REG_WRITE(ah, AR_RXDP, rxdp);
- HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
+ iowrite32_mac(AR_RXDP, rxdp);
+ HALASSERT(ioread32_mac(AR_RXDP) == rxdp);
}
HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
{
- OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
+ iowrite32_mac(AR_CR, AR_CR_RXD); /* Set receive disable bit */
if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
return AH_FALSE;
} else {
{
a_uint32_t phybits;
- OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
+ iowrite32_mac(AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
phybits = 0;
if (bits & HAL_RX_FILTER_PHYRADAR)
phybits |= AR_PHY_ERR_RADAR;
if (bits & HAL_RX_FILTER_PHYERR)
phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
- OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
+ iowrite32_mac(AR_PHY_ERR, phybits);
if (phybits) {
- OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
+ iowrite32_mac(AR_RXCFG,
+ ioread32_mac(AR_RXCFG)
+ | AR_RXCFG_ZLFDMA);
} else {
- OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
+ iowrite32_mac(AR_RXCFG,
+ ioread32_mac(AR_RXCFG)
+ & ~AR_RXCFG_ZLFDMA);
}
}
void ar5416EnableReceive(struct ath_hal *ah)
{
- OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
+ iowrite32_mac(AR_CR, AR_CR_RXE);
}
void ar5416StopPcuReceive(struct ath_hal *ah)
* once and picked it up again...make sure the hw has moved on.
*/
if ((ands->ds_rxstatus8 & AR_RxDone) == 0
- && OS_REG_READ(ah, AR_RXDP) == pa)
+ && ioread32_mac(AR_RXDP) == pa)
return HAL_EINPROGRESS;
/*
*/
omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
- txcfg = OS_REG_READ(ah, AR_TXCFG);
+ txcfg = ioread32_mac(AR_TXCFG);
curLevel = MS(txcfg, AR_FTRIG);
newLevel = curLevel;
} else if (curLevel > MIN_TX_FIFO_THRESHOLD)
newLevel--;
if (newLevel != curLevel)
- OS_REG_WRITE(ah, AR_TXCFG,
- (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
+ iowrite32_mac(AR_TXCFG,
+ (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
/* re-enable chip interrupts */
ar5416SetInterrupts(ah, omask);
* Make sure that TXE is deasserted before setting the TXDP. If TXE
* is still asserted, setting TXDP will have no effect.
*/
- HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
+ HALASSERT((ioread32_mac(AR_Q_TXE) & (1 << q)) == 0);
- OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
+ iowrite32_mac(AR_QTXDP(q), txdp);
return AH_TRUE;
}
HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
/* Check to be sure we're not enabling a q that has its TXD bit set. */
- HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
+ HALASSERT((ioread32_mac(AR_Q_TXD) & (1 << q)) == 0);
- OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
+ iowrite32_mac(AR_Q_TXE, 1 << q);
return AH_TRUE;
}
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
- npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
+ npend = ioread32_mac(AR_QSTS(q))
+ & AR_Q_STS_PEND_FR_CNT;
if (npend == 0) {
/*
* Pending frame count (PFC) can momentarily go to zero
* while TXE remains asserted. In other words a PFC of
* zero is not sufficient to say that the queue has stopped.
*/
- if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
+ if (ioread32_mac(AR_Q_TXE) & (1 << q))
npend = 1;
}
#ifdef DEBUG
if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
- if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
+ if (ioread32_mac(AR_Q_RDYTIMESHDN)
+ & (1 << q)) {
isrPrintf("RTSD on CAB queue\n");
/* Clear the ReadyTime shutdown status bits */
- OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
+ iowrite32_mac(AR_Q_RDYTIMESHDN, 1 << q);
}
}
#endif
/*
* set txd on all queues
*/
- OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
+ iowrite32_mac(AR_Q_TXD, AR_Q_TXD_M);
/*
* set tx abort bits
/*
* clear txd
*/
- OS_REG_WRITE(ah, AR_Q_TXD, 0);
+ iowrite32_mac(AR_Q_TXD, 0);
return AH_TRUE;
}
HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
- OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
+ iowrite32_mac(AR_Q_TXD, 1 << q);
for (i = 1000; i != 0; i--) {
if (ar5416NumTxPending(ah, q) == 0)
break;
OS_DELAY(100); /* XXX get actual value */
}
- OS_REG_WRITE(ah, AR_Q_TXD, 0);
+ iowrite32_mac(AR_Q_TXD, 0);
return (i != 0);
}
{
if ((addr & 0xffffe000) == 0x2000) {
/* SEEPROM registers */
- ath_hal_reg_read_target(ah, addr);
+ ioread32_mac(addr);
if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0))
adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
- return (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
+ return ioread32_mac(0x407c) & 0x0000ffff;
} else if (addr > 0xffff)
/* SoC registers */
- return HAL_WORD_REG_READ(addr);
+ return ioread32(addr);
else
/* MAC registers */
- return ath_hal_reg_read_target(ah, addr);
+ return ioread32_mac(addr);
}
static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
if(reset_pll == 0) {
#if defined(PROJECT_K2)
/* here we write to core register */
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
/* and here to mac register */
- ath_hal_reg_write_target(ah, 0x786c,
- ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
- ath_hal_reg_write_target(ah, 0x786c,
- ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
+ iowrite32_mac(0x786c,
+ ioread32_mac(0x786c) | 0x6000000);
+ iowrite32_mac(0x786c,
+ ioread32_mac(0x786c) & (~0x6000000));
- HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
+ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
- ath_hal_reg_write_target(ah, 0x7890,
- ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
- ath_hal_reg_write_target(ah, 0x7890,
- ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
+ iowrite32_mac(0x7890,
+ ioread32_mac(0x7890) | 0x1800000);
+ iowrite32_mac(0x7890,
+ ioread32_mac(0x7890) & (~0x1800000));
#endif
reset_pll = 1;
}
a_uint32_t reg, a_uint32_t val)
{
if(reg > 0xffff) {
- HAL_WORD_REG_WRITE(reg, val);
+ iowrite32(reg, val);
#if defined(PROJECT_K2)
if(reg == 0x50040) {
static uint8_t flg=0;
if(reg == 0x7014)
ath_pll_reset_ones(ah);
- ath_hal_reg_write_target(ah, reg, val);
+ iowrite32_mac(reg, val);
}
}
} else {
*txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
- txe_val = OS_REG_READ(ah, 0x840);
+ txe_val = ioread32_mac(0x0840);
if (!(txe_val & (1<< txq->axq_qnum)))
ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
}
projects / open-ath9k-htc-firmware.git / commitdiff