and use ioread32
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
#define __adf_os_reg_read16(_dev, _addr) oops no implementation...
#define __adf_os_reg_read16(_dev, _addr) oops no implementation...
-#define __adf_os_reg_read32(_dev, _addr) *((a_uint32_t *)(WLAN_BASE_ADDRESS + _addr))
-
#define __adf_os_reg_read64(_dev, _addr) oops no implementation...
#define __adf_os_reg_write8(_dev, _addr, _val) oops no implementation...
#define __adf_os_reg_read64(_dev, _addr) oops no implementation...
#define __adf_os_reg_write8(_dev, _addr, _val) oops no implementation...
/**
* @brief Read a 32-bit register value
*
/**
* @brief Read a 32-bit register value
*
- * @param[in] osdev platform device object
* @param[in] addr register addr
*
* @return A 32-bit register value.
*/
* @param[in] addr register addr
*
* @return A 32-bit register value.
*/
-#define adf_os_reg_read32(osdev, addr) __adf_os_reg_read32(osdev, addr)
+static inline a_uint32_t ioread32(a_uint32_t addr)
+{
+ return *(const volatile a_uint32_t *) addr;
+}
+
+#define ioread32_mac(addr) ioread32(WLAN_BASE_ADDRESS + (addr))
/**
* @brief Read a 64-bit register value
/**
* @brief Read a 64-bit register value
if (ath_hal_getcapability(ah, HAL_CAP_HT) == HAL_OK) {
for (i = 0; i < AH_TIMEOUT_11N; i++) {
if (ath_hal_getcapability(ah, HAL_CAP_HT) == HAL_OK) {
for (i = 0; i < AH_TIMEOUT_11N; i++) {
- if ((OS_REG_READ(ah, reg) & mask) == val)
+ if ((ioread32_mac(reg) & mask) == val)
return AH_TRUE;
OS_DELAY(10);
}
} else {
for (i = 0; i < AH_TIMEOUT_11G; i++) {
return AH_TRUE;
OS_DELAY(10);
}
} else {
for (i = 0; i < AH_TIMEOUT_11G; i++) {
- if ((OS_REG_READ(ah, reg) & mask) == val)
+ if ((ioread32_mac(reg) & mask) == val)
return AH_TRUE;
OS_DELAY(10);
}
return AH_TRUE;
OS_DELAY(10);
}
#define MS(_v, _f) (((_v) & _f) >> _f##_S)
#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
OS_REG_WRITE(_a, _r, \
#define MS(_v, _f) (((_v) & _f) >> _f##_S)
#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
OS_REG_WRITE(_a, _r, \
- (OS_REG_READ(_a, _r) &~ _f) | (((_v) << _f##_S) & _f))
+ (ioread32_mac(_r) & ~_f) \
+ | (((_v) << _f##_S) & _f))
#define OS_REG_RMW(_a, _r, _set, _clr) \
#define OS_REG_RMW(_a, _r, _set, _clr) \
- OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
+ OS_REG_WRITE(_a, _r, \
+ (ioread32_mac(_r) & ~(_clr)) | (_set))
#define OS_REG_SET_BIT(_a, _r, _f) \
#define OS_REG_SET_BIT(_a, _r, _f) \
- OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | _f)
+ OS_REG_WRITE(_a, _r, ioread32_mac(_r) | _f)
#define OS_REG_CLR_BIT(_a, _r, _f) \
#define OS_REG_CLR_BIT(_a, _r, _f) \
- OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ _f)
+ OS_REG_WRITE(_a, _r, ioread32_mac(_r) & ~_f)
/* wait for the register contents to have the specified value */
/* wait for the register contents to have the specified value */
adf_os_reg_write32(ah->ah_dev, reg, val);
}
adf_os_reg_write32(ah->ah_dev, reg, val);
}
-a_uint32_t __ahdecl
-ath_hal_reg_read_target(struct ath_hal *ah, a_uint32_t reg)
-{
- a_uint32_t val;
-
- val = adf_os_reg_read32(ah->ah_dev, reg);
-
- return val;
-}
-
/*
* Delay n microseconds.
*/
/*
* Delay n microseconds.
*/
#endif
#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write_target(_ah, _reg, _val)
#endif
#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write_target(_ah, _reg, _val)
-#define OS_REG_READ(_ah, _reg) ath_hal_reg_read_target(_ah, _reg)
extern void __ahdecl ath_hal_reg_write_target(struct ath_hal *ah,
a_uint32_t reg, a_uint32_t val);
extern void __ahdecl ath_hal_reg_write_target(struct ath_hal *ah,
a_uint32_t reg, a_uint32_t val);
-extern a_uint32_t __ahdecl ath_hal_reg_read_target(struct ath_hal *ah, a_uint32_t reg);
#define AH_USE_EEPROM 0x00000001
extern struct ath_hal *_ath_hal_attach_tgt( a_uint32_t, HAL_SOFTC, adf_os_device_t,
#define AH_USE_EEPROM 0x00000001
extern struct ath_hal *_ath_hal_attach_tgt( a_uint32_t, HAL_SOFTC, adf_os_device_t,
HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
{
HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
{
- a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
+ a_uint32_t host_isr =
+ ioread32_mac(AR_INTR_ASYNC_CAUSE);
/*
* Some platforms trigger our ISR before applying power to
* the card, so make sure.
/*
* Some platforms trigger our ISR before applying power to
* the card, so make sure.
HAL_BOOL fatal_int = AH_FALSE;
a_uint32_t sync_cause;
HAL_BOOL fatal_int = AH_FALSE;
a_uint32_t sync_cause;
- if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
- if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
+ if (ioread32_mac(AR_INTR_ASYNC_CAUSE)
+ & AR_INTR_MAC_IRQ) {
+ if ((ioread32_mac(AR_RTC_STATUS)
+ & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
*masked = 0;
return AH_FALSE;
}
*masked = 0;
return AH_FALSE;
}
return AH_FALSE;
}
#endif
return AH_FALSE;
}
#endif
- isr = OS_REG_READ(ah, AR_ISR_RAC);
+ isr = ioread32_mac(AR_ISR_RAC);
if (isr == 0xffffffff) {
*masked = 0;
return AH_FALSE;
if (isr == 0xffffffff) {
*masked = 0;
return AH_FALSE;
if (isr & AR_ISR_BCNMISC) {
a_uint32_t s2_s;
if (isr & AR_ISR_BCNMISC) {
a_uint32_t s2_s;
- s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
+ s2_s = ioread32_mac(AR_ISR_S2_S);
if (s2_s & AR_ISR_S2_GTT) {
*masked |= HAL_INT_GTT;
if (s2_s & AR_ISR_S2_GTT) {
*masked |= HAL_INT_GTT;
a_uint32_t s0_s, s1_s;
*masked |= HAL_INT_TX;
a_uint32_t s0_s, s1_s;
*masked |= HAL_INT_TX;
- s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
- s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
+ s0_s = ioread32_mac(AR_ISR_S0_S);
+ s1_s = ioread32_mac(AR_ISR_S1_S);
ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
- sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
+ sync_cause = ioread32_mac(AR_INTR_SYNC_CAUSE);
fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
- (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
- AH_TRUE : AH_FALSE;
+ (sync_cause & (AR_INTR_SYNC_HOST1_FATAL
+ | AR_INTR_SYNC_HOST1_PERR))) ? AH_TRUE : AH_FALSE;
if (AH_TRUE == fatal_int) {
OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
if (AH_TRUE == fatal_int) {
OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
- (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
+ (void) ioread32_mac(AR_INTR_SYNC_CAUSE_CLR);
if (omask & HAL_INT_GLOBAL) {
OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
if (omask & HAL_INT_GLOBAL) {
OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
- (void) OS_REG_READ(ah, AR_IER);
+ (void) ioread32_mac(AR_IER);
}
mask = ints & HAL_INT_COMMON;
}
mask = ints & HAL_INT_COMMON;
}
OS_REG_WRITE(ah, AR_IMR, mask);
}
OS_REG_WRITE(ah, AR_IMR, mask);
- (void) OS_REG_READ(ah, AR_IMR);
+ (void) ioread32_mac(AR_IMR);
ahp->ah_maskReg = ints;
/* Re-enable interrupts if they were enabled before. */
if (ints & HAL_INT_GLOBAL) {
OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
/* See explanation above... */
ahp->ah_maskReg = ints;
/* Re-enable interrupts if they were enabled before. */
if (ints & HAL_INT_GLOBAL) {
OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
/* See explanation above... */
- (void) OS_REG_READ(ah, AR_IER);
+ (void) ioread32_mac(AR_IER);
}
OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
}
OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
- tsf = OS_REG_READ(ah, AR_TSF_U32);
- tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
+ tsf = ioread32_mac(AR_TSF_U32);
+ tsf = (tsf << 32) | ioread32_mac(AR_TSF_L32);
void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
{
OS_REG_WRITE(ah, AR_RXDP, rxdp);
void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
{
OS_REG_WRITE(ah, AR_RXDP, rxdp);
- HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
+ HALASSERT(ioread32_mac(AR_RXDP) == rxdp);
}
HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
}
HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
if (phybits) {
phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
if (phybits) {
- OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
+ OS_REG_WRITE(ah, AR_RXCFG,
+ ioread32_mac(AR_RXCFG)
+ | AR_RXCFG_ZLFDMA);
- OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
+ OS_REG_WRITE(ah, AR_RXCFG,
+ ioread32_mac(AR_RXCFG)
+ & ~AR_RXCFG_ZLFDMA);
* once and picked it up again...make sure the hw has moved on.
*/
if ((ands->ds_rxstatus8 & AR_RxDone) == 0
* once and picked it up again...make sure the hw has moved on.
*/
if ((ands->ds_rxstatus8 & AR_RxDone) == 0
- && OS_REG_READ(ah, AR_RXDP) == pa)
+ && ioread32_mac(AR_RXDP) == pa)
return HAL_EINPROGRESS;
/*
return HAL_EINPROGRESS;
/*
*/
omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
*/
omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
- txcfg = OS_REG_READ(ah, AR_TXCFG);
+ txcfg = ioread32_mac(AR_TXCFG);
curLevel = MS(txcfg, AR_FTRIG);
newLevel = curLevel;
curLevel = MS(txcfg, AR_FTRIG);
newLevel = curLevel;
* Make sure that TXE is deasserted before setting the TXDP. If TXE
* is still asserted, setting TXDP will have no effect.
*/
* Make sure that TXE is deasserted before setting the TXDP. If TXE
* is still asserted, setting TXDP will have no effect.
*/
- HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
+ HALASSERT((ioread32_mac(AR_Q_TXE) & (1 << q)) == 0);
OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
/* Check to be sure we're not enabling a q that has its TXD bit set. */
HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
/* Check to be sure we're not enabling a q that has its TXD bit set. */
- HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
+ HALASSERT((ioread32_mac(AR_Q_TXD) & (1 << q)) == 0);
OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
- npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
+ npend = ioread32_mac(AR_QSTS(q))
+ & AR_Q_STS_PEND_FR_CNT;
if (npend == 0) {
/*
* Pending frame count (PFC) can momentarily go to zero
* while TXE remains asserted. In other words a PFC of
* zero is not sufficient to say that the queue has stopped.
*/
if (npend == 0) {
/*
* Pending frame count (PFC) can momentarily go to zero
* while TXE remains asserted. In other words a PFC of
* zero is not sufficient to say that the queue has stopped.
*/
- if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
+ if (ioread32_mac(AR_Q_TXE) & (1 << q))
npend = 1;
}
#ifdef DEBUG
if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
npend = 1;
}
#ifdef DEBUG
if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
- if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
+ if (ioread32_mac(AR_Q_RDYTIMESHDN)
+ & (1 << q)) {
isrPrintf("RTSD on CAB queue\n");
/* Clear the ReadyTime shutdown status bits */
OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
isrPrintf("RTSD on CAB queue\n");
/* Clear the ReadyTime shutdown status bits */
OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
{
if ((addr & 0xffffe000) == 0x2000) {
/* SEEPROM registers */
{
if ((addr & 0xffffe000) == 0x2000) {
/* SEEPROM registers */
- ath_hal_reg_read_target(ah, addr);
if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0))
adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0))
adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
- return (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
+ return ioread32_mac(0x407c) & 0x0000ffff;
} else if (addr > 0xffff)
/* SoC registers */
return HAL_WORD_REG_READ(addr);
else
/* MAC registers */
} else if (addr > 0xffff)
/* SoC registers */
return HAL_WORD_REG_READ(addr);
else
/* MAC registers */
- return ath_hal_reg_read_target(ah, addr);
+ return ioread32_mac(addr);
}
static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
}
static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
/* and here to mac register */
ath_hal_reg_write_target(ah, 0x786c,
HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
/* and here to mac register */
ath_hal_reg_write_target(ah, 0x786c,
- ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
+ ioread32_mac(0x786c) | 0x6000000);
ath_hal_reg_write_target(ah, 0x786c,
ath_hal_reg_write_target(ah, 0x786c,
- ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
+ ioread32_mac(0x786c) & (~0x6000000));
HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
ath_hal_reg_write_target(ah, 0x7890,
HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
ath_hal_reg_write_target(ah, 0x7890,
- ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
+ ioread32_mac(0x7890) | 0x1800000);
ath_hal_reg_write_target(ah, 0x7890,
ath_hal_reg_write_target(ah, 0x7890,
- ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
+ ioread32_mac(0x7890) & (~0x1800000));
} else {
*txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
} else {
*txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
- txe_val = OS_REG_READ(ah, 0x840);
+ txe_val = ioread32_mac(0x0840);
if (!(txe_val & (1<< txq->axq_qnum)))
ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
}
if (!(txe_val & (1<< txq->axq_qnum)))
ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
}