2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <adf_os_types.h>
37 #include <adf_os_dma.h>
38 #include <adf_os_timer.h>
39 #include <adf_os_lock.h>
40 #include <adf_os_io.h>
41 #include <adf_os_mem.h>
42 #include <adf_os_util.h>
43 #include <adf_os_stdtypes.h>
44 #include <adf_os_defer.h>
45 #include <adf_os_atomic.h>
48 #include <adf_net_wcmd.h>
50 #include "if_ethersubr.h"
53 #ifdef USE_HEADERLEN_RESV
57 #include <ieee80211_var.h>
58 #include "if_athrate.h"
59 #include "if_athvar.h"
61 #include "if_ath_pci.h"
63 #define ath_tgt_free_skb adf_nbuf_free
65 #define OFDM_PLCP_BITS 22
66 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
67 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
73 #define HT_LTF(_ns) (4 * (_ns))
74 #define SYMBOL_TIME(_ns) ((_ns) << 2) // ns * 4 us
75 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) // ns * 3.6 us
77 static a_uint16_t bits_per_symbol[][2] = {
79 { 26, 54 }, // 0: BPSK
80 { 52, 108 }, // 1: QPSK 1/2
81 { 78, 162 }, // 2: QPSK 3/4
82 { 104, 216 }, // 3: 16-QAM 1/2
83 { 156, 324 }, // 4: 16-QAM 3/4
84 { 208, 432 }, // 5: 64-QAM 2/3
85 { 234, 486 }, // 6: 64-QAM 3/4
86 { 260, 540 }, // 7: 64-QAM 5/6
87 { 52, 108 }, // 8: BPSK
88 { 104, 216 }, // 9: QPSK 1/2
89 { 156, 324 }, // 10: QPSK 3/4
90 { 208, 432 }, // 11: 16-QAM 1/2
91 { 312, 648 }, // 12: 16-QAM 3/4
92 { 416, 864 }, // 13: 64-QAM 2/3
93 { 468, 972 }, // 14: 64-QAM 3/4
94 { 520, 1080 }, // 15: 64-QAM 5/6
97 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
98 owl_txq_state_t txqstate);
99 static void ath_tgt_txqaddbuf(struct ath_softc_tgt *sc, struct ath_txq *txq,
100 struct ath_buf *bf, struct ath_desc *lastds);
101 void ath_rate_findrate_11n_Hardcoded(struct ath_softc_tgt *sc,
102 struct ath_rc_series series[]);
103 void ath_buf_set_rate_Hardcoded(struct ath_softc_tgt *sc,
104 struct ath_tx_buf *bf) ;
105 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
106 struct ath_tx_buf *bf, ath_data_hdr_t *dh);
107 static void ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
108 static void ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
109 static void ath_update_stats(struct ath_softc_tgt *sc, struct ath_buf *bf);
110 void adf_print_buf(adf_nbuf_t buf);
111 static void ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid);
113 struct ath_buf * ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
114 adf_nbuf_t skb, ath_data_hdr_t *dh);
115 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
116 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb);
118 void ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
120 static void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
121 static void ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
123 extern a_int32_t ath_chainmask_sel_logic(void *);
124 static a_int32_t ath_get_pktlen(struct ath_buf *bf, a_int32_t hdrlen);
125 static void ath_tgt_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
127 typedef void (*ath_ft_set_atype_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
130 ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
133 ath_bar_tx(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, struct ath_tx_buf *bf);
135 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno);
137 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
138 ath_bufhead *bf_q, struct ath_tx_buf **bar);
141 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_atx_tid_t *tid);
143 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf);
144 static inline void ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
145 static void ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
146 static void ath_update_aggr_stats(struct ath_softc_tgt *sc, struct ath_tx_desc *ds,
147 int nframes, int nbad);
148 static inline void ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
149 static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
151 int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc,
152 struct ath_buf *bf,int datatype,
153 ath_atx_tid_t *tid, int is_burst);
155 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb)
160 adf_nbuf_peek_header(skb, &anbdata, &anblen);
162 return((struct ieee80211_frame *)anbdata);
165 #undef adf_os_cpu_to_le16
167 static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
169 return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
173 ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
177 txq = TID_TO_ACTXQ(tid->tidno);
180 if (asf_tailq_empty(&tid->buf_q))
183 ath_tgt_tx_enqueue(txq, tid);
184 ath_tgt_txq_schedule(sc, txq);
188 ath_aggr_pause_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
193 static a_uint32_t ath_pkt_duration(struct ath_softc_tgt *sc,
194 a_uint8_t rix, struct ath_tx_buf *bf,
195 a_int32_t width, a_int32_t half_gi)
197 const HAL_RATE_TABLE *rt = sc->sc_currates;
198 a_uint32_t nbits, nsymbits, duration, nsymbols;
203 pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_pktlen;
204 rc = rt->info[rix].rateCode;
207 return ath_hal_computetxtime(sc->sc_ah, rt, pktlen, rix,
210 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
211 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
212 nsymbols = (nbits + nsymbits - 1) / nsymbits;
215 duration = SYMBOL_TIME(nsymbols);
217 duration = SYMBOL_TIME_HALFGI(nsymbols);
219 streams = HT_RC_2_STREAMS(rc);
220 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
225 static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_buf *bf)
227 adf_nbuf_t skb = bf->bf_skb;
229 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
230 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
233 static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_buf *bf)
235 adf_nbuf_t skb = bf->bf_skb;
237 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
238 adf_nbuf_unmap( sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
241 static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
243 struct ath_desc *ds0, *ds = bf->bf_desc;
247 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
249 for (i = 0; i < bf->bf_dmamap_info.nsegs; i++, ds++) {
251 ds->ds_data = bf->bf_dmamap_info.dma_segs[i].paddr;
253 if (i == (bf->bf_dmamap_info.nsegs - 1)) {
257 ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
259 ath_hal_filltxdesc(sc->sc_ah, ds
260 , bf->bf_dmamap_info.dma_segs[i].len
262 , i == (bf->bf_dmamap_info.nsegs - 1)
267 static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
269 struct ath_desc *ds = bf->bf_desc;
271 switch (bf->bf_protmode) {
272 case IEEE80211_PROT_RTSCTS:
273 bf->bf_flags |= HAL_TXDESC_RTSENA;
275 case IEEE80211_PROT_CTSONLY:
276 bf->bf_flags |= HAL_TXDESC_CTSENA;
282 ath_hal_set11n_txdesc(sc->sc_ah, ds
288 , bf->bf_flags | HAL_TXDESC_INTREQ);
290 ath_filltxdesc(sc, bf);
293 static struct ath_buf *ath_buf_toggle(struct ath_softc_tgt *sc,
294 struct ath_tx_buf *bf,
297 struct ath_tx_buf *tmp = NULL;
298 adf_nbuf_t buf = NULL;
300 adf_os_assert(sc->sc_txbuf_held != NULL);
302 tmp = sc->sc_txbuf_held;
305 ath_dma_unmap(sc, bf);
306 adf_nbuf_queue_init(&tmp->bf_skbhead);
307 buf = adf_nbuf_queue_remove(&bf->bf_skbhead);
309 adf_nbuf_queue_add(&tmp->bf_skbhead, buf);
311 adf_os_assert(adf_nbuf_queue_len(&bf->bf_skbhead) == 0);
313 tmp->bf_next = bf->bf_next;
314 tmp->bf_endpt = bf->bf_endpt;
315 tmp->bf_tidno = bf->bf_tidno;
316 tmp->bf_skb = bf->bf_skb;
317 tmp->bf_node = bf->bf_node;
318 tmp->bf_isaggr = bf->bf_isaggr;
319 tmp->bf_flags = bf->bf_flags;
320 tmp->bf_state = bf->bf_state;
321 tmp->bf_retries = bf->bf_retries;
322 tmp->bf_comp = bf->bf_comp;
323 tmp->bf_nframes = bf->bf_nframes;
324 tmp->bf_cookie = bf->bf_cookie;
336 ath_dma_map(sc, tmp);
337 ath_tx_tgt_setds(sc, tmp);
340 sc->sc_txbuf_held = bf;
345 static void ath_tgt_skb_free(struct ath_softc_tgt *sc,
346 adf_nbuf_queue_t *head,
347 HTC_ENDPOINT_ID endpt)
351 while (adf_nbuf_queue_len(head) != 0) {
352 tskb = adf_nbuf_queue_remove(head);
353 ath_free_tx_skb(sc->tgt_htc_handle,endpt,tskb);
357 static void ath_buf_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
359 ath_dma_unmap(sc, bf);
360 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
363 bf = ath_buf_toggle(sc, bf, 0);
365 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
369 static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
371 struct ath_hal *ah = sc->sc_ah;
372 const HAL_RATE_TABLE *rt;
373 struct ath_desc *ds = bf->bf_desc;
374 HAL_11N_RATE_SERIES series[4];
376 a_uint8_t rix, cix, rtsctsrate;
377 a_uint32_t aggr_limit_with_rts;
378 a_uint32_t ctsduration = 0;
379 a_int32_t prot_mode = AH_FALSE;
381 rt = sc->sc_currates;
382 rix = bf->bf_rcs[0].rix;
383 flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA));
384 cix = rt->info[sc->sc_protrix].controlRate;
386 if (bf->bf_protmode != IEEE80211_PROT_NONE &&
387 (rt->info[rix].phy == IEEE80211_T_OFDM ||
388 rt->info[rix].phy == IEEE80211_T_HT) &&
389 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
390 cix = rt->info[sc->sc_protrix].controlRate;
393 if (ath_hal_htsupported(ah) && (!bf->bf_ismcast))
394 flags = HAL_TXDESC_RTSENA;
397 if (bf->bf_rcs[i].tries) {
398 cix = rt->info[bf->bf_rcs[i].rix].controlRate;
405 ath_hal_getrtsaggrlimit(sc->sc_ah, &aggr_limit_with_rts);
407 if (bf->bf_isaggr && aggr_limit_with_rts &&
408 bf->bf_al > aggr_limit_with_rts) {
409 flags &= ~(HAL_TXDESC_RTSENA);
412 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES) * 4);
414 for (i = 0; i < 4; i++) {
415 if (!bf->bf_rcs[i].tries)
418 rix = bf->bf_rcs[i].rix;
420 series[i].Rate = rt->info[rix].rateCode |
421 (bf->bf_shpream ? rt->info[rix].shortPreamble : 0);
423 series[i].Tries = bf->bf_rcs[i].tries;
425 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
426 HAL_RATESERIES_RTS_CTS : 0 ) |
427 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
428 HAL_RATESERIES_2040 : 0 ) |
429 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
430 HAL_RATESERIES_HALFGI : 0 ) |
431 ((bf->bf_rcs[i].flags & ATH_RC_TX_STBC_FLAG) ?
432 HAL_RATESERIES_STBC: 0);
434 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
435 HAL_RATESERIES_RTS_CTS : 0 ) |
436 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
437 HAL_RATESERIES_2040 : 0 ) |
438 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
439 HAL_RATESERIES_HALFGI : 0 );
441 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
442 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
443 (bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG));
445 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
448 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
450 if (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG)
451 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
454 rtsctsrate = rt->info[cix].rateCode |
455 (bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
457 ath_hal_set11n_ratescenario(ah, ds, 1,
458 rtsctsrate, ctsduration,
463 static void ath_tgt_rate_findrate(struct ath_softc_tgt *sc,
464 struct ath_node_target *an,
465 a_int32_t shortPreamble,
471 struct ath_rc_series series[],
474 ath_rate_findrate(sc, an, 1, frameLen, 10, 4, 1,
475 ATH_RC_PROBE_ALLOWED, series, isProbe);
478 static void owl_tgt_tid_init(struct ath_atx_tid *tid)
482 tid->seq_start = tid->seq_next = 0;
483 tid->baw_size = WME_MAX_BA;
484 tid->baw_head = tid->baw_tail = 0;
487 tid->sched = AH_FALSE;
489 asf_tailq_init(&tid->buf_q);
491 for (i = 0; i < ATH_TID_MAX_BUFS; i++) {
492 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, i);
496 static void owl_tgt_tid_cleanup(struct ath_softc_tgt *sc,
497 struct ath_atx_tid *tid)
504 tid->flag &= ~TID_CLEANUP_INPROGRES;
506 if (tid->flag & TID_REINITIALIZE) {
507 adf_os_print("TID REINIT DONE for tid %p\n", tid);
508 tid->flag &= ~TID_REINITIALIZE;
509 owl_tgt_tid_init(tid);
511 ath_aggr_resume_tid(sc, tid);
515 void owl_tgt_node_init(struct ath_node_target * an)
517 struct ath_atx_tid *tid;
520 for (tidno = 0, tid = &an->tid[tidno]; tidno < WME_NUM_TID;tidno++, tid++) {
524 if ( tid->flag & TID_CLEANUP_INPROGRES ) {
525 tid->flag |= TID_REINITIALIZE;
526 adf_os_print("tid[%p]->incomp is not 0: %d\n",
529 owl_tgt_tid_init(tid);
534 void ath_tx_status_clear(struct ath_softc_tgt *sc)
538 for (i = 0; i < 2; i++) {
539 sc->tx_status[i].cnt = 0;
543 struct WMI_TXSTATUS_EVENT* ath_tx_status_get(struct ath_softc_tgt *sc)
545 WMI_TXSTATUS_EVENT *txs = NULL;
548 for (i = 0; i < 2; i++) {
549 if (sc->tx_status[i].cnt < HTC_MAX_TX_STATUS) {
550 txs = &sc->tx_status[i];
558 void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
560 struct ath_tx_desc *ds = bf->bf_lastds;
561 WMI_TXSTATUS_EVENT *txs;
563 if (sc->sc_tx_draining)
566 txs = ath_tx_status_get(sc);
570 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
571 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
573 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
574 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_FILT;
576 if (!(ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) &&
577 !(ds->ds_txstat.ts_status & HAL_TXERR_FIFO) &&
578 !(ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED) &&
579 !(ds->ds_txstat.ts_status & HAL_TXERR_FILT))
580 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
582 ath_tx_status_update_rate(sc, bf->bf_rcs, ds->ds_txstat.ts_rate, txs);
587 void ath_tx_status_update_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
588 struct ath_tx_desc *ds, struct ath_rc_series rcs[],
591 WMI_TXSTATUS_EVENT *txs;
593 if (sc->sc_tx_draining)
596 txs = ath_tx_status_get(sc);
600 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
601 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
604 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
607 ath_tx_status_update_rate(sc, rcs, ds->ds_txstat.ts_rate, txs);
612 void ath_tx_status_send(struct ath_softc_tgt *sc)
616 if (sc->sc_tx_draining)
619 for (i = 0; i < 2; i++) {
620 if (sc->tx_status[i].cnt) {
621 wmi_event(sc->tgt_wmi_handle, WMI_TXSTATUS_EVENTID,
622 &sc->tx_status[i], sizeof(WMI_TXSTATUS_EVENT));
623 /* FIXME: Handle failures. */
624 sc->tx_status[i].cnt = 0;
629 static void owltgt_tx_process_cabq(struct ath_softc_tgt *sc, struct ath_txq *txq)
631 ath_hal_intrset(sc->sc_ah, sc->sc_imask & ~HAL_INT_SWBA);
632 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
633 ath_hal_intrset(sc->sc_ah, sc->sc_imask);
636 void owl_tgt_tx_tasklet(TQUEUE_ARG data)
638 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
642 ath_tx_status_clear(sc);
644 for (i = 0; i < (HAL_NUM_TX_QUEUES - 6); i++) {
645 txq = ATH_TXQ(sc, i);
647 if (ATH_TXQ_SETUP(sc, i)) {
648 if (txq == sc->sc_cabq)
649 owltgt_tx_process_cabq(sc, txq);
651 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
655 ath_tx_status_send(sc);
658 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
659 owl_txq_state_t txqstate)
661 struct ath_tx_buf *bf;
662 struct ath_tx_desc *ds;
666 if (asf_tailq_empty(&txq->axq_q)) {
667 txq->axq_link = NULL;
668 txq->axq_linkbuf = NULL;
672 bf = asf_tailq_first(&txq->axq_q);
675 status = ath_hal_txprocdesc(sc->sc_ah, ds);
677 if (status == HAL_EINPROGRESS) {
678 if (txqstate == OWL_TXQ_ACTIVE)
680 else if (txqstate == OWL_TXQ_STOPPED) {
681 __stats(sc, tx_stopfiltered);
682 ds->ds_txstat.ts_flags = 0;
683 ds->ds_txstat.ts_status = HAL_OK;
685 ds->ds_txstat.ts_flags = HAL_TX_SW_FILTERED;
689 ATH_TXQ_REMOVE_HEAD(txq, bf, bf_list);
690 if ((asf_tailq_empty(&txq->axq_q))) {
691 __stats(sc, tx_qnull);
692 txq->axq_link = NULL;
693 txq->axq_linkbuf = NULL;
699 ath_tx_status_update(sc, bf);
700 ath_buf_comp(sc, bf);
703 if (txqstate == OWL_TXQ_ACTIVE) {
704 ath_tgt_txq_schedule(sc, txq);
709 static struct ieee80211_frame* ATH_SKB2_WH(adf_nbuf_t skb)
714 adf_nbuf_peek_header(skb, &anbdata, &anblen);
715 return((struct ieee80211_frame *)anbdata);
719 ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid)
721 struct ath_tx_buf *bf;
723 while (!asf_tailq_empty(&tid->buf_q)) {
724 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
725 ath_tx_freebuf(sc, bf);
728 tid->seq_next = tid->seq_start;
729 tid->baw_tail = tid->baw_head;
732 static void ath_tgt_tx_comp_normal(struct ath_softc_tgt *sc,
733 struct ath_tx_buf *bf)
735 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
736 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
738 if (tid->flag & TID_CLEANUP_INPROGRES) {
739 owl_tgt_tid_cleanup(sc, tid);
743 ath_tx_uc_comp(sc, bf);
746 ath_tx_freebuf(sc, bf);
749 static struct ieee80211_node_target * ath_tgt_find_node(struct ath_softc_tgt *sc,
750 a_int32_t node_index)
752 struct ath_node_target *an;
753 struct ieee80211_node_target *ni;
755 if (node_index > TARGET_NODE_MAX)
758 an = &sc->sc_sta[node_index];
762 if (ni->ni_vap == NULL) {
771 static struct ath_buf* ath_buf_alloc(struct ath_softc_tgt *sc)
773 struct ath_tx_buf *bf = NULL;
775 bf = asf_tailq_first(&sc->sc_txbuf);
777 adf_os_mem_set(&bf->bf_state, 0, sizeof(struct ath_buf_state));
778 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
786 struct ath_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
787 adf_nbuf_t skb, ath_data_hdr_t *dh)
789 struct ath_tx_buf *bf;
790 struct ieee80211_node_target *ni;
791 struct ath_atx_tid *tid;
793 ni = ath_tgt_find_node(sc, dh->ni_index);
797 tid = ATH_AN_2_TID(ATH_NODE_TARGET(ni), dh->tidno);
798 if (tid->flag & TID_REINITIALIZE) {
799 adf_os_print("drop frame due to TID reinit\n");
803 bf = ath_buf_alloc(sc);
805 __stats(sc, tx_nobufs);
809 bf->bf_tidno = dh->tidno;
810 bf->bf_txq = TID_TO_ACTXQ(bf->bf_tidno);
811 bf->bf_keytype = dh->keytype;
812 bf->bf_keyix = dh->keyix;
813 bf->bf_protmode = dh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
814 bf->bf_node = (struct ath_node_target *)ni;
816 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
817 skb = adf_nbuf_queue_first(&(bf->bf_skbhead));
819 if (adf_nbuf_queue_len(&(bf->bf_skbhead)) == 0) {
820 __stats(sc, tx_noskbs);
828 ath_tgt_txbuf_setup(sc, bf, dh);
830 ath_tx_tgt_setds(sc, bf);
835 static void ath_tgt_tx_seqno_normal(struct ath_tx_buf *bf)
837 struct ieee80211_node_target *ni = bf->bf_node;
838 struct ath_node_target *an = ATH_NODE_TARGET(ni);
839 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
840 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
842 u_int8_t fragno = (wh->i_seq[0] & 0xf);
844 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
846 bf->bf_seqno = (tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
848 *(u_int16_t *)wh->i_seq = adf_os_cpu_to_le16(bf->bf_seqno);
849 wh->i_seq[0] |= fragno;
851 if (!(wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG))
852 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
855 static a_int32_t ath_key_setup(struct ieee80211_node_target *ni,
856 struct ath_tx_buf *bf)
858 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
860 if (!(wh->i_fc[1] & IEEE80211_FC1_WEP)) {
861 bf->bf_keytype = HAL_KEY_TYPE_CLEAR;
862 bf->bf_keyix = HAL_TXKEYIX_INVALID;
866 switch (bf->bf_keytype) {
867 case HAL_KEY_TYPE_WEP:
868 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
870 case HAL_KEY_TYPE_AES:
871 bf->bf_pktlen += IEEE80211_WEP_MICLEN;
873 case HAL_KEY_TYPE_TKIP:
874 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
880 if (bf->bf_keytype == HAL_KEY_TYPE_AES ||
881 bf->bf_keytype == HAL_KEY_TYPE_TKIP)
882 ieee80211_tgt_crypto_encap(wh, ni, bf->bf_keytype);
887 static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
889 struct ath_hal *ah = sc->sc_ah;
892 volatile a_int32_t txe_val;
898 status = ath_hal_txprocdesc(sc->sc_ah, bf->bf_lastds);
900 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
902 if (txq->axq_link == NULL) {
903 ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
905 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
907 txe_val = OS_REG_READ(ah, 0x840);
908 if (!(txe_val & (1<< txq->axq_qnum)))
909 ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
912 txq->axq_link = &bf->bf_lastds->ds_link;
913 ath_hal_txstart(ah, txq->axq_qnum);
916 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
917 struct ath_tx_buf *bf,
921 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
922 struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb);
923 struct ieee80211_node_target *ni = (struct ieee80211_node_target *)an;
924 struct ieee80211vap_target *vap = ni->ni_vap;
925 struct ieee80211com_target *ic = &sc->sc_ic;
926 a_int32_t retval, fragno = 0;
927 a_uint32_t flags = adf_os_ntohl(dh->flags);
929 ath_tgt_tx_seqno_normal(bf);
931 bf->bf_txq_add = ath_tgt_txq_add_ucast;
932 bf->bf_hdrlen = ieee80211_anyhdrsize(wh);
933 bf->bf_pktlen = ath_get_pktlen(bf, bf->bf_hdrlen);
934 bf->bf_ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
936 if ((retval = ath_key_setup(bf->bf_node, bf)) < 0)
939 if (flags & ATH_SHORT_PREAMBLE)
940 bf->bf_shpream = AH_TRUE;
942 bf->bf_shpream = AH_FALSE;
944 bf->bf_flags = HAL_TXDESC_CLRDMASK;
945 bf->bf_atype = HAL_PKT_TYPE_NORMAL;
951 ath_get_pktlen(struct ath_buf *bf, a_int32_t hdrlen)
953 adf_nbuf_t skb = bf->bf_skb;
956 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
957 pktlen = adf_nbuf_len(skb);
959 pktlen -= (hdrlen & 3);
960 pktlen += IEEE80211_CRC_LEN;
966 ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
968 struct ath_node_target *an = bf->bf_node;
969 struct ath_rc_series rcs[4];
970 struct ath_rc_series mrcs[4];
971 a_int32_t shortPreamble = 0;
972 a_int32_t isProbe = 0;
974 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4 );
975 adf_os_mem_set(mrcs, 0, sizeof(struct ath_rc_series)*4 );
977 if (!bf->bf_ismcast) {
978 ath_tgt_rate_findrate(sc, an, shortPreamble,
981 memcpy(bf->bf_rcs, rcs, sizeof(rcs));
983 mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0;
984 mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0;
988 memcpy(bf->bf_rcs, mrcs, sizeof(mrcs));
991 ath_buf_set_rate(sc, bf);
992 bf->bf_txq_add(sc, bf);
996 ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
999 struct ath_desc *bfd = NULL;
1001 for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
1002 ath_hal_clr11n_aggr(sc->sc_ah, bfd);
1003 ath_hal_set11n_burstduration(sc->sc_ah, bfd, 0);
1004 ath_hal_set11n_virtualmorefrag(sc->sc_ah, bfd, 0);
1007 ath_dma_unmap(sc, bf);
1009 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
1015 bf = ath_buf_toggle(sc, bf, 0);
1017 bf->bf_isretried = 0;
1020 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
1024 ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1026 ath_tx_status_update(sc, bf);
1027 ath_update_stats(sc, bf);
1028 ath_rate_tx_complete(sc, ATH_NODE_TARGET(bf->bf_node),
1029 bf->bf_lastds, bf->bf_rcs, 1, 0);
1033 ath_update_stats(struct ath_softc_tgt *sc, struct ath_buf *bf)
1035 struct ath_tx_desc *ds = bf->bf_desc;
1038 if (ds->ds_txstat.ts_status == 0) {
1039 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
1040 sc->sc_tx_stats.ast_tx_altrate++;
1042 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
1043 sc->sc_tx_stats.ast_tx_xretries++;
1044 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
1045 sc->sc_tx_stats.ast_tx_fifoerr++;
1046 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
1047 sc->sc_tx_stats.ast_tx_filtered++;
1048 if (ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED)
1049 sc->sc_tx_stats.ast_tx_timer_exp++;
1051 sr = ds->ds_txstat.ts_shortretry;
1052 lr = ds->ds_txstat.ts_longretry;
1053 sc->sc_tx_stats.ast_tx_shortretry += sr;
1054 sc->sc_tx_stats.ast_tx_longretry += lr;
1058 ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
1059 HTC_ENDPOINT_ID endpt)
1061 struct ieee80211_node_target *ni;
1062 struct ieee80211vap_target *vap;
1063 struct ath_vap_target *avp;
1064 struct ath_hal *ah = sc->sc_ah;
1065 a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
1066 a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration;
1067 a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
1068 struct ath_desc *ds=NULL;
1069 struct ath_txq *txq=NULL;
1070 struct ath_tx_buf *bf;
1072 const HAL_RATE_TABLE *rt;
1073 HAL_BOOL shortPreamble;
1074 struct ieee80211_frame *wh;
1075 struct ath_rc_series rcs[4];
1076 HAL_11N_RATE_SERIES series[4];
1081 adf_nbuf_peek_header(skb, &data, &len);
1082 adf_nbuf_pull_head(skb, sizeof(ath_mgt_hdr_t));
1084 adf_nbuf_peek_header(hdr_buf, &data, &len);
1087 adf_os_assert(len >= sizeof(ath_mgt_hdr_t));
1089 mh = (ath_mgt_hdr_t *)data;
1090 adf_nbuf_peek_header(skb, &data, &len);
1091 wh = (struct ieee80211_frame *)data;
1093 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4);
1094 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES)*4);
1096 bf = asf_tailq_first(&sc->sc_txbuf);
1100 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
1102 ni = ath_tgt_find_node(sc, mh->ni_index);
1106 bf->bf_endpt = endpt;
1107 bf->bf_cookie = mh->cookie;
1108 bf->bf_protmode = mh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
1109 txq = &sc->sc_txq[1];
1110 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1111 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1112 hdrlen = ieee80211_anyhdrsize(wh);
1114 keyix = HAL_TXKEYIX_INVALID;
1115 pktlen -= (hdrlen & 3);
1116 pktlen += IEEE80211_CRC_LEN;
1121 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
1124 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
1127 rt = sc->sc_currates;
1128 adf_os_assert(rt != NULL);
1130 if (mh->flags == ATH_SHORT_PREAMBLE)
1131 shortPreamble = AH_TRUE;
1133 shortPreamble = AH_FALSE;
1135 flags = HAL_TXDESC_CLRDMASK;
1137 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1138 case IEEE80211_FC0_TYPE_MGT:
1139 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1141 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1142 atype = HAL_PKT_TYPE_PROBE_RESP;
1143 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1144 atype = HAL_PKT_TYPE_ATIM;
1146 atype = HAL_PKT_TYPE_NORMAL;
1150 atype = HAL_PKT_TYPE_NORMAL;
1154 avp = &sc->sc_vap[mh->vap_index];
1156 rcs[0].rix = ath_get_minrateidx(sc, avp);
1157 rcs[0].tries = ATH_TXMAXTRY;
1160 adf_os_mem_copy(bf->bf_rcs, rcs, sizeof(rcs));
1162 try0 = rcs[0].tries;
1163 txrate = rt->info[rix].rateCode;
1166 txrate |= rt->info[rix].shortPreamble;
1173 flags |= HAL_TXDESC_NOACK;
1175 } else if (pktlen > vap->iv_rtsthreshold) {
1176 flags |= HAL_TXDESC_RTSENA;
1177 cix = rt->info[rix].controlRate;
1180 if ((bf->bf_protmode != IEEE80211_PROT_NONE) &&
1181 rt->info[rix].phy == IEEE80211_T_OFDM &&
1182 (flags & HAL_TXDESC_NOACK) == 0) {
1183 cix = rt->info[sc->sc_protrix].controlRate;
1184 sc->sc_tx_stats.ast_tx_protect++;
1187 *(a_uint16_t *)&wh->i_seq[0] = adf_os_cpu_to_le16(ni->ni_txseqmgmt <<
1188 IEEE80211_SEQ_SEQ_SHIFT);
1189 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
1192 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
1193 adf_os_assert(cix != 0xff);
1194 ctsrate = rt->info[cix].rateCode;
1195 if (shortPreamble) {
1196 ctsrate |= rt->info[cix].shortPreamble;
1197 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1198 ctsduration += rt->info[cix].spAckDuration;
1199 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1200 ctsduration += rt->info[cix].spAckDuration;
1202 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1203 ctsduration += rt->info[cix].lpAckDuration;
1204 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1205 ctsduration += rt->info[cix].lpAckDuration;
1207 ctsduration += ath_hal_computetxtime(ah,
1208 rt, pktlen, rix, shortPreamble);
1213 flags |= HAL_TXDESC_INTREQ;
1215 ath_hal_setuptxdesc(ah, ds
1228 , ATH_COMP_PROC_NO_COMP_NO_CCS);
1230 bf->bf_flags = flags;
1233 * Set key type in tx desc while sending the encrypted challenge to AP
1234 * in Auth frame 3 of Shared Authentication, owl needs this.
1236 if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
1237 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
1238 ath_hal_fillkeytxdesc(ah, ds, mh->keytype);
1240 ath_filltxdesc(sc, bf);
1242 for (i=0; i<4; i++) {
1243 series[i].Tries = 2;
1244 series[i].Rate = txrate;
1245 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
1246 series[i].RateFlags = 0;
1248 ath_hal_set11n_ratescenario(ah, ds, 0, ctsrate, ctsduration, series, 4, 0);
1249 ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
1253 HTC_ReturnBuffers(sc->tgt_htc_handle, endpt, skb);
1258 ath_tgt_txqaddbuf(struct ath_softc_tgt *sc,
1259 struct ath_txq *txq, struct ath_buf *bf,
1260 struct ath_desc *lastds)
1262 struct ath_hal *ah = sc->sc_ah;
1264 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
1266 if (txq->axq_link == NULL) {
1267 ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
1269 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1272 txq->axq_link = &lastds->ds_link;
1273 ath_hal_txstart(ah, txq->axq_qnum);
1276 void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1279 struct ath_node_target *an;
1281 an = (struct ath_node_target *)bf->bf_node;
1284 tid = &an->tid[bf->bf_tidno];
1287 bf->bf_comp = ath_tgt_tx_comp_normal;
1288 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1289 ath_tgt_tx_send_normal(sc, bf);
1293 ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid)
1301 tid->sched = AH_TRUE;
1302 asf_tailq_insert_tail(&txq->axq_tidq, tid, tid_qelem);
1306 ath_tgt_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1308 struct ath_atx_tid *tid;
1314 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
1319 tid->sched = AH_FALSE;
1324 if (!(tid->flag & TID_AGGR_ENABLED))
1325 ath_tgt_tx_sched_normal(sc,tid);
1327 ath_tgt_tx_sched_aggr(sc,tid);
1331 if (!asf_tailq_empty(&tid->buf_q)) {
1332 ath_tgt_tx_enqueue(txq, tid);
1335 } while (!asf_tailq_empty(&txq->axq_tidq) && !bdone);
1339 ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1342 struct ath_node_target *an;
1343 struct ath_txq *txq = bf->bf_txq;
1344 a_bool_t queue_frame, within_baw;
1346 an = (struct ath_node_target *)bf->bf_node;
1349 tid = &an->tid[bf->bf_tidno];
1352 bf->bf_comp = ath_tgt_tx_comp_aggr;
1354 within_baw = BAW_WITHIN(tid->seq_start, tid->baw_size,
1355 SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1357 queue_frame = ( (txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) ||
1358 (!asf_tailq_empty(&tid->buf_q)) ||
1359 (tid->paused) || (!within_baw) );
1362 asf_tailq_insert_tail(&tid->buf_q, bf, bf_list);
1363 ath_tgt_tx_enqueue(txq, tid);
1365 ath_tx_addto_baw(tid, bf);
1366 __stats(sc, txaggr_nframes);
1367 ath_tgt_tx_send_normal(sc, bf);
1372 ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1375 struct ath_txq *txq =TID_TO_ACTXQ(tid->tidno);;
1378 if (asf_tailq_empty(&tid->buf_q))
1381 bf = asf_tailq_first(&tid->buf_q);
1382 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1383 ath_tgt_tx_send_normal(sc, bf);
1385 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH);
1389 ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1391 struct ath_tx_buf *bf, *bf_last;
1392 ATH_AGGR_STATUS status;
1394 struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno);
1395 struct ath_desc *ds = NULL;
1399 if (asf_tailq_empty(&tid->buf_q))
1403 if (asf_tailq_empty(&tid->buf_q))
1406 asf_tailq_init(&bf_q);
1408 status = ath_tgt_tx_form_aggr(sc, tid, &bf_q);
1410 if (asf_tailq_empty(&bf_q))
1413 bf = asf_tailq_first(&bf_q);
1414 bf_last = asf_tailq_last(&bf_q, ath_bufhead_s);
1416 if (bf->bf_nframes == 1) {
1418 if(bf->bf_retries == 0)
1419 __stats(sc, txaggr_single);
1421 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs -1]);
1422 bf->bf_lastds->ds_link = 0;
1425 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1426 ath_hal_clr11n_aggr(sc->sc_ah, ds);
1428 ath_buf_set_rate(sc, bf);
1429 bf->bf_txq_add(sc, bf);
1434 bf_last->bf_next = NULL;
1435 bf_last->bf_lastds->ds_link = 0;
1436 bf_last->bf_ndelim = 0;
1439 ath_buf_set_rate(sc, bf);
1440 ath_hal_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al,
1442 bf->bf_lastds = bf_last->bf_lastds;
1444 for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
1445 ath_hal_set11n_aggr_last(sc->sc_ah, &bf_last->bf_descarr[i]);
1447 if (status == ATH_AGGR_8K_LIMITED) {
1452 bf->bf_txq_add(sc, bf);
1453 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1454 status != ATH_TGT_AGGR_BAW_CLOSED);
1457 static u_int32_t ath_lookup_rate(struct ath_softc_tgt *sc,
1458 struct ath_node_target *an,
1459 struct ath_tx_buf *bf)
1462 u_int32_t max4msframelen, frame_length;
1463 u_int16_t aggr_limit, legacy=0;
1464 const HAL_RATE_TABLE *rt = sc->sc_currates;
1465 struct ieee80211_node_target *ieee_node = (struct ieee80211_node_target *)an;
1467 if (bf->bf_ismcast) {
1468 bf->bf_rcs[1].tries = bf->bf_rcs[2].tries = bf->bf_rcs[3].tries = 0;
1469 bf->bf_rcs[0].rix = 0xb;
1470 bf->bf_rcs[0].tries = ATH_TXMAXTRY - 1;
1471 bf->bf_rcs[0].flags = 0;
1473 ath_tgt_rate_findrate(sc, an, AH_TRUE, 0, ATH_TXMAXTRY-1, 4, 1,
1474 ATH_RC_PROBE_ALLOWED, bf->bf_rcs, &prate);
1477 max4msframelen = IEEE80211_AMPDU_LIMIT_MAX;
1479 for (i = 0; i < 4; i++) {
1480 if (bf->bf_rcs[i].tries) {
1481 frame_length = bf->bf_rcs[i].max4msframelen;
1483 if (rt->info[bf->bf_rcs[i].rix].phy != IEEE80211_T_HT) {
1488 max4msframelen = ATH_MIN(max4msframelen, frame_length);
1492 if (prate || legacy)
1495 if (sc->sc_ic.ic_enable_coex)
1496 aggr_limit = ATH_MIN((max4msframelen*3)/8, sc->sc_ic.ic_ampdu_limit);
1498 aggr_limit = ATH_MIN(max4msframelen, sc->sc_ic.ic_ampdu_limit);
1500 if (ieee_node->ni_maxampdu)
1501 aggr_limit = ATH_MIN(aggr_limit, ieee_node->ni_maxampdu);
1506 int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
1509 struct ath_tx_buf *bf_first ,*bf_prev = NULL;
1510 int nframes = 0, rl = 0;;
1511 struct ath_desc *ds = NULL;
1512 struct ath_tx_buf *bf;
1513 u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta;
1514 u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
1516 bf_first = asf_tailq_first(&tid->buf_q);
1519 bf = asf_tailq_first(&tid->buf_q);
1522 if (!BAW_WITHIN(tid->seq_start, tid->baw_size,
1523 SEQNO_FROM_BF_SEQNO(bf->bf_seqno))) {
1525 bf_first->bf_al= al;
1526 bf_first->bf_nframes = nframes;
1527 return ATH_TGT_AGGR_BAW_CLOSED;
1531 aggr_limit = ath_lookup_rate(sc, tid->an, bf);
1535 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_pktlen;
1537 if (nframes && (aggr_limit < (al + bpad + al_delta + prev_al))) {
1538 bf_first->bf_al= al;
1539 bf_first->bf_nframes = nframes;
1540 return ATH_TGT_AGGR_LIMITED;
1544 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 17)) {
1546 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 22)) {
1548 bf_first->bf_al= al;
1549 bf_first->bf_nframes = nframes;
1550 return ATH_TGT_AGGR_LIMITED;
1553 ath_tx_addto_baw(tid, bf);
1554 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1555 asf_tailq_insert_tail(bf_q, bf, bf_list);
1560 adf_os_assert(bf->bf_comp == ath_tgt_tx_comp_aggr);
1562 al += bpad + al_delta;
1563 bf->bf_ndelim = ATH_AGGR_GET_NDELIM(bf->bf_pktlen);
1565 switch (bf->bf_keytype) {
1566 case HAL_KEY_TYPE_AES:
1567 bf->bf_ndelim += ATH_AGGR_ENCRYPTDELIM;
1569 case HAL_KEY_TYPE_WEP:
1570 case HAL_KEY_TYPE_TKIP:
1571 bf->bf_ndelim += 64;
1573 case HAL_KEY_TYPE_WAPI:
1574 bf->bf_ndelim += 12;
1580 bpad = PADBYTES(al_delta) + (bf->bf_ndelim << 2);
1583 bf_prev->bf_next = bf;
1584 bf_prev->bf_lastds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1588 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1589 ath_hal_set11n_aggr_middle(sc->sc_ah, ds, bf->bf_ndelim);
1591 } while (!asf_tailq_empty(&tid->buf_q));
1593 bf_first->bf_al= al;
1594 bf_first->bf_nframes = nframes;
1596 return ATH_TGT_AGGR_DONE;
1599 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf)
1603 if (bf->bf_isretried) {
1607 index = ATH_BA_INDEX(tid->seq_start, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1608 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1610 TX_BUF_BITMAP_SET(tid->tx_buf_bitmap, cindex);
1612 if (index >= ((tid->baw_tail - tid->baw_head) & (ATH_TID_MAX_BUFS - 1))) {
1613 tid->baw_tail = cindex;
1614 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1618 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1620 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1621 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1622 struct ath_tx_desc lastds;
1623 struct ath_tx_desc *ds = &lastds;
1624 struct ath_rc_series rcs[4];
1629 int nframes = bf->bf_nframes;
1630 struct ath_buf *bf_next;
1633 struct ath_buf *bar = NULL;
1634 struct ath_txq *txq;
1638 if (tid->flag & TID_CLEANUP_INPROGRES) {
1639 ath_tx_comp_cleanup(sc, bf);
1643 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1644 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1646 if (ds->ds_txstat.ts_flags == HAL_TX_SW_FILTERED) {
1651 if (!bf->bf_isaggr) {
1652 ath_tx_comp_unaggr(sc, bf);
1656 __stats(sc, tx_compaggr);
1658 asf_tailq_init(&bf_q);
1660 seq_st = ATH_DS_BA_SEQ(ds);
1661 ba = ATH_DS_BA_BITMAP(ds);
1662 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1664 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1665 ath_tx_comp_aggr_error(sc, bf, tid);
1669 if (tx_ok && !ATH_DS_TX_BA(ds)) {
1670 __stats(sc, txaggr_babug);
1671 adf_os_print("BA Bug?\n");
1672 ath_tx_comp_aggr_error(sc, bf, tid);
1677 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1678 bf_next = bf->bf_next;
1680 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
1681 __stats(sc, txaggr_compgood);
1682 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1683 ath_tx_status_update_aggr(sc, bf, ds, rcs, 1);
1684 ath_tx_freebuf(sc, bf);
1686 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1692 ath_update_aggr_stats(sc, ds, nframes, nbad);
1693 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1696 ath_bar_tx(sc, tid, bar);
1699 if (!asf_tailq_empty(&bf_q)) {
1700 __stats(sc, txaggr_prepends);
1701 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1702 ath_tgt_tx_enqueue(txq, tid);
1707 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1712 struct ath_tx_desc lastds;
1713 struct ath_desc *ds = &lastds;
1714 struct ath_rc_series rcs[4];
1715 struct ath_buf *bar = NULL;
1716 struct ath_buf *bf_next;
1717 int nframes = bf->bf_nframes;
1719 struct ath_txq *txq;
1721 asf_tailq_init(&bf_q);
1724 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1725 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1728 bf_next = bf->bf_next;
1729 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1733 ath_update_aggr_stats(sc, ds, nframes, nframes);
1734 ath_rate_tx_complete(sc, tid->an, ds, rcs, nframes, nframes);
1737 ath_bar_tx(sc, tid, bar);
1740 if (!asf_tailq_empty(&bf_q)) {
1741 __stats(sc, txaggr_prepends);
1742 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1743 ath_tgt_tx_enqueue(txq, tid);
1748 ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1751 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1752 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1753 struct ath_tx_desc lastds;
1754 struct ath_tx_desc *ds = &lastds;
1755 struct ath_rc_series rcs[4];
1760 int nframes = bf->bf_nframes;
1761 struct ath_buf *bf_next;
1764 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1765 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1767 seq_st = ATH_DS_BA_SEQ(ds);
1768 ba = ATH_DS_BA_BITMAP(ds);
1769 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1771 if (!bf->bf_isaggr) {
1772 ath_update_stats(sc, bf);
1774 __stats(sc, tx_compunaggr);
1776 ath_tx_status_update(sc, bf);
1778 ath_tx_freebuf(sc, bf);
1780 if (tid->flag & TID_CLEANUP_INPROGRES) {
1781 owl_tgt_tid_cleanup(sc, tid);
1789 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1790 bf_next = bf->bf_next;
1792 ath_tx_status_update_aggr(sc, bf, ds, rcs, 0);
1794 ath_tx_freebuf(sc, bf);
1798 tid->flag &= ~TID_CLEANUP_INPROGRES;
1799 ath_aggr_resume_tid(sc, tid);
1806 ath_update_aggr_stats(sc, ds, nframes, nbad);
1807 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1811 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1812 ath_bufhead *bf_q, struct ath_tx_buf **bar)
1815 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1816 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1817 struct ath_desc *ds = NULL;
1820 __stats(sc, txaggr_compretries);
1822 for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
1823 ath_hal_clr11n_aggr(sc->sc_ah, ds);
1824 ath_hal_set11n_burstduration(sc->sc_ah, ds, 0);
1825 ath_hal_set11n_virtualmorefrag(sc->sc_ah, ds, 0);
1828 if (bf->bf_retries >= OWLMAX_RETRIES) {
1829 __stats(sc, txaggr_xretries);
1830 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1831 ath_tx_status_update_aggr(sc, bf, bf->bf_lastds, NULL, 0);
1836 ath_tx_freebuf(sc, bf);
1841 __stats(sc, txaggr_errlast);
1842 bf = ath_buf_toggle(sc, bf, 1);
1844 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs - 1]);
1846 ath_tx_set_retry(sc, bf);
1847 asf_tailq_insert_tail(bf_q, bf, bf_list);
1851 ath_update_aggr_stats(struct ath_softc_tgt *sc,
1852 struct ath_tx_desc *ds, int nframes,
1856 u_int8_t status = ATH_DS_TX_STATUS(ds);
1857 u_int8_t txflags = ATH_DS_TX_FLAGS(ds);
1859 __statsn(sc, txaggr_longretries, ds->ds_txstat.ts_longretry);
1860 __statsn(sc, txaggr_shortretries, ds->ds_txstat.ts_shortretry);
1862 if (txflags & HAL_TX_DESC_CFG_ERR)
1863 __stats(sc, txaggr_desc_cfgerr);
1865 if (txflags & HAL_TX_DATA_UNDERRUN)
1866 __stats(sc, txaggr_data_urun);
1868 if (txflags & HAL_TX_DELIM_UNDERRUN)
1869 __stats(sc, txaggr_delim_urun);
1875 if (status & HAL_TXERR_XRETRY)
1876 __stats(sc, txaggr_compxretry);
1878 if (status & HAL_TXERR_FILT)
1879 __stats(sc, txaggr_filtered);
1881 if (status & HAL_TXERR_FIFO)
1882 __stats(sc, txaggr_fifo);
1884 if (status & HAL_TXERR_XTXOP)
1885 __stats(sc, txaggr_xtxop);
1887 if (status & HAL_TXERR_TIMER_EXPIRED)
1888 __stats(sc, txaggr_timer_exp);
1892 ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1894 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1895 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1896 struct ath_desc *ds = bf->bf_lastds;
1898 ath_update_stats(sc, bf);
1899 ath_rate_tx_complete(sc, an, ds, bf->bf_rcs, 1, 0);
1901 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1902 ath_tx_retry_unaggr(sc, bf);
1905 __stats(sc, tx_compunaggr);
1907 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1908 ath_tx_status_update(sc, bf);
1909 ath_tx_freebuf(sc, bf);
1913 ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1915 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1916 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1917 struct ath_txq *txq;
1921 if (bf->bf_retries >= OWLMAX_RETRIES) {
1922 __stats(sc, txunaggr_xretry);
1923 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1924 ath_tx_status_update(sc, bf);
1925 ath_bar_tx(sc, tid, bf);
1929 __stats(sc, txunaggr_compretries);
1930 if (!bf->bf_lastds->ds_link) {
1931 __stats(sc, txunaggr_errlast);
1932 bf = ath_buf_toggle(sc, bf, 1);
1935 ath_tx_set_retry(sc, bf);
1936 asf_tailq_insert_head(&tid->buf_q, bf, bf_list);
1937 ath_tgt_tx_enqueue(txq, tid);
1941 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno)
1946 index = ATH_BA_INDEX(tid->seq_start, seqno);
1947 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1949 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, cindex);
1951 while (tid->baw_head != tid->baw_tail &&
1952 (!TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head))) {
1953 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1954 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1958 static void ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1960 struct ieee80211_frame *wh;
1962 __stats(sc, txaggr_retries);
1964 bf->bf_isretried = 1;
1966 wh = ATH_SKB_2_WH(bf->bf_skb);
1967 wh->i_fc[1] |= IEEE80211_FC1_RETRY;
1970 void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an,
1971 ath_atx_tid_t *tid, a_uint8_t discard_all)
1973 struct ath_tx_buf *bf;
1974 struct ath_tx_buf *bf_next;
1975 struct ath_txq *txq;
1977 txq = TID_TO_ACTXQ(tid->tidno);
1979 bf = asf_tailq_first(&tid->buf_q);
1982 if (discard_all || bf->bf_isretried) {
1983 bf_next = asf_tailq_next(bf, bf_list);
1984 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
1985 if (bf->bf_isretried)
1986 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1987 ath_tx_freebuf(sc, bf);
1991 bf->bf_comp = ath_tgt_tx_comp_normal;
1992 bf = asf_tailq_next(bf, bf_list);
1995 ath_aggr_pause_tid(sc, tid);
1997 while (tid->baw_head != tid->baw_tail) {
1998 if (TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head)) {
2000 tid->flag |= TID_CLEANUP_INPROGRES;
2001 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, tid->baw_head);
2003 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
2004 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
2007 if (!(tid->flag & TID_CLEANUP_INPROGRES)) {
2008 ath_aggr_resume_tid(sc, tid);
2012 /******************/
2013 /* BAR Management */
2014 /******************/
2016 static void ath_tgt_delba_send(struct ath_softc_tgt *sc,
2017 struct ieee80211_node_target *ni,
2018 a_uint8_t tidno, a_uint8_t initiator,
2019 a_uint16_t reasoncode)
2021 struct ath_node_target *an = ATH_NODE_TARGET(ni);
2022 ath_atx_tid_t *tid = ATH_AN_2_TID(an, tidno);
2023 struct wmi_data_delba wmi_delba;
2025 tid->flag &= ~TID_AGGR_ENABLED;
2027 ath_tgt_tx_cleanup(sc, an, tid, 1);
2029 wmi_delba.ni_nodeindex = ni->ni_nodeindex;
2030 wmi_delba.tidno = tid->tidno;
2031 wmi_delba.initiator = 1;
2032 wmi_delba.reasoncode = IEEE80211_REASON_UNSPECIFIED;
2034 __stats(sc, txbar_xretry);
2035 wmi_event(sc->tgt_wmi_handle,
2041 static void ath_bar_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2043 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
2044 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
2046 if (bf->bf_retries >= OWLMAX_BAR_RETRIES) {
2047 ath_tgt_delba_send(sc, bf->bf_node, tid->tidno, 1,
2048 IEEE80211_REASON_UNSPECIFIED);
2049 ath_tgt_tid_drain(sc, tid);
2052 ath_buf_comp(sc, bf);
2056 __stats(sc, txbar_compretries);
2058 if (!bf->bf_lastds->ds_link) {
2059 __stats(sc, txbar_errlast);
2060 bf = ath_buf_toggle(sc, bf, 1);
2063 bf->bf_lastds->ds_link = 0;
2065 ath_tx_set_retry(sc, bf);
2066 ath_tgt_txq_add_ucast(sc, bf);
2069 static void ath_bar_tx_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2071 struct ath_desc *ds = bf->bf_lastds;
2072 struct ath_node_target *an;
2074 struct ath_txq *txq;
2076 an = (struct ath_node_target *)bf->bf_node;
2077 tid = &an->tid[bf->bf_tidno];
2078 txq = TID_TO_ACTXQ(tid->tidno);
2080 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
2081 ath_bar_retry(sc, bf);
2085 ath_aggr_resume_tid(sc, tid);
2088 ath_buf_comp(sc, bf);
2091 static void ath_bar_tx(struct ath_softc_tgt *sc,
2092 ath_atx_tid_t *tid, struct ath_tx_buf *bf)
2095 struct ieee80211_frame_bar *bar;
2097 struct ath_desc *ds, *ds0;
2098 HAL_11N_RATE_SERIES series[4];
2100 adf_nbuf_queue_t skbhead;
2104 __stats(sc, tx_bars);
2106 memset(&series, 0, sizeof(series));
2108 ath_aggr_pause_tid(sc, tid);
2110 skb = adf_nbuf_queue_remove(&bf->bf_skbhead);
2111 adf_nbuf_peek_header(skb, &anbdata, &anblen);
2112 adf_nbuf_trim_tail(skb, anblen);
2113 bar = (struct ieee80211_frame_bar *) anbdata;
2117 ath_dma_unmap(sc, bf);
2118 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
2120 bar->i_fc[1] = IEEE80211_FC1_DIR_NODS;
2121 bar->i_fc[0] = IEEE80211_FC0_VERSION_0 |
2122 IEEE80211_FC0_TYPE_CTL |
2123 IEEE80211_FC0_SUBTYPE_BAR;
2124 bar->i_ctl = tid->tidno << IEEE80211_BAR_CTL_TID_S |
2125 IEEE80211_BAR_CTL_COMBA;
2126 bar->i_seq = adf_os_cpu_to_le16(tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT);
2128 bf->bf_seqno = tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT;
2130 adf_nbuf_put_tail(skb, sizeof(struct ieee80211_frame_bar));
2132 bf->bf_comp = ath_bar_tx_comp;
2133 bf->bf_tidno = tid->tidno;
2134 bf->bf_node = &tid->an->ni;
2135 ath_dma_map(sc, bf);
2136 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
2139 ath_hal_setuptxdesc(sc->sc_ah, ds
2140 , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
2142 , HAL_PKT_TYPE_NORMAL
2149 | HAL_TXDESC_CLRDMASK
2151 , ATH_COMP_PROC_NO_COMP_NO_CCS);
2153 skbhead = bf->bf_skbhead;
2157 for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
2158 ath_hal_clr11n_aggr(sc->sc_ah, ds0);
2161 ath_filltxdesc(sc, bf);
2163 for (i = 0 ; i < 4; i++) {
2164 series[i].Tries = ATH_TXMAXTRY;
2165 series[i].Rate = min_rate;
2166 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
2169 ath_hal_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 0, 0, 0, series, 4, 4);
2170 ath_tgt_txq_add_ucast(sc, bf);