target_firmware/wlan/if_ath.c

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <adf_os_types.h>
  37 #include <adf_os_pci.h>
  38 #include <adf_os_dma.h>
  39 #include <adf_os_timer.h>
  40 #include <adf_os_lock.h>
  41 #include <adf_os_io.h>
  42 #include <adf_os_mem.h>
  43 #include <adf_os_util.h>
  44 #include <adf_os_stdtypes.h>
  45 #include <adf_os_defer.h>
  46 #include <adf_os_atomic.h>
  47 #include <adf_nbuf.h>
  48 #include <adf_net.h>
  49 #include <adf_net_wcmd.h>
  50 #include <adf_os_irq.h>
  51
  52 #include <if_ath_pci.h>
  53 #include "if_llc.h"
  54 #include "ieee80211_var.h"
  55 #include "if_athrate.h"
  56 #include "if_athvar.h"
  57 #include "ah_desc.h"
  58 #include "ah.h"
  59
  60 static a_int32_t ath_numrxbufs = -1;
  61 static a_int32_t ath_numrxdescs = -1;
  62
  63 #if defined(PROJECT_MAGPIE)
  64 uint32_t *init_htc_handle = 0;
  65 #endif
  66
  67 #define RX_ENDPOINT_ID 3
  68 #define ATH_CABQ_HANDLING_THRESHOLD 9000
  69 #define UAPSDQ_NUM   9
  70 #define CABQ_NUM     8
  71
  72 void owl_tgt_tx_tasklet(TQUEUE_ARG data);
  73 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
  74 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
  75 extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
  76 extern void  ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
  77 extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
  78 extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,  owl_txq_state_t txqstate);
  79 void owl_tgt_node_init(struct ath_node_target * an);
  80 void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
  81 void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
  82
  83 /*
  84  * Extend a 32 bit TSF to 64 bit, taking wrapping into account.
  85  */
  86 static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
  87 {
  88         struct ath_hal *ah = sc->sc_ah;
  89         u_int64_t tsf;
  90         u_int32_t tsf_low;
  91         u_int64_t tsf64;
  92
  93         tsf = ah->ah_getTsf64(ah);
  94         tsf_low = tsf & 0xffffffff;
  95         tsf64 = (tsf & ~0xffffffffULL) | rstamp;
  96
  97         if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000))
  98                 tsf64 -= 0x100000000ULL;
  99
 100         if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000))
 101                 tsf64 += 0x100000000ULL;
 102
 103         return tsf64;
 104 }
 105
 106 static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode)
 107 {
 108         struct ath_hal *ah = sc->sc_ah;
 109         const HAL_RATE_TABLE *rt;
 110
 111         switch (mode) {
 112         case IEEE80211_MODE_11NA:
 113                 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NA);
 114                 break;
 115         case IEEE80211_MODE_11NG:
 116                 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NG);
 117                 break;
 118         default:
 119                 return 0;
 120         }
 121         rt = sc->sc_rates[mode];
 122         if (rt == NULL)
 123                 return 0;
 124
 125         return 1;
 126 }
 127
 128 static void ath_setcurmode(struct ath_softc_tgt *sc,
 129                            enum ieee80211_phymode mode)
 130 {
 131         const HAL_RATE_TABLE *rt;
 132         a_int32_t i;
 133
 134         adf_os_mem_set(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
 135
 136         rt = sc->sc_rates[mode];
 137         adf_os_assert(rt != NULL);
 138
 139         for (i = 0; i < rt->rateCount; i++) {
 140                 sc->sc_rixmap[rt->info[i].rateCode] = i;
 141         }
 142
 143         sc->sc_currates = rt;
 144         sc->sc_curmode = mode;
 145         sc->sc_protrix = ((mode == IEEE80211_MODE_11NG) ? 3 : 0);
 146
 147 }
 148
 149 void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
 150                void *buffer, a_int32_t Length)
 151 {
 152         adf_nbuf_t netbuf = ADF_NBUF_NULL;
 153         a_uint8_t *pData;
 154
 155         netbuf = WMI_AllocEvent(handle, WMI_EVT_CLASS_CMD_EVENT,
 156                                 sizeof(WMI_CMD_HDR) + Length);
 157
 158         if (netbuf == ADF_NBUF_NULL) {
 159                 adf_os_print("Buf null\n");
 160                 return;
 161         }
 162
 163         if (buffer != NULL && Length != 0 && Length < WMI_SVC_MAX_BUFFERED_EVENT_SIZE) {
 164                 pData = adf_nbuf_put_tail(netbuf, Length);
 165                 adf_os_mem_copy(pData, buffer, Length);
 166         }
 167
 168         WMI_SendEvent(handle, netbuf, evt_id, 0, Length);
 169 }
 170
 171 void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo,
 172                  void *buffer, a_int32_t Length)
 173 {
 174         adf_nbuf_t netbuf = ADF_NBUF_NULL;
 175         A_UINT8 *pData;
 176
 177         netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY,
 178                                 sizeof(WMI_CMD_HDR) + Length);
 179
 180         if (netbuf == ADF_NBUF_NULL) {
 181                 adf_os_assert(0);
 182                 return;
 183         }
 184
 185         if (Length != 0 && buffer != NULL) {
 186                 pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length);
 187                 adf_os_mem_copy(pData, buffer, Length);
 188         }
 189
 190         WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length);
 191 }
 192
 193 static void ath_node_vdelete_tgt(struct ath_softc_tgt *sc, a_uint8_t vap_index)
 194 {
 195         a_int32_t i;
 196
 197         for (i = 0; i < TARGET_NODE_MAX; i++) {
 198                 if(sc->sc_sta[i].ni.ni_vapindex == vap_index)
 199                         sc->sc_sta[i].an_valid = 0;
 200         }
 201 }
 202
 203 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp)
 204 {
 205         if (sc->sc_curmode == IEEE80211_MODE_11NG)
 206                 return avp->av_minrateidx[0];
 207         else if (sc->sc_curmode == IEEE80211_MODE_11NA)
 208                 return avp->av_minrateidx[1];
 209
 210         return 0;
 211 }
 212
 213 /******/
 214 /* RX */
 215 /******/
 216
 217 static adf_nbuf_t ath_alloc_skb_align(struct ath_softc_tgt *sc,
 218                                       a_uint32_t size, a_uint32_t align)
 219 {
 220         adf_nbuf_t skb;
 221
 222         skb = BUF_Pool_alloc_buf_align(sc->pool_handle, POOL_ID_WLAN_RX_BUF,
 223                                        RX_HEADER_SPACE, align);
 224         return skb;
 225 }
 226
 227 static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *ds)
 228 {
 229         struct ath_hal *ah = sc->sc_ah;
 230         struct ath_rx_desc *ds_held;
 231         a_uint8_t *anbdata;
 232         a_uint32_t anblen;
 233
 234         if (!sc->sc_rxdesc_held) {
 235                 sc->sc_rxdesc_held = ds;
 236                 return 0;
 237         }
 238
 239         ds_held = sc->sc_rxdesc_held;
 240         sc->sc_rxdesc_held = ds;
 241         ds = ds_held;
 242
 243         if (ds->ds_nbuf == ADF_NBUF_NULL) {
 244                 ds->ds_nbuf = ath_alloc_skb_align(sc, sc->sc_rxbufsize, sc->sc_cachelsz);
 245                 if (ds->ds_nbuf == ADF_NBUF_NULL) {
 246                         sc->sc_rxdesc_held = ds;
 247                         sc->sc_rx_stats.ast_rx_nobuf++;
 248                         return ENOMEM;
 249                 }
 250                 adf_nbuf_map(sc->sc_dev, ds->ds_dmap, ds->ds_nbuf, ADF_OS_DMA_FROM_DEVICE);
 251                 adf_nbuf_dmamap_info(ds->ds_dmap, &ds->ds_dmap_info);
 252                 ds->ds_data = ds->ds_dmap_info.dma_segs[0].paddr;
 253         }
 254
 255         ds->ds_link = 0;
 256         adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
 257
 258         ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0);
 259
 260         if (sc->sc_rxlink == NULL) {
 261                 ah->ah_setRxDP(ah, ds->ds_daddr);
 262         }
 263         else {
 264                 *sc->sc_rxlink = ds->ds_daddr;
 265         }
 266         sc->sc_rxlink = &ds->ds_link;
 267         ah->ah_enableReceive(ah);
 268
 269         return 0;
 270 }
 271
 272 static void ath_rx_complete(struct ath_softc_tgt *sc, adf_nbuf_t buf)
 273 {
 274         struct ath_rx_desc *ds;
 275         adf_nbuf_t buf_tmp;
 276         adf_nbuf_queue_t nbuf_head;
 277
 278         adf_nbuf_split_to_frag(buf, &nbuf_head);
 279         ds = asf_tailq_first(&sc->sc_rxdesc_idle);
 280
 281         while (ds) {
 282                 struct ath_rx_desc *ds_tmp;
 283                 buf_tmp = adf_nbuf_queue_remove(&nbuf_head);
 284
 285                 if (buf_tmp == NULL) {
 286                         break;
 287                 }
 288
 289                 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, buf_tmp);
 290
 291                 ds_tmp = ds;
 292                 ds = asf_tailq_next(ds, ds_list);
 293
 294                 ath_rxdesc_init(sc, ds_tmp);
 295
 296                 asf_tailq_remove(&sc->sc_rxdesc_idle, ds_tmp, ds_list);
 297                 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_tmp, ds_list);
 298         }
 299 }
 300
 301 static void tgt_HTCSendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t buf, void *ServiceCtx)
 302 {
 303         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 304
 305         if (Endpt == RX_ENDPOINT_ID) {
 306                 sc->sc_rx_stats.ast_rx_done++;
 307                 ath_rx_complete(sc, buf);
 308         }
 309 }
 310
 311 static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc)
 312 {
 313         struct ath_hal *ah = sc->sc_ah;
 314         struct ath_rx_buf *bf = NULL;
 315         struct ath_rx_desc *ds, *ds_head, *ds_tail, *ds_tmp;
 316         a_int32_t retval;
 317         a_uint32_t cnt = 0;
 318         a_uint16_t frame_len = 0;
 319         a_uint64_t tsf;
 320
 321 #define PA2DESC(_sc, _pa)                                               \
 322         ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc +         \
 323                              ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
 324
 325         tsf = ah->ah_getTsf64(ah);
 326         bf = asf_tailq_first(&sc->sc_rxbuf);
 327
 328         ds = asf_tailq_first(&sc->sc_rxdesc);
 329         ds_head = ds;
 330
 331         while(ds) {
 332                 ++cnt;
 333
 334                 if (cnt == ath_numrxbufs - 1) {
 335                         adf_os_print("VERY LONG PACKET!!!!!\n");
 336                         ds_tail = ds;
 337                         ds_tmp = ds_head;
 338                         while (ds_tmp) {
 339                                 struct ath_rx_desc *ds_rmv;
 340                                 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
 341                                 ds_rmv = ds_tmp;
 342                                 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
 343
 344                                 if (ds_tmp == NULL) {
 345                                         adf_os_print("ds_tmp is NULL\n");
 346                                         adf_os_assert(0);
 347                                 }
 348
 349                                 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ds_rmv->ds_nbuf);
 350                                 ds_rmv->ds_nbuf = ADF_NBUF_NULL;
 351
 352                                 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
 353                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 354                                         asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
 355                                 }
 356                                 else {
 357                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 358                                         asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
 359                                 }
 360
 361                                 if (ds_rmv == ds_tail) {
 362                                         break;
 363                                 }
 364                         }
 365                         break;
 366                 }
 367
 368                 if (ds->ds_link == 0) {
 369                         break;
 370                 }
 371
 372                 if (bf->bf_status & ATH_BUFSTATUS_DONE) {
 373                         continue;
 374                 }
 375
 376                 retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr,
 377                                                 PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
 378                 if (HAL_EINPROGRESS == retval) {
 379                         break;
 380                 }
 381
 382                 if (adf_nbuf_len(ds->ds_nbuf) == 0) {
 383                         adf_nbuf_put_tail(ds->ds_nbuf, bf->bf_rx_status.rs_datalen);
 384                 }
 385
 386                 frame_len += bf->bf_rx_status.rs_datalen;
 387
 388                 if (bf->bf_rx_status.rs_more == 0) {
 389                         adf_nbuf_queue_t nbuf_head;
 390                         adf_nbuf_queue_init(&nbuf_head);
 391
 392                         cnt = 0;
 393
 394                         ds_tail = ds;
 395                         ds = asf_tailq_next(ds, ds_list);
 396
 397                         ds_tmp = ds_head;
 398                         ds_head = asf_tailq_next(ds_tail, ds_list);
 399
 400                         while (ds_tmp) {
 401                                 struct ath_rx_desc *ds_rmv;
 402
 403                                 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
 404                                 adf_nbuf_queue_add(&nbuf_head, ds_tmp->ds_nbuf);
 405                                 ds_tmp->ds_nbuf = ADF_NBUF_NULL;
 406
 407                                 ds_rmv = ds_tmp;
 408                                 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
 409                                 if (ds_tmp == NULL) {
 410                                         adf_os_assert(0);
 411                                 }
 412
 413                                 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
 414                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 415                                         asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
 416                                 }  else {
 417                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 418                                         asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
 419                                 }
 420
 421                                 if (ds_rmv == ds_tail) {
 422                                         break;
 423                                 }
 424                         }
 425
 426
 427                         bf->bf_rx_status.rs_datalen = frame_len;
 428                         frame_len = 0;
 429
 430                         bf->bf_skb = adf_nbuf_create_frm_frag(&nbuf_head);
 431
 432                         bf->bf_status |= ATH_BUFSTATUS_DONE;
 433
 434                         bf = (struct ath_rx_buf *)asf_tailq_next(bf, bf_list);
 435                 }
 436                 else {
 437                         ds = asf_tailq_next(ds, ds_list);
 438                 }
 439         }
 440
 441 #undef PA2DESC
 442 }
 443
 444 static a_int32_t ath_startrecv(struct ath_softc_tgt *sc)
 445 {
 446         struct ath_hal *ah = sc->sc_ah;
 447         struct ath_rx_desc *ds;
 448
 449         sc->sc_rxbufsize = 1024+512+128;
 450         sc->sc_rxlink = NULL;
 451
 452         sc->sc_rxdesc_held = NULL;
 453
 454         asf_tailq_foreach(ds, &sc->sc_rxdesc, ds_list) {
 455                 a_int32_t error = ath_rxdesc_init(sc, ds);
 456                 if (error != 0) {
 457                         return error;
 458                 }
 459         }
 460
 461         ds = asf_tailq_first(&sc->sc_rxdesc);
 462         ah->ah_setRxDP(ah, ds->ds_daddr);
 463
 464         return 0;
 465 }
 466
 467 static void ath_tgt_rx_tasklet(TQUEUE_ARG data)
 468 {
 469         struct ath_softc_tgt *sc  = (struct ath_softc_tgt *)data;
 470         struct ath_rx_buf *bf = NULL;
 471         struct ath_hal *ah = sc->sc_ah;
 472         struct rx_frame_header *rxhdr;
 473         struct ath_rx_status *rxstats;
 474         adf_nbuf_t skb = ADF_NBUF_NULL;
 475
 476         do {
 477                 bf = asf_tailq_first(&sc->sc_rxbuf);
 478                 if (bf == NULL) {
 479                         break;
 480                 }
 481
 482                 if (!(bf->bf_status & ATH_BUFSTATUS_DONE)) {
 483                         break;
 484                 }
 485
 486                 skb = bf->bf_skb;
 487                 if (skb == NULL) {
 488                         continue;
 489                 }
 490
 491                 asf_tailq_remove(&sc->sc_rxbuf, bf, bf_list);
 492
 493                 bf->bf_skb = NULL;
 494
 495                 rxhdr = (struct rx_frame_header *)adf_nbuf_push_head(skb,
 496                                                      sizeof(struct rx_frame_header));
 497                 rxstats = (struct ath_rx_status *)(&rxhdr->rx_stats[0]);
 498                 adf_os_mem_copy(rxstats, &(bf->bf_rx_status),
 499                                 sizeof(struct ath_rx_status));
 500
 501                 rxstats->rs_tstamp = ath_extend_tsf(sc, (u_int32_t)rxstats->rs_tstamp);
 502
 503                 HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb);
 504                 sc->sc_rx_stats.ast_rx_send++;
 505
 506                 bf->bf_status &= ~ATH_BUFSTATUS_DONE;
 507                 asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list);
 508
 509         } while(1);
 510
 511         sc->sc_imask |= HAL_INT_RX;
 512         ah->ah_setInterrupts(ah, sc->sc_imask);
 513 }
 514
 515 /*******************/
 516 /* Beacon Handling */
 517 /*******************/
 518
 519 /*
 520  * Setup the beacon frame for transmit.
 521  * FIXME: Short Preamble.
 522  */
 523 static void ath_beacon_setup(struct ath_softc_tgt *sc,
 524                              struct ath_tx_buf *bf,
 525                              struct ath_vap_target *avp)
 526 {
 527         adf_nbuf_t skb = bf->bf_skb;
 528         struct ath_hal *ah = sc->sc_ah;
 529         struct ath_tx_desc *ds;
 530         a_int32_t flags;
 531         const HAL_RATE_TABLE *rt;
 532         a_uint8_t rix, rate;
 533         HAL_11N_RATE_SERIES series[4] = {{ 0 }};
 534
 535         flags = HAL_TXDESC_NOACK;
 536
 537         ds = bf->bf_desc;
 538         ds->ds_link = 0;
 539         ds->ds_data = bf->bf_dmamap_info.dma_segs[0].paddr;
 540
 541         rix = ath_get_minrateidx(sc, avp);
 542         rt  = sc->sc_currates;
 543         rate = rt->info[rix].rateCode;
 544
 545         ah->ah_setupTxDesc(ah, ds
 546                             , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
 547                             , sizeof(struct ieee80211_frame)
 548                             , HAL_PKT_TYPE_BEACON
 549                             , MAX_RATE_POWER
 550                             , rate, 1
 551                             , HAL_TXKEYIX_INVALID
 552                             , 0
 553                             , flags
 554                             , 0
 555                             , 0
 556                             , 0
 557                             , 0
 558                             , ATH_COMP_PROC_NO_COMP_NO_CCS);
 559
 560         ah->ah_fillTxDesc(ah, ds
 561                            , asf_roundup(adf_nbuf_len(skb), 4)
 562                            , AH_TRUE
 563                            , AH_TRUE
 564                            , ds);
 565
 566         series[0].Tries = 1;
 567         series[0].Rate = rate;
 568         series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
 569         series[0].RateFlags = 0;
 570         ah->ah_set11nRateScenario(ah, ds, 0, 0, 0, series, 4, 0);
 571 }
 572
 573 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
 574                                 adf_nbuf_t nbuf, HTC_ENDPOINT_ID EndPt)
 575 {
 576         struct ath_hal *ah = sc->sc_ah;
 577         struct ath_tx_buf *bf;
 578         a_uint8_t vap_index, *anbdata;
 579         ath_beacon_hdr_t *bhdr;
 580         struct ieee80211vap_target  *vap;
 581         a_uint32_t anblen;
 582         struct ieee80211_frame *wh;
 583
 584         if (!bc_hdr) {
 585                 adf_nbuf_peek_header(nbuf, &anbdata, &anblen);
 586                 bhdr = (ath_beacon_hdr_t *)anbdata;
 587         } else {
 588                 adf_os_print("found bc_hdr! 0x%x\n", bc_hdr);
 589         }
 590
 591         vap_index = bhdr->vap_index;
 592         adf_os_assert(vap_index < TARGET_VAP_MAX);
 593         vap = &sc->sc_vap[vap_index].av_vap;
 594
 595         wh = (struct ieee80211_frame *)adf_nbuf_pull_head(nbuf,
 596                                                   sizeof(ath_beacon_hdr_t));
 597
 598         bf = sc->sc_vap[vap_index].av_bcbuf;
 599         adf_os_assert(bf);
 600         bf->bf_endpt = EndPt;
 601
 602         if (bf->bf_skb) {
 603                 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
 604                 adf_nbuf_push_head(bf->bf_skb, sizeof(ath_beacon_hdr_t));
 605                 ath_free_tx_skb(sc->tgt_htc_handle, bf->bf_endpt, bf->bf_skb);
 606         }
 607
 608         bf->bf_skb = nbuf;
 609
 610         adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, nbuf, ADF_OS_DMA_TO_DEVICE);
 611         adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info);
 612
 613         ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]);
 614         ah->ah_stopTxDma(ah, sc->sc_bhalq);
 615         ah->ah_setTxDP(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
 616         ah->ah_startTxDma(ah, sc->sc_bhalq);
 617 }
 618
 619 /******/
 620 /* TX */
 621 /******/
 622
 623 static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq)
 624 {
 625         struct ath_hal *ah = sc->sc_ah;
 626
 627         ah->ah_stopTxDma(ah, txq->axq_qnum);
 628 }
 629
 630 static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq)
 631 {
 632         owltgt_tx_processq(sc, txq, OWL_TXQ_STOPPED);
 633 }
 634
 635 static void ath_tx_draintxq(struct ath_softc_tgt *sc, struct ath_txq *txq)
 636 {
 637         owltgt_txq_drain(sc, txq);
 638 }
 639
 640 static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq)
 641 {
 642         struct ath_hal *ah = sc->sc_ah;
 643         a_uint16_t i;
 644         struct ath_txq *txq = NULL;
 645         struct ath_atx_tid *tid = NULL;
 646
 647         ath_tx_status_clear(sc);
 648         sc->sc_tx_draining = 1;
 649
 650         ah->ah_stopTxDma(ah, sc->sc_bhalq);
 651
 652         for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
 653                 if (ATH_TXQ_SETUP(sc, i))
 654                         ath_tx_stopdma(sc, ATH_TXQ(sc, i));
 655
 656         for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
 657                 if (ATH_TXQ_SETUP(sc, i)) {
 658                         owltgt_tx_processq(sc, ATH_TXQ(sc,i), OWL_TXQ_STOPPED);
 659
 660                         txq = ATH_TXQ(sc,i);
 661                         while (!asf_tailq_empty(&txq->axq_tidq)){
 662                                 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
 663                                 if(tid == NULL)
 664                                         break;
 665                                 tid->sched = AH_FALSE;
 666                                 ath_tgt_tid_drain(sc,tid);
 667                         }
 668                 }
 669
 670         sc->sc_tx_draining = 0;
 671 }
 672
 673 static void ath_tgt_txq_setup(struct ath_softc_tgt *sc)
 674 {
 675         a_int32_t qnum;
 676         struct ath_txq *txq;
 677
 678         sc->sc_txqsetup=0;
 679
 680         for (qnum=0;qnum<HAL_NUM_TX_QUEUES;qnum++) {
 681                 txq= &sc->sc_txq[qnum];
 682                 txq->axq_qnum = qnum;
 683                 txq->axq_link = NULL;
 684                 asf_tailq_init(&txq->axq_q);
 685                 txq->axq_depth = 0;
 686                 txq->axq_linkbuf = NULL;
 687                 asf_tailq_init(&txq->axq_tidq);
 688                 sc->sc_txqsetup |= 1<<qnum;
 689         }
 690
 691         sc->sc_uapsdq  = &sc->sc_txq[UAPSDQ_NUM];
 692         sc->sc_cabq    = &sc->sc_txq[CABQ_NUM];
 693
 694         sc->sc_ac2q[WME_AC_BE]  = &sc->sc_txq[0];
 695         sc->sc_ac2q[WME_AC_BK]  = &sc->sc_txq[1];
 696         sc->sc_ac2q[WME_AC_VI]  = &sc->sc_txq[2];
 697         sc->sc_ac2q[WME_AC_VO]  = &sc->sc_txq[3];
 698
 699         return;
 700 #undef N
 701 }
 702
 703 static void tgt_HTCRecv_beaconhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 704                                       adf_nbuf_t buf, void *ServiceCtx)
 705 {
 706         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 707
 708         ath_tgt_send_beacon(sc, hdr_buf, buf, EndPt);
 709 }
 710
 711 static void tgt_HTCRecv_uapsdhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 712                                      adf_nbuf_t buf, void *ServiceCtx)
 713 {
 714 }
 715
 716 static void tgt_HTCRecv_mgmthandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 717                                     adf_nbuf_t buf, void *ServiceCtx)
 718 {
 719         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 720
 721         ath_tgt_send_mgt(sc,hdr_buf,buf,EndPt);
 722 }
 723
 724 static void tgt_HTCRecvMessageHandler(HTC_ENDPOINT_ID EndPt,
 725                                       adf_nbuf_t hdr_buf, adf_nbuf_t buf,
 726                                       void *ServiceCtx)
 727 {
 728         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 729         struct ath_tx_buf *bf;
 730         a_uint8_t *data;
 731         a_uint32_t len;
 732         ath_data_hdr_t *dh;
 733         struct ath_node_target *an;
 734         struct ath_atx_tid *tid;
 735
 736         if (!hdr_buf) {
 737                 adf_nbuf_peek_header(buf, &data, &len);
 738                 adf_nbuf_pull_head(buf, sizeof(ath_data_hdr_t));
 739         } else {
 740                 adf_nbuf_peek_header(hdr_buf, &data, &len);
 741         }
 742
 743         adf_os_assert(len >= sizeof(ath_data_hdr_t));
 744         dh = (ath_data_hdr_t *)data;
 745
 746         an = &sc->sc_sta[dh->ni_index];
 747         tid = ATH_AN_2_TID(an, dh->tidno);
 748
 749         sc->sc_tx_stats.tx_tgt++;
 750
 751         bf = ath_tgt_tx_prepare(sc, buf, dh);
 752         if (!bf) {
 753                 ath_free_tx_skb(sc->tgt_htc_handle,EndPt,buf);
 754                 return;
 755         }
 756
 757         bf->bf_endpt = EndPt;
 758         bf->bf_cookie = dh->cookie;
 759
 760         if (tid->flag & TID_AGGR_ENABLED)
 761                 ath_tgt_handle_aggr(sc, bf);
 762         else
 763                 ath_tgt_handle_normal(sc, bf);
 764 }
 765
 766 static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 767                                    adf_nbuf_t buf, void *ServiceCtx)
 768 {
 769         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 770         struct ath_hal *ah = sc->sc_ah;
 771         a_uint64_t tsf;
 772         a_uint32_t tmp;
 773
 774 #ifdef ATH_ENABLE_CABQ
 775         tsf = ah->ah_getTsf64(ah);
 776         tmp = tsf - sc->sc_swba_tsf;
 777
 778         if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
 779                 HTC_ReturnBuffers(sc->tgt_htc_handle, EndPt, buf);
 780                 return;
 781         }
 782
 783         tgt_HTCRecvMessageHandler(EndPt, hdr_buf, buf, ServiceCtx);
 784 #endif
 785 }
 786
 787 /***********************/
 788 /* Descriptor Handling */
 789 /***********************/
 790
 791 static a_int32_t ath_descdma_setup(struct ath_softc_tgt *sc,
 792                                    struct ath_descdma *dd, ath_bufhead *head,
 793                                    const char *name, a_int32_t nbuf, a_int32_t ndesc,
 794                                    a_uint32_t bfSize, a_uint32_t descSize)
 795 {
 796 #define DS2PHYS(_dd, _ds)                                               \
 797         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 798
 799         struct ath_desc *ds;
 800         struct ath_buf *bf;
 801         a_int32_t i, bsize, error;
 802         a_uint8_t *bf_addr;
 803         a_uint8_t *ds_addr;
 804
 805         dd->dd_name = name;
 806         dd->dd_desc_len = descSize * nbuf * ndesc;
 807
 808         dd->dd_desc = adf_os_dmamem_alloc(sc->sc_dev,
 809                                   dd->dd_desc_len, 1, &dd->dd_desc_dmamap);
 810         dd->dd_desc_paddr = adf_os_dmamem_map2addr(dd->dd_desc_dmamap);
 811         if (dd->dd_desc == NULL) {
 812                 error = -ENOMEM;
 813                 goto fail;
 814         }
 815         ds = dd->dd_desc;
 816
 817         bsize = bfSize * nbuf;
 818         bf = adf_os_mem_alloc(bsize);
 819         if (bf == NULL) {
 820                 error = -ENOMEM;
 821                 goto fail2;
 822         }
 823         adf_os_mem_set(bf, 0, bsize);
 824         dd->dd_bufptr = bf;
 825
 826         bf_addr = (a_uint8_t *)bf;
 827         ds_addr = (a_uint8_t *)ds;
 828
 829         asf_tailq_init(head);
 830
 831         for (i = 0; i < nbuf; i++) {
 832                 a_int32_t j;
 833
 834                 if (adf_nbuf_dmamap_create( sc->sc_dev, &bf->bf_dmamap) != A_STATUS_OK) {
 835                         goto fail2;
 836                 }
 837
 838                 bf->bf_desc = bf->bf_descarr = bf->bf_lastds = ds;
 839                 for (j = 0; j < ndesc; j++)
 840                         ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, j, (ds_addr + (j*descSize)));
 841
 842                 ATH_BUF_SET_DESC_PHY_ADDR(bf, ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, 0));
 843
 844                 adf_nbuf_queue_init(&bf->bf_skbhead);
 845                 asf_tailq_insert_tail(head, bf, bf_list);
 846
 847                 bf_addr += bfSize;
 848                 ds_addr += (ndesc * descSize);
 849                 bf = (struct ath_buf *)bf_addr;
 850                 ds = (struct ath_desc *)ds_addr;
 851         }
 852
 853         return 0;
 854 fail2:
 855         adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
 856                            1, dd->dd_desc, dd->dd_desc_dmamap);
 857 fail:
 858         adf_os_mem_set(dd, 0, sizeof(*dd));
 859         adf_os_assert(0);
 860         return error;
 861
 862 #undef DS2PHYS
 863 }
 864
 865 static void ath_descdma_cleanup(struct ath_softc_tgt *sc,
 866                                 struct ath_descdma *dd,
 867                                 ath_bufhead *head, a_int32_t dir)
 868 {
 869         struct ath_buf *bf;
 870         struct ieee80211_node_target *ni;
 871
 872         asf_tailq_foreach(bf, head, bf_list) {
 873                 if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
 874                         adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, dir);
 875                         while(adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
 876                                 ath_free_rx_skb(sc,
 877                                         adf_nbuf_queue_remove(&bf->bf_skbhead));
 878                         }
 879                         bf->bf_skb = NULL;
 880                 } else if (bf->bf_skb != NULL) {
 881                         adf_nbuf_unmap(sc->sc_dev,bf->bf_dmamap, dir);
 882                         ath_free_rx_skb(sc, bf->bf_skb);
 883                         bf->bf_skb = NULL;
 884                 }
 885
 886                 adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap);
 887
 888                 ni = bf->bf_node;
 889                 bf->bf_node = NULL;
 890         }
 891
 892         adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
 893                            1, dd->dd_desc, dd->dd_desc_dmamap);
 894
 895         asf_tailq_init(head);
 896         adf_os_mem_free(dd->dd_bufptr);
 897         adf_os_mem_set(dd, 0, sizeof(*dd));
 898 }
 899
 900 static a_int32_t ath_desc_alloc(struct ath_softc_tgt *sc)
 901 {
 902 #define DS2PHYS(_dd, _ds)                                               \
 903         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 904
 905         a_int32_t error;
 906         struct ath_tx_buf *bf;
 907
 908         if(ath_numrxbufs == -1)
 909                 ath_numrxbufs = ATH_RXBUF;
 910
 911         if (ath_numrxdescs == -1)
 912                 ath_numrxdescs = ATH_RXDESC;
 913
 914         error = ath_descdma_setup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 915                                   "rx", ath_numrxdescs, 1,
 916                                   sizeof(struct ath_rx_buf),
 917                                   sizeof(struct ath_rx_desc));
 918         if (error != 0)
 919                 return error;
 920
 921         a_uint32_t i;
 922         struct ath_descdma *dd = &sc->sc_rxdma;
 923         struct ath_rx_desc *ds = (struct ath_rx_desc *)dd->dd_desc;
 924         struct ath_rx_desc *ds_prev = NULL;
 925
 926         asf_tailq_init(&sc->sc_rxdesc);
 927         asf_tailq_init(&sc->sc_rxdesc_idle);
 928
 929         for (i = 0; i < ath_numrxdescs; i++, ds++) {
 930
 931                 if (ds->ds_nbuf != ADF_NBUF_NULL) {
 932                         ds->ds_nbuf = ADF_NBUF_NULL;
 933                 }
 934
 935                 if (adf_nbuf_dmamap_create(sc->sc_dev, &ds->ds_dmap) != A_STATUS_OK) {
 936                         adf_os_assert(0);
 937                 }
 938
 939                 ds->ds_daddr = DS2PHYS(&sc->sc_rxdma, ds);
 940
 941                 if (ds_prev) {
 942                         ds_prev->ds_link = ds->ds_daddr;
 943                 }
 944
 945                 ds->ds_link = 0;
 946                 ds_prev = ds;
 947
 948                 asf_tailq_insert_tail(&sc->sc_rxdesc, ds, ds_list);
 949         }
 950
 951         error = ath_descdma_setup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 952                                   "tx", ATH_TXBUF + 1, ATH_TXDESC,
 953                                   sizeof(struct ath_tx_buf),
 954                                   sizeof(struct ath_tx_desc));
 955         if (error != 0) {
 956                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 957                                     ADF_OS_DMA_FROM_DEVICE);
 958                 return error;
 959         }
 960
 961         error = ath_descdma_setup(sc, &sc->sc_bdma, (ath_bufhead *)&sc->sc_bbuf,
 962                                   "beacon", ATH_BCBUF, 1,
 963                                   sizeof(struct ath_tx_buf),
 964                                   sizeof(struct ath_tx_desc));
 965         if (error != 0) {
 966                 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 967                                     ADF_OS_DMA_TO_DEVICE);
 968                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 969                                     ADF_OS_DMA_FROM_DEVICE);
 970                 return error;
 971         }
 972
 973         bf = asf_tailq_first(&sc->sc_txbuf);
 974         bf->bf_isaggr = bf->bf_isretried = bf->bf_retries = 0;
 975         asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
 976
 977         sc->sc_txbuf_held = bf;
 978
 979         return 0;
 980
 981 #undef DS2PHYS
 982 }
 983
 984 static void ath_desc_free(struct ath_softc_tgt *sc)
 985 {
 986         asf_tailq_insert_tail(&sc->sc_txbuf, sc->sc_txbuf_held, bf_list);
 987
 988         sc->sc_txbuf_held = NULL;
 989
 990         if (sc->sc_txdma.dd_desc_len != 0)
 991                 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 992                                     ADF_OS_DMA_TO_DEVICE);
 993         if (sc->sc_rxdma.dd_desc_len != 0)
 994                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 995                                     ADF_OS_DMA_FROM_DEVICE);
 996 }
 997
 998 /**********************/
 999 /* Interrupt Handling */
1000 /**********************/
1001
1002 adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl)
1003 {
1004         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl;
1005         struct ath_hal *ah = sc->sc_ah;
1006         HAL_INT status;
1007
1008         if (sc->sc_invalid)
1009                 return ADF_OS_IRQ_NONE;
1010
1011         if (!ah->ah_isInterruptPending(ah))
1012                 return ADF_OS_IRQ_NONE;
1013
1014         ah->ah_getPendingInterrupts(ah, &status);
1015
1016         status &= sc->sc_imask;
1017
1018         if (status & HAL_INT_FATAL) {
1019                 ah->ah_setInterrupts(ah, 0);
1020                 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
1021         } else {
1022                 if (status & HAL_INT_SWBA) {
1023                         WMI_SWBA_EVENT swbaEvt;
1024                         struct ath_txq *txq = ATH_TXQ(sc, 8);
1025
1026                         swbaEvt.tsf = ah->ah_getTsf64(ah);
1027                         swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq);
1028                         sc->sc_swba_tsf = ah->ah_getTsf64(ah);
1029
1030                         wmi_event(sc->tgt_wmi_handle,
1031                                   WMI_SWBA_EVENTID,
1032                                   &swbaEvt,
1033                                   sizeof(WMI_SWBA_EVENT));
1034
1035                         ath_tx_draintxq(sc, txq);
1036                 }
1037
1038                 if (status & HAL_INT_RXORN)
1039                         sc->sc_int_stats.ast_rxorn++;
1040
1041                 if (status & HAL_INT_RXEOL)
1042                         sc->sc_int_stats.ast_rxeol++;
1043
1044                 if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
1045                         if (status & HAL_INT_RX)
1046                                 sc->sc_int_stats.ast_rx++;
1047
1048                         ath_uapsd_processtriggers(sc);
1049
1050                         sc->sc_imask &= ~HAL_INT_RX;
1051                         ah->ah_setInterrupts(ah, sc->sc_imask);
1052
1053                         ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
1054                 }
1055
1056                 if (status & HAL_INT_TXURN) {
1057                         sc->sc_int_stats.ast_txurn++;
1058                         ah->ah_updateTxTrigLevel(ah, AH_TRUE);
1059                 }
1060
1061                 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq);
1062
1063                 if (status & HAL_INT_BMISS) {
1064                         ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_bmisstq);
1065                 }
1066
1067                 if (status & HAL_INT_GTT)
1068                         sc->sc_int_stats.ast_txto++;
1069
1070                 if (status & HAL_INT_CST)
1071                         sc->sc_int_stats.ast_cst++;
1072         }
1073
1074         return ADF_OS_IRQ_HANDLED;
1075 }
1076
1077 static void ath_fatal_tasklet(TQUEUE_ARG data )
1078 {
1079         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1080
1081         wmi_event(sc->tgt_wmi_handle, WMI_FATAL_EVENTID, NULL, 0);
1082 }
1083
1084 static void ath_bmiss_tasklet(TQUEUE_ARG data)
1085 {
1086         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1087
1088         wmi_event(sc->tgt_wmi_handle, WMI_BMISS_EVENTID, NULL, 0);
1089 }
1090
1091 /****************/
1092 /* WMI Commands */
1093 /****************/
1094
1095 static void ath_enable_intr_tgt(void *Context, A_UINT16 Command,
1096                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1097 {
1098         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1099         struct ath_hal *ah = sc->sc_ah;
1100         a_uint32_t intr;
1101
1102         if (data)
1103                 intr = (*(a_uint32_t *)data);
1104
1105         intr = adf_os_ntohl(intr);
1106
1107         if (intr & HAL_INT_SWBA) {
1108                 sc->sc_imask |= HAL_INT_SWBA;
1109         } else {
1110                 sc->sc_imask &= ~HAL_INT_SWBA;
1111         }
1112
1113         if (intr & HAL_INT_BMISS) {
1114                 sc->sc_imask |= HAL_INT_BMISS;
1115         }
1116
1117         ah->ah_setInterrupts(ah, sc->sc_imask);
1118         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1119 }
1120
1121 static void ath_init_tgt(void *Context, A_UINT16 Command,
1122                          A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1123 {
1124         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1125         struct ath_hal *ah = sc->sc_ah;
1126
1127         sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1128                 | HAL_INT_RXEOL | HAL_INT_RXORN
1129                 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1130
1131         sc->sc_imask |= HAL_INT_GTT;
1132
1133         if (ath_hal_getcapability(ah, HAL_CAP_HT))
1134                 sc->sc_imask |= HAL_INT_CST;
1135
1136         adf_os_setup_intr(sc->sc_dev, ath_intr);
1137         ah->ah_setInterrupts(ah, sc->sc_imask);
1138
1139         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1140 }
1141
1142 static void ath_int_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1143                               A_UINT8 *data, a_int32_t datalen)
1144 {
1145         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1146
1147         struct fusion_stats {
1148                 a_uint32_t ast_rx;
1149                 a_uint32_t ast_rxorn;
1150                 a_uint32_t ast_rxeol;
1151                 a_uint32_t ast_txurn;
1152                 a_uint32_t ast_txto;
1153                 a_uint32_t ast_cst;
1154         };
1155
1156         struct fusion_stats stats;
1157
1158         stats.ast_rx = sc->sc_int_stats.ast_rx;
1159         stats.ast_rxorn = sc->sc_int_stats.ast_rxorn;
1160         stats.ast_rxeol = sc->sc_int_stats.ast_rxeol;
1161         stats.ast_txurn = sc->sc_int_stats.ast_txurn;
1162         stats.ast_txto = sc->sc_int_stats.ast_txto;
1163         stats.ast_cst = sc->sc_int_stats.ast_cst;
1164
1165         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1166 }
1167
1168 static void ath_tx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1169                              A_UINT8 *data, a_int32_t datalen)
1170 {
1171         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1172
1173         struct fusion_stats {
1174                 a_uint32_t   ast_tx_xretries;
1175                 a_uint32_t   ast_tx_fifoerr;
1176                 a_uint32_t   ast_tx_filtered;
1177                 a_uint32_t   ast_tx_timer_exp;
1178                 a_uint32_t   ast_tx_shortretry;
1179                 a_uint32_t   ast_tx_longretry;
1180
1181                 a_uint32_t   tx_qnull;
1182                 a_uint32_t   tx_noskbs;
1183                 a_uint32_t   tx_nobufs;
1184         };
1185
1186         struct fusion_stats stats;
1187
1188         stats.ast_tx_xretries = sc->sc_tx_stats.ast_tx_xretries;
1189         stats.ast_tx_fifoerr = sc->sc_tx_stats.ast_tx_fifoerr;
1190         stats.ast_tx_filtered = sc->sc_tx_stats.ast_tx_filtered;
1191         stats.ast_tx_timer_exp = sc->sc_tx_stats.ast_tx_timer_exp;
1192         stats.ast_tx_shortretry = sc->sc_tx_stats.ast_tx_shortretry;
1193         stats.ast_tx_longretry = sc->sc_tx_stats.ast_tx_longretry;
1194         stats.tx_qnull = sc->sc_tx_stats.tx_qnull;
1195         stats.tx_noskbs = sc->sc_tx_stats.tx_noskbs;
1196         stats.tx_nobufs = sc->sc_tx_stats.tx_nobufs;
1197
1198         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1199 }
1200
1201 static void ath_rx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1202                              A_UINT8 *data, a_int32_t datalen)
1203 {
1204         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1205
1206         struct fusion_stats {
1207                 a_uint32_t   ast_rx_nobuf;
1208                 a_uint32_t   ast_rx_send;
1209                 a_uint32_t   ast_rx_done;
1210         };
1211
1212         struct fusion_stats stats;
1213
1214         stats.ast_rx_nobuf = sc->sc_rx_stats.ast_rx_nobuf;
1215         stats.ast_rx_send = sc->sc_rx_stats.ast_rx_send;
1216         stats.ast_rx_done = sc->sc_rx_stats.ast_rx_done;
1217
1218         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1219 }
1220
1221 static void ath_get_tgt_version(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1222                                 A_UINT8 *data, a_int32_t datalen)
1223 {
1224         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1225         struct wmi_fw_version ver;
1226
1227         ver.major = ATH_VERSION_MAJOR;
1228         ver.minor = ATH_VERSION_MINOR;
1229
1230         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &ver, sizeof(ver));
1231 }
1232
1233 static void ath_enable_aggr_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1234                                 A_UINT8 *data, a_int32_t datalen)
1235 {
1236         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1237         struct ath_aggr_info *aggr = (struct ath_aggr_info *)data;
1238         a_uint8_t nodeindex = aggr->nodeindex;
1239         a_uint8_t tidno = aggr->tidno;
1240         struct ath_node_target *an = NULL ;
1241         struct ath_atx_tid  *tid = NULL;
1242
1243         if (nodeindex >= TARGET_NODE_MAX) {
1244                 goto done;
1245         }
1246
1247         an = &sc->sc_sta[nodeindex];
1248         if (!an->an_valid) {
1249                 goto done;
1250         }
1251
1252         if (tidno >= WME_NUM_TID) {
1253                 adf_os_print("[%s] enable_aggr with invalid tid %d(node = %d)\n",
1254                              __FUNCTION__, tidno, nodeindex);
1255                 goto done;
1256         }
1257
1258         tid = ATH_AN_2_TID(an, tidno);
1259
1260         if (aggr->aggr_enable) {
1261                 tid->flag |= TID_AGGR_ENABLED;
1262         } else if ( tid->flag & TID_AGGR_ENABLED ) {
1263                 tid->flag &= ~TID_AGGR_ENABLED;
1264                 ath_tgt_tx_cleanup(sc, an, tid, 1);
1265         }
1266 done:
1267         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1268 }
1269
1270 static void ath_ic_update_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1271                               A_UINT8 *data, a_int32_t datalen)
1272 {
1273         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1274         struct ieee80211com_target *ic = (struct ieee80211com_target * )data;
1275         struct ieee80211com_target *ictgt = &sc->sc_ic ;
1276
1277         adf_os_mem_copy(ictgt, ic, sizeof(struct  ieee80211com_target));
1278
1279         ictgt->ic_ampdu_limit         = adf_os_ntohl(ic->ic_ampdu_limit);
1280
1281         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1282 }
1283
1284 static void ath_vap_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1285                                A_UINT8 *data, a_int32_t datalen)
1286 {
1287         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1288         struct ieee80211vap_target *vap;
1289         a_uint8_t vap_index;
1290
1291         vap = (struct ieee80211vap_target *)data;
1292
1293         vap->iv_rtsthreshold    = adf_os_ntohs(vap->iv_rtsthreshold);
1294         vap->iv_opmode          = adf_os_ntohl(vap->iv_opmode);
1295
1296         vap_index = vap->iv_vapindex;
1297
1298         adf_os_assert(sc->sc_vap[vap_index].av_valid == 0);
1299
1300         adf_os_mem_copy(&(sc->sc_vap[vap_index].av_vap), vap,
1301                         VAP_TARGET_SIZE);
1302
1303         sc->sc_vap[vap_index].av_bcbuf = asf_tailq_first(&(sc->sc_bbuf));
1304         sc->sc_vap[vap_index].av_valid = 1;
1305
1306         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1307 }
1308
1309 static void ath_node_create_tgt(void *Context, A_UINT16 Command,
1310                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1311 {
1312         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1313         struct ieee80211_node_target *node;
1314         a_uint8_t vap_index;
1315         a_uint8_t node_index;
1316
1317         node = (struct ieee80211_node_target *)data;
1318
1319         node_index = node->ni_nodeindex;
1320
1321         node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1322         node->ni_flags = adf_os_ntohs(node->ni_flags);
1323         node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1324
1325         adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1326                         NODE_TARGET_SIZE);
1327
1328         vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1329         sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1330         if(sc->sc_sta[node_index].ni.ni_is_vapnode == 1)
1331                 sc->sc_vap[vap_index].av_vap.iv_nodeindex = node_index;
1332
1333         sc->sc_sta[node_index].an_valid = 1;
1334         sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1335         sc->sc_sta[node_index].ni.ni_iv16 = 0;
1336         sc->sc_sta[node_index].ni.ni_iv32 = 0;
1337
1338         owl_tgt_node_init(&sc->sc_sta[node_index]);
1339
1340         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1341 }
1342
1343 static void ath_node_cleanup_tgt(void *Context, A_UINT16 Command,
1344                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1345 {
1346         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1347         a_uint8_t node_index;
1348         a_uint8_t *nodedata;
1349
1350         nodedata = (a_uint8_t *)data;
1351         node_index = *nodedata;
1352         sc->sc_sta[node_index].an_valid = 0;
1353
1354         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1355 }
1356
1357 static void ath_node_update_tgt(void *Context, A_UINT16 Command,
1358                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1359 {
1360         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1361         struct ieee80211_node_target *node;
1362         a_uint8_t vap_index;
1363         a_uint8_t node_index;
1364
1365         node = (struct ieee80211_node_target *)data;
1366
1367         node_index = node->ni_nodeindex;
1368
1369         node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1370         node->ni_flags = adf_os_ntohs(node->ni_flags);
1371         node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1372
1373         adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1374                         NODE_TARGET_SIZE);
1375
1376         vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1377         sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1378
1379         sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1380         sc->sc_sta[node_index].ni.ni_iv16 = 0;
1381         sc->sc_sta[node_index].ni.ni_iv32 = 0;
1382
1383         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1384 }
1385
1386 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
1387                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1388 {
1389         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1390         struct ath_hal *ah = sc->sc_ah;
1391         a_uint32_t addr;
1392         a_uint32_t val[32];
1393         int i;
1394
1395         for (i = 0; i < datalen; i += sizeof(a_int32_t)) {
1396                 addr = *(a_uint32_t *)(data + i);
1397                 addr = adf_os_ntohl(addr);
1398
1399                 if ((addr & 0xffffe000) == 0x2000) {
1400                         /* SEEPROM */
1401                         ath_hal_reg_read_target(ah, addr);
1402                         if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) {
1403                                 adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
1404                         }
1405                         val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
1406                 } else if (addr > 0xffff) {
1407                         val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr;
1408                 } else
1409                         val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr);
1410
1411                 val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]);
1412         }
1413
1414         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
1415 }
1416
1417 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
1418                                   A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1419 {
1420         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1421         struct ath_hal *ah = sc->sc_ah;
1422         int i;
1423         struct registerWrite {
1424                 a_uint32_t reg;
1425                 a_uint32_t val;
1426         }*t;
1427
1428         for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
1429                 t = (struct registerWrite *)(data+i);
1430
1431                 if( t->reg > 0xffff ) {
1432                         a_uint32_t *pReg = (a_uint32_t *)t->reg;
1433
1434                         *pReg = t->val;
1435
1436 #if defined(PROJECT_K2)
1437                         if( t->reg == 0x50040 ) {
1438                                 static uint8_t flg=0;
1439
1440                                 if( flg == 0 ) {
1441                                         A_CLOCK_INIT(117);
1442                                         A_UART_HWINIT(117*1000*1000, 19200);
1443                                         flg = 1;
1444                                 }
1445                         }
1446 #endif
1447                 } else {
1448 #if defined(PROJECT_K2)
1449                         if( t->reg == 0x7014 ) {
1450                                 static uint8_t resetPLL = 0;
1451                                 a_uint32_t *pReg;
1452
1453                                 if( resetPLL == 0 ) {
1454                                         t->reg = 0x50044;
1455                                         pReg = (a_uint32_t *)t->reg;
1456                                         *pReg = 0;
1457                                         ath_hal_reg_write_target(ah, 0x786c,
1458                                                  ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
1459                                         ath_hal_reg_write_target(ah, 0x786c,
1460                                                  ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
1461                                         *pReg = 0x20;
1462                                         resetPLL = 1;
1463                                 }
1464                                 t->reg = 0x7014;
1465                         }
1466 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
1467                         if( t->reg == 0x7014 ){
1468                                 static uint8_t resetPLL = 0;
1469
1470                                 if( resetPLL == 0 ) {
1471                                         ath_hal_reg_write_target(ah, 0x7890,
1472                                                  ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
1473                                         ath_hal_reg_write_target(ah, 0x7890,
1474                                                  ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
1475                                         resetPLL = 1;
1476                                 }
1477                         }
1478 #endif
1479                         ath_hal_reg_write_target(ah,t->reg,t->val);
1480                 }
1481         }
1482
1483         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1484 }
1485
1486 static void ath_vap_delete_tgt(void *Context, A_UINT16 Command,
1487                                A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1488 {
1489         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1490         a_uint8_t vap_index;
1491
1492         vap_index = *(a_uint8_t *)data;
1493
1494         sc->sc_vap[vap_index].av_valid = 0;
1495         sc->sc_vap[vap_index].av_bcbuf = NULL;
1496         ath_node_vdelete_tgt(sc, vap_index);
1497         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1498 }
1499
1500 static void ath_disable_intr_tgt(void *Context, A_UINT16 Command,
1501                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1502 {
1503         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1504         struct ath_hal *ah = sc->sc_ah;
1505
1506         ah->ah_setInterrupts(ah, 0);
1507         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1508 }
1509
1510 static void ath_flushrecv_tgt(void *Context, A_UINT16 Command,
1511                               A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1512 {
1513         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1514         struct ath_rx_buf *bf;
1515
1516         asf_tailq_foreach(bf, &sc->sc_rxbuf, bf_list)
1517                 if (bf->bf_skb != NULL) {
1518                         adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap,
1519                                        ADF_OS_DMA_FROM_DEVICE);
1520                         ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead));
1521                         bf->bf_skb = NULL;
1522                 }
1523
1524         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1525 }
1526
1527 static void ath_tx_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1528                                 A_UINT8 *data, a_int32_t datalen)
1529 {
1530         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1531         a_uint32_t q = *(a_uint32_t *)data;
1532         struct ath_txq *txq = NULL;
1533
1534         q = adf_os_ntohl(q);
1535         txq = ATH_TXQ(sc, q);
1536
1537         ath_tx_draintxq(sc, txq);
1538         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1539 }
1540
1541 static void ath_draintxq_tgt(void *Context, A_UINT16 Command,
1542                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1543 {
1544         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1545         HAL_BOOL b = (HAL_BOOL) *(a_int32_t *)data;
1546
1547         ath_draintxq(Context, b);
1548         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1549 }
1550
1551 static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command,
1552                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1553 {
1554         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1555         struct ath_hal *ah = sc->sc_ah;
1556
1557         ah->ah_abortTxDma(sc->sc_ah);
1558         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1559 }
1560
1561 static void ath_aborttxq_tgt(void *Context, A_UINT16 Command,
1562                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1563 {
1564
1565         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1566         a_uint16_t i;
1567
1568         for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
1569                 if (ATH_TXQ_SETUP(sc, i))
1570                         ath_tx_draintxq(sc, ATH_TXQ(sc,i));
1571         }
1572
1573         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1574 }
1575
1576 static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command,
1577                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1578 {
1579         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1580         struct ath_hal *ah = sc->sc_ah;
1581         a_uint32_t q;
1582
1583         if (data)
1584                 q = *(a_uint32_t *)data;
1585
1586         q = adf_os_ntohl(q);
1587         ah->ah_stopTxDma(ah, q);
1588         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1589 }
1590
1591 static void ath_startrecv_tgt(void *Context, A_UINT16 Command,
1592                               A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1593 {
1594
1595         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1596
1597         ath_startrecv(sc);
1598         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1599 }
1600
1601 static void ath_stoprecv_tgt(void *Context, A_UINT16 Command,
1602                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1603 {
1604         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1605         struct ath_hal *ah = sc->sc_ah;
1606
1607         ah->ah_stopPcuReceive(ah);
1608         ah->ah_setRxFilter(ah, 0);
1609         ah->ah_stopDmaReceive(ah);
1610
1611         sc->sc_rxlink = NULL;
1612         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1613 }
1614
1615 static void ath_setcurmode_tgt(void *Context, A_UINT16 Command,
1616                                A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1617 {
1618         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1619         a_uint16_t mode;
1620
1621         mode= *((a_uint16_t *)data);
1622         mode = adf_os_ntohs(mode);
1623
1624         ath_setcurmode(sc, mode);
1625
1626         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1627 }
1628
1629 static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1630                                  A_UINT8 *data, a_int32_t datalen)
1631 {
1632         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1633         struct ath_hal *ah = sc->sc_ah;
1634
1635         ath_desc_free(sc);
1636         ah->ah_detach(ah);
1637         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1638         adf_os_mem_free(sc);
1639 }
1640
1641 static void handle_echo_command(void *pContext, A_UINT16 Command,
1642                                 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1643 {
1644         wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length);
1645 }
1646
1647 static void handle_rc_state_change_cmd(void *Context, A_UINT16 Command,
1648                                        A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1649
1650 {
1651         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1652         struct wmi_rc_state_change_cmd *wmi_data = (struct wmi_rc_state_change_cmd *)buffer;
1653
1654         a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1655
1656         ath_rate_newstate(sc, &sc->sc_vap[wmi_data->vap_index].av_vap,
1657                           wmi_data->vap_state,
1658                           capflag,
1659                           &wmi_data->rs);
1660
1661         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1662 }
1663
1664 static void handle_rc_rate_update_cmd(void *Context, A_UINT16 Command,
1665                                       A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1666 {
1667         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1668         struct wmi_rc_rate_update_cmd *wmi_data = (struct wmi_rc_rate_update_cmd *)buffer;
1669
1670         a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1671
1672         ath_rate_node_update(sc, &sc->sc_sta[wmi_data->node_index],
1673                              wmi_data->isNew,
1674                              capflag,
1675                              &wmi_data->rs);
1676
1677         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1678 }
1679
1680 static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command,
1681                                      A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1682 {
1683         adf_os_assert(0);
1684 }
1685
1686 static void ath_rc_mask_tgt(void *Context, A_UINT16 Command,
1687                             A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1688 {
1689         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1690         struct wmi_rc_rate_mask_cmd *wmi_data = (struct wmi_rc_rate_mask_cmd *)buffer;
1691         int idx, band, i;
1692
1693         idx = wmi_data->vap_index;
1694         band = wmi_data->band;
1695
1696         sc->sc_vap[idx].av_rate_mask[band] = adf_os_ntohl(wmi_data->mask);
1697
1698         if (sc->sc_vap[idx].av_rate_mask[band]) {
1699                 for (i = 0; i < RATE_TABLE_SIZE; i++) {
1700                         if ((1 << i) & sc->sc_vap[idx].av_rate_mask[band]) {
1701                                 sc->sc_vap[idx].av_minrateidx[band] = i;
1702                                 break;
1703                         }
1704                 }
1705         } else {
1706                 sc->sc_vap[idx].av_minrateidx[band] = 0;
1707         }
1708
1709         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1710 }
1711
1712 static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] =
1713 {
1714         {handle_echo_command,         WMI_ECHO_CMDID,               0},
1715         {dispatch_magpie_sys_cmds,    WMI_ACCESS_MEMORY_CMDID,      0},
1716         {ath_get_tgt_version,         WMI_GET_FW_VERSION,           0},
1717         {ath_disable_intr_tgt,        WMI_DISABLE_INTR_CMDID,       0},
1718         {ath_enable_intr_tgt,         WMI_ENABLE_INTR_CMDID,        0},
1719         {ath_init_tgt,                WMI_ATH_INIT_CMDID,           0},
1720         {ath_aborttxq_tgt,            WMI_ABORT_TXQ_CMDID,          0},
1721         {ath_stop_tx_dma_tgt,         WMI_STOP_TX_DMA_CMDID,        0},
1722         {ath_aborttx_dma_tgt,         WMI_ABORT_TX_DMA_CMDID,       0},
1723         {ath_tx_draintxq_tgt,         WMI_DRAIN_TXQ_CMDID,          0},
1724         {ath_draintxq_tgt,            WMI_DRAIN_TXQ_ALL_CMDID,      0},
1725         {ath_startrecv_tgt,           WMI_START_RECV_CMDID,         0},
1726         {ath_stoprecv_tgt,            WMI_STOP_RECV_CMDID,          0},
1727         {ath_flushrecv_tgt,           WMI_FLUSH_RECV_CMDID,         0},
1728         {ath_setcurmode_tgt,          WMI_SET_MODE_CMDID,           0},
1729         {ath_node_create_tgt,         WMI_NODE_CREATE_CMDID,        0},
1730         {ath_node_cleanup_tgt,        WMI_NODE_REMOVE_CMDID,        0},
1731         {ath_vap_delete_tgt,          WMI_VAP_REMOVE_CMDID,         0},
1732         {ath_vap_create_tgt,          WMI_VAP_CREATE_CMDID,         0},
1733         {ath_hal_reg_read_tgt,        WMI_REG_READ_CMDID,           0},
1734         {ath_hal_reg_write_tgt,       WMI_REG_WRITE_CMDID,          0},
1735         {handle_rc_state_change_cmd,  WMI_RC_STATE_CHANGE_CMDID,    0},
1736         {handle_rc_rate_update_cmd,   WMI_RC_RATE_UPDATE_CMDID,     0},
1737         {ath_ic_update_tgt,           WMI_TARGET_IC_UPDATE_CMDID,   0},
1738         {ath_enable_aggr_tgt,         WMI_TX_AGGR_ENABLE_CMDID,     0},
1739         {ath_detach_tgt,              WMI_TGT_DETACH_CMDID,         0},
1740         {ath_node_update_tgt,         WMI_NODE_UPDATE_CMDID,        0},
1741         {ath_int_stats_tgt,           WMI_INT_STATS_CMDID,          0},
1742         {ath_tx_stats_tgt,            WMI_TX_STATS_CMDID,           0},
1743         {ath_rx_stats_tgt,            WMI_RX_STATS_CMDID,           0},
1744         {ath_rc_mask_tgt,             WMI_BITRATE_MASK_CMDID,       0},
1745 };
1746
1747 /*****************/
1748 /* Init / Deinit */
1749 /*****************/
1750
1751 static void htc_setup_comp(void)
1752 {
1753 }
1754
1755 static A_UINT8 tgt_ServiceConnect(HTC_SERVICE *pService,
1756                                   HTC_ENDPOINT_ID eid,
1757                                   A_UINT8 *pDataIn,
1758                                   a_int32_t LengthIn,
1759                                   A_UINT8 *pDataOut,
1760                                   a_int32_t *pLengthOut)
1761 {
1762         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)pService->ServiceCtx;
1763
1764         switch(pService->ServiceID) {
1765         case WMI_CONTROL_SVC:
1766                 sc->wmi_command_ep= eid;
1767                 break;
1768         case WMI_BEACON_SVC:
1769                 sc->beacon_ep= eid;
1770                 break;
1771         case WMI_CAB_SVC:
1772                 sc->cab_ep= eid;
1773                 break;
1774         case WMI_UAPSD_SVC:
1775                 sc->uapsd_ep= eid;
1776                 break;
1777         case WMI_MGMT_SVC:
1778                 sc->mgmt_ep= eid;
1779                 break;
1780         case WMI_DATA_VO_SVC:
1781                 sc->data_VO_ep = eid;
1782                 break;
1783         case WMI_DATA_VI_SVC:
1784                 sc->data_VI_ep = eid;
1785                 break;
1786         case WMI_DATA_BE_SVC:
1787                 sc->data_BE_ep = eid;
1788                 break;
1789         case WMI_DATA_BK_SVC:
1790                 sc->data_BK_ep = eid;
1791                 break;
1792         default:
1793                 adf_os_assert(0);
1794         }
1795
1796         return HTC_SERVICE_SUCCESS;
1797 }
1798
1799 static void tgt_reg_service(struct ath_softc_tgt *sc, HTC_SERVICE *svc,
1800                             int svcId, HTC_SERVICE_ProcessRecvMsg recvMsg)
1801 {
1802         svc->ProcessRecvMsg = recvMsg;
1803         svc->ProcessSendBufferComplete = tgt_HTCSendCompleteHandler;
1804         svc->ProcessConnect = tgt_ServiceConnect;
1805         svc->MaxSvcMsgSize = 1600;
1806         svc->TrailerSpcCheckLimit = 0;
1807         svc->ServiceID = svcId;
1808         svc->ServiceCtx = sc;
1809         HTC_RegisterService(sc->tgt_htc_handle, svc);
1810 }
1811
1812 static void tgt_hif_htc_wmi_init(struct ath_softc_tgt *sc)
1813 {
1814         HTC_CONFIG htc_conf;
1815         WMI_SVC_CONFIG wmiConfig;
1816         WMI_DISPATCH_TABLE *Magpie_Sys_Commands_Tbl;
1817
1818         /* Init dynamic buf pool */
1819         sc->pool_handle = BUF_Pool_init(sc->sc_hdl);
1820
1821         /* Init target-side HIF */
1822         sc->tgt_hif_handle = HIF_init(0);
1823
1824         /* Init target-side HTC */
1825         htc_conf.HIFHandle = sc->tgt_hif_handle;
1826         htc_conf.CreditSize = 320;
1827         htc_conf.CreditNumber = ATH_TXBUF;
1828         htc_conf.OSHandle = sc->sc_hdl;
1829         htc_conf.PoolHandle = sc->pool_handle;
1830         sc->tgt_htc_handle = HTC_init(htc_setup_comp, &htc_conf);
1831 #if defined(PROJECT_MAGPIE)
1832         init_htc_handle = sc->tgt_htc_handle;
1833 #endif
1834
1835         tgt_reg_service(sc, &sc->htc_beacon_service, WMI_BEACON_SVC, tgt_HTCRecv_beaconhandler);
1836         tgt_reg_service(sc, &sc->htc_cab_service, WMI_CAB_SVC, tgt_HTCRecv_cabhandler);
1837         tgt_reg_service(sc, &sc->htc_uapsd_service, WMI_UAPSD_SVC, tgt_HTCRecv_uapsdhandler);
1838         tgt_reg_service(sc, &sc->htc_mgmt_service, WMI_MGMT_SVC, tgt_HTCRecv_mgmthandler);
1839         tgt_reg_service(sc, &sc->htc_data_BE_service, WMI_DATA_BE_SVC, tgt_HTCRecvMessageHandler);
1840         tgt_reg_service(sc, &sc->htc_data_BK_service, WMI_DATA_BK_SVC, tgt_HTCRecvMessageHandler);
1841         tgt_reg_service(sc, &sc->htc_data_VI_service, WMI_DATA_VI_SVC, tgt_HTCRecvMessageHandler);
1842         tgt_reg_service(sc, &sc->htc_data_VO_service, WMI_DATA_VO_SVC, tgt_HTCRecvMessageHandler);
1843
1844         /* Init target-side WMI */
1845         Magpie_Sys_Commands_Tbl = (WMI_DISPATCH_TABLE *)adf_os_mem_alloc(sizeof(WMI_DISPATCH_TABLE));
1846         adf_os_mem_zero(Magpie_Sys_Commands_Tbl, sizeof(WMI_DISPATCH_TABLE));
1847         Magpie_Sys_Commands_Tbl->NumberOfEntries = WMI_DISPATCH_ENTRY_COUNT(Magpie_Sys_DispatchEntries);
1848         Magpie_Sys_Commands_Tbl->pTable = Magpie_Sys_DispatchEntries;
1849
1850         adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG));
1851         wmiConfig.HtcHandle = sc->tgt_htc_handle;
1852         wmiConfig.PoolHandle = sc->pool_handle;
1853         wmiConfig.MaxCmdReplyEvts = ATH_WMI_MAX_CMD_REPLY;
1854         wmiConfig.MaxEventEvts = ATH_WMI_MAX_EVENTS;
1855
1856         sc->tgt_wmi_handle = WMI_Init(&wmiConfig);
1857         Magpie_Sys_Commands_Tbl->pContext = sc;
1858         WMI_RegisterDispatchTable(sc->tgt_wmi_handle, Magpie_Sys_Commands_Tbl);
1859
1860         HTC_NotifyTargetInserted(sc->tgt_htc_handle);
1861
1862         /* Start HTC messages exchange */
1863         HTC_Ready(sc->tgt_htc_handle);
1864 }
1865
1866 a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_device_t osdev)
1867 {
1868         struct ath_hal *ah;
1869         HAL_STATUS status;
1870         a_int32_t error = 0, i, flags = 0;
1871         a_uint8_t csz;
1872
1873         adf_os_pci_config_read8(osdev, ATH_PCI_CACHE_LINE_SIZE, &csz);
1874
1875         if (csz == 0)
1876                 csz = 16;
1877         sc->sc_cachelsz = csz << 2;
1878
1879         sc->sc_dev = osdev;
1880         sc->sc_hdl = osdev;
1881
1882         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_rxtq, ath_tgt_rx_tasklet, sc);
1883         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_txtq, owl_tgt_tx_tasklet, sc);
1884         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_bmisstq, ath_bmiss_tasklet, sc);
1885         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_fataltq, ath_fatal_tasklet, sc);
1886
1887         flags |= AH_USE_EEPROM;
1888         ah = _ath_hal_attach_tgt(devid, sc, sc->sc_dev, flags, &status);
1889         if (ah == NULL) {
1890                 error = ENXIO;
1891                 goto bad;
1892         }
1893         sc->sc_ah = ah;
1894
1895         tgt_hif_htc_wmi_init(sc);
1896
1897         sc->sc_bhalq = HAL_NUM_TX_QUEUES - 1;
1898
1899         ath_rate_setup(sc, IEEE80211_MODE_11NA);
1900         ath_rate_setup(sc, IEEE80211_MODE_11NG);
1901
1902         sc->sc_rc = ath_rate_attach(sc);
1903         if (sc->sc_rc == NULL) {
1904                 error = EIO;
1905                 goto bad2;
1906         }
1907
1908         for (i=0; i < TARGET_NODE_MAX; i++) {
1909                 sc->sc_sta[i].an_rcnode = adf_os_mem_alloc(sc->sc_rc->arc_space);
1910         }
1911
1912         error = ath_desc_alloc(sc);
1913         if (error != 0) {
1914                 goto bad;
1915         }
1916
1917         BUF_Pool_create_pool(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ath_numrxdescs, 1664);
1918
1919         ath_tgt_txq_setup(sc);
1920         sc->sc_imask =0;
1921         ah->ah_setInterrupts(ah, 0);
1922
1923         return 0;
1924 bad:
1925 bad2:
1926         ath_desc_free(sc);
1927         if (ah)
1928                 ah->ah_detach(ah);
1929 }
1930
1931 static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)
1932 {
1933         HTC_NotifyTargetDetached(sc->tgt_htc_handle);
1934
1935         WMI_Shutdown(sc->tgt_wmi_handle);
1936         HTC_Shutdown(sc->tgt_htc_handle);
1937         HIF_shutdown(sc->tgt_hif_handle);
1938         BUF_Pool_shutdown(sc->pool_handle);
1939 }
1940
1941 a_int32_t ath_detach(struct ath_softc_tgt *sc)
1942 {
1943         tgt_hif_htc_wmi_shutdown(sc);
1944 }