target_firmware/wlan/if_ath.c

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <adf_os_types.h>
  37 #include <adf_os_pci.h>
  38 #include <adf_os_dma.h>
  39 #include <adf_os_timer.h>
  40 #include <adf_os_lock.h>
  41 #include <adf_os_io.h>
  42 #include <adf_os_mem.h>
  43 #include <adf_os_util.h>
  44 #include <adf_os_stdtypes.h>
  45 #include <adf_os_defer.h>
  46 #include <adf_os_atomic.h>
  47 #include <adf_nbuf.h>
  48 #include <adf_net.h>
  49 #include <adf_net_wcmd.h>
  50 #include <adf_os_irq.h>
  51
  52 #include <if_ath_pci.h>
  53 #include "if_ethersubr.h"
  54 #include "if_llc.h"
  55 #include "ieee80211_var.h"
  56 #include "ieee80211_proto.h"
  57 #include "if_athrate.h"
  58 #include "if_athvar.h"
  59 #include "ah_desc.h"
  60
  61 static a_int32_t ath_numrxbufs = -1;
  62 static a_int32_t ath_numrxdescs = -1;
  63
  64 #if defined(PROJECT_MAGPIE)
  65 uint32_t *init_htc_handle = 0;
  66 #endif
  67
  68 #define RX_ENDPOINT_ID 3
  69 #define ATH_CABQ_HANDLING_THRESHOLD 9000
  70 #define UAPSDQ_NUM   9
  71 #define CABQ_NUM     8
  72
  73 void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id, A_UINT8 *buffer, a_int32_t Length);
  74 void owl_tgt_tx_tasklet(TQUEUE_ARG data);
  75 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
  76 void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length);
  77 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
  78 extern struct ath_buf * ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
  79 extern void  ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
  80 extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
  81 extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,  owl_txq_state_t txqstate);
  82 void owl_tgt_node_init(struct ath_node_target * an);
  83 void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
  84 void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
  85
  86 /*************/
  87 /* Utilities */
  88 /*************/
  89
  90 #undef adf_os_cpu_to_le16
  91
  92 static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
  93 {
  94         return ((((x) & 0xff00) >> 8) |   (((x) & 0x00ff) << 8));
  95 }
  96
  97 /*
  98  * Extend a 32 bit TSF to 64 bit, taking wrapping into account.
  99  */
 100 static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
 101 {
 102         u_int64_t tsf;
 103         u_int32_t tsf_low;
 104         u_int64_t tsf64;
 105
 106         tsf = ath_hal_gettsf64(sc->sc_ah);
 107         tsf_low = tsf & 0xffffffff;
 108         tsf64 = (tsf & ~0xffffffffULL) | rstamp;
 109
 110         if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000))
 111                 tsf64 -= 0x100000000ULL;
 112
 113         if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000))
 114                 tsf64 += 0x100000000ULL;
 115
 116         return tsf64;
 117 }
 118
 119 static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode)
 120 {
 121         struct ath_hal *ah = sc->sc_ah;
 122         const HAL_RATE_TABLE *rt;
 123
 124         switch (mode) {
 125         case IEEE80211_MODE_11NA:
 126                 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11NA);
 127                 break;
 128         case IEEE80211_MODE_11NG:
 129                 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11NG);
 130                 break;
 131         default:
 132                 return 0;
 133         }
 134         rt = sc->sc_rates[mode];
 135         if (rt == NULL)
 136                 return 0;
 137
 138         return 1;
 139 }
 140
 141 static void ath_setcurmode(struct ath_softc_tgt *sc,
 142                            enum ieee80211_phymode mode)
 143 {
 144         const HAL_RATE_TABLE *rt;
 145         a_int32_t i;
 146
 147         adf_os_mem_set(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
 148
 149         rt = sc->sc_rates[mode];
 150         adf_os_assert(rt != NULL);
 151
 152         for (i = 0; i < rt->rateCount; i++) {
 153                 sc->sc_rixmap[rt->info[i].rateCode] = i;
 154         }
 155
 156         sc->sc_currates = rt;
 157         sc->sc_curmode = mode;
 158         sc->sc_protrix = ((mode == IEEE80211_MODE_11NG) ? 3 : 0);
 159
 160 }
 161
 162 void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
 163                A_UINT8 *buffer, a_int32_t Length)
 164 {
 165         adf_nbuf_t netbuf = ADF_NBUF_NULL;
 166         a_uint8_t *pData;
 167
 168         netbuf = WMI_AllocEvent(handle, WMI_EVT_CLASS_CMD_EVENT,
 169                                 sizeof(WMI_CMD_HDR) + Length);
 170
 171         if (netbuf == ADF_NBUF_NULL) {
 172                 adf_os_print("Buf null\n");
 173                 return;
 174         }
 175
 176         if (buffer != NULL && Length != 0 && Length < WMI_SVC_MAX_BUFFERED_EVENT_SIZE) {
 177                 pData = adf_nbuf_put_tail(netbuf, Length);
 178                 adf_os_mem_copy(pData, buffer, Length);
 179         }
 180
 181         WMI_SendEvent(handle, netbuf, evt_id, 0, Length);
 182 }
 183
 184 void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo,
 185                  A_UINT8 *buffer, a_int32_t Length)
 186 {
 187         adf_nbuf_t netbuf = ADF_NBUF_NULL;
 188         A_UINT8 *pData;
 189
 190         netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY,
 191                                 sizeof(WMI_CMD_HDR) + Length);
 192
 193         if (netbuf == ADF_NBUF_NULL) {
 194                 adf_os_assert(0);
 195                 return;
 196         }
 197
 198         if (Length != 0 && buffer != NULL) {
 199                 pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length);
 200                 adf_os_mem_copy(pData, buffer, Length);
 201         }
 202
 203         WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length);
 204 }
 205
 206 static void ath_node_vdelete_tgt(struct ath_softc_tgt *sc, a_uint8_t vap_index)
 207 {
 208         a_int32_t i;
 209
 210         for (i = 0; i < TARGET_NODE_MAX; i++) {
 211                 if(sc->sc_sta[i].ni.ni_vapindex == vap_index)
 212                         sc->sc_sta[i].an_valid = 0;
 213         }
 214 }
 215
 216 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp)
 217 {
 218         if (sc->sc_curmode == IEEE80211_MODE_11NG)
 219                 return avp->av_minrateidx[0];
 220         else if (sc->sc_curmode == IEEE80211_MODE_11NA)
 221                 return avp->av_minrateidx[1];
 222
 223         return 0;
 224 }
 225
 226 /******/
 227 /* RX */
 228 /******/
 229
 230 static adf_nbuf_t ath_alloc_skb_align(struct ath_softc_tgt *sc,
 231                                       a_uint32_t size, a_uint32_t align)
 232 {
 233         adf_nbuf_t skb;
 234
 235         skb = BUF_Pool_alloc_buf_align(sc->pool_handle, POOL_ID_WLAN_RX_BUF,
 236                                        RX_HEADER_SPACE, align);
 237         return skb;
 238 }
 239
 240 static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *ds)
 241 {
 242         struct ath_hal *ah = sc->sc_ah;
 243         struct ath_rx_desc *ds_held;
 244         a_uint8_t *anbdata;
 245         a_uint32_t anblen;
 246
 247         if (!sc->sc_rxdesc_held) {
 248                 sc->sc_rxdesc_held = ds;
 249                 return 0;
 250         }
 251
 252         ds_held = sc->sc_rxdesc_held;
 253         sc->sc_rxdesc_held = ds;
 254         ds = ds_held;
 255
 256         if (ds->ds_nbuf == ADF_NBUF_NULL) {
 257                 ds->ds_nbuf = ath_alloc_skb_align(sc, sc->sc_rxbufsize, sc->sc_cachelsz);
 258                 if (ds->ds_nbuf == ADF_NBUF_NULL) {
 259                         sc->sc_rxdesc_held = ds;
 260                         sc->sc_rx_stats.ast_rx_nobuf++;
 261                         return ENOMEM;
 262                 }
 263                 adf_nbuf_map(sc->sc_dev, ds->ds_dmap, ds->ds_nbuf, ADF_OS_DMA_FROM_DEVICE);
 264                 adf_nbuf_dmamap_info(ds->ds_dmap, &ds->ds_dmap_info);
 265                 ds->ds_data = ds->ds_dmap_info.dma_segs[0].paddr;
 266         }
 267
 268         ds->ds_link = 0;
 269         adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
 270
 271         ath_hal_setuprxdesc(ah, ds,
 272                             adf_nbuf_tailroom(ds->ds_nbuf),
 273                             0);
 274
 275         if (sc->sc_rxlink == NULL) {
 276                 ath_hal_putrxbuf(ah, ds->ds_daddr);
 277         }
 278         else {
 279                 *sc->sc_rxlink = ds->ds_daddr;
 280         }
 281         sc->sc_rxlink = &ds->ds_link;
 282         ath_hal_rxena(ah);
 283
 284         return 0;
 285 }
 286
 287 static void ath_rx_complete(struct ath_softc_tgt *sc, adf_nbuf_t buf)
 288 {
 289         struct ath_rx_desc *ds;
 290         adf_nbuf_t buf_tmp;
 291         adf_nbuf_queue_t nbuf_head;
 292
 293         adf_nbuf_split_to_frag(buf, &nbuf_head);
 294         ds = asf_tailq_first(&sc->sc_rxdesc_idle);
 295
 296         while (ds) {
 297                 struct ath_rx_desc *ds_tmp;
 298                 buf_tmp = adf_nbuf_queue_remove(&nbuf_head);
 299
 300                 if (buf_tmp == NULL) {
 301                         break;
 302                 }
 303
 304                 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, buf_tmp);
 305
 306                 ds_tmp = ds;
 307                 ds = asf_tailq_next(ds, ds_list);
 308
 309                 ath_rxdesc_init(sc, ds_tmp);
 310
 311                 asf_tailq_remove(&sc->sc_rxdesc_idle, ds_tmp, ds_list);
 312                 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_tmp, ds_list);
 313         }
 314 }
 315
 316 static void tgt_HTCSendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t buf, void *ServiceCtx)
 317 {
 318         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 319
 320         if (Endpt == RX_ENDPOINT_ID) {
 321                 sc->sc_rx_stats.ast_rx_done++;
 322                 ath_rx_complete(sc, buf);
 323         }
 324 }
 325
 326 static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc)
 327 {
 328         struct ath_hal *ah = sc->sc_ah;
 329         struct ath_rx_buf *bf = NULL;
 330         struct ath_rx_desc *ds, *ds_head, *ds_tail, *ds_tmp;
 331         a_int32_t retval;
 332         a_uint32_t cnt = 0;
 333         a_uint16_t frame_len = 0;
 334         a_uint64_t tsf;
 335
 336 #define PA2DESC(_sc, _pa)                                               \
 337         ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc +         \
 338                              ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
 339
 340         tsf = ath_hal_gettsf64(ah);
 341         bf = asf_tailq_first(&sc->sc_rxbuf);
 342
 343         ds = asf_tailq_first(&sc->sc_rxdesc);
 344         ds_head = ds;
 345
 346         while(ds) {
 347                 ++cnt;
 348
 349                 if (cnt == ath_numrxbufs - 1) {
 350                         adf_os_print("VERY LONG PACKET!!!!!\n");
 351                         ds_tail = ds;
 352                         ds_tmp = ds_head;
 353                         while (ds_tmp) {
 354                                 struct ath_rx_desc *ds_rmv;
 355                                 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
 356                                 ds_rmv = ds_tmp;
 357                                 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
 358
 359                                 if (ds_tmp == NULL) {
 360                                         adf_os_print("ds_tmp is NULL\n");
 361                                         adf_os_assert(0);
 362                                 }
 363
 364                                 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ds_rmv->ds_nbuf);
 365                                 ds_rmv->ds_nbuf = ADF_NBUF_NULL;
 366
 367                                 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
 368                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 369                                         asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
 370                                 }
 371                                 else {
 372                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 373                                         asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
 374                                 }
 375
 376                                 if (ds_rmv == ds_tail) {
 377                                         break;
 378                                 }
 379                         }
 380                         break;
 381                 }
 382
 383                 if (ds->ds_link == 0) {
 384                         break;
 385                 }
 386
 387                 if (bf->bf_status & ATH_BUFSTATUS_DONE) {
 388                         continue;
 389                 }
 390
 391                 retval = ath_hal_rxprocdescfast(ah, ds, ds->ds_daddr,
 392                                                 PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
 393                 if (HAL_EINPROGRESS == retval) {
 394                         break;
 395                 }
 396
 397                 if (adf_nbuf_len(ds->ds_nbuf) == 0) {
 398                         adf_nbuf_put_tail(ds->ds_nbuf, bf->bf_rx_status.rs_datalen);
 399                 }
 400
 401                 frame_len += bf->bf_rx_status.rs_datalen;
 402
 403                 if (bf->bf_rx_status.rs_more == 0) {
 404                         adf_nbuf_queue_t nbuf_head;
 405                         adf_nbuf_queue_init(&nbuf_head);
 406
 407                         cnt = 0;
 408
 409                         ds_tail = ds;
 410                         ds = asf_tailq_next(ds, ds_list);
 411
 412                         ds_tmp = ds_head;
 413                         ds_head = asf_tailq_next(ds_tail, ds_list);
 414
 415                         while (ds_tmp) {
 416                                 struct ath_rx_desc *ds_rmv;
 417
 418                                 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
 419                                 adf_nbuf_queue_add(&nbuf_head, ds_tmp->ds_nbuf);
 420                                 ds_tmp->ds_nbuf = ADF_NBUF_NULL;
 421
 422                                 ds_rmv = ds_tmp;
 423                                 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
 424                                 if (ds_tmp == NULL) {
 425                                         adf_os_assert(0);
 426                                 }
 427
 428                                 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
 429                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 430                                         asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
 431                                 }  else {
 432                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 433                                         asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
 434                                 }
 435
 436                                 if (ds_rmv == ds_tail) {
 437                                         break;
 438                                 }
 439                         }
 440
 441
 442                         bf->bf_rx_status.rs_datalen = frame_len;
 443                         frame_len = 0;
 444
 445                         bf->bf_skb = adf_nbuf_create_frm_frag(&nbuf_head);
 446
 447                         bf->bf_status |= ATH_BUFSTATUS_DONE;
 448
 449                         bf = asf_tailq_next(bf, bf_list);
 450                 }
 451                 else {
 452                         ds = asf_tailq_next(ds, ds_list);
 453                 }
 454         }
 455
 456 #undef PA2DESC
 457 }
 458
 459 static a_int32_t ath_startrecv(struct ath_softc_tgt *sc)
 460 {
 461         struct ath_hal *ah = sc->sc_ah;
 462         struct ath_rx_desc *ds;
 463
 464         sc->sc_rxbufsize = 1024+512+128;
 465         sc->sc_rxlink = NULL;
 466
 467         sc->sc_rxdesc_held = NULL;
 468
 469         asf_tailq_foreach(ds, &sc->sc_rxdesc, ds_list) {
 470                 a_int32_t error = ath_rxdesc_init(sc, ds);
 471                 if (error != 0) {
 472                         return error;
 473                 }
 474         }
 475
 476         ds = asf_tailq_first(&sc->sc_rxdesc);
 477         ath_hal_putrxbuf(ah, ds->ds_daddr);
 478
 479         return 0;
 480 }
 481
 482 static void ath_tgt_rx_tasklet(TQUEUE_ARG data)
 483 {
 484         struct ath_softc_tgt *sc  = (struct ath_softc_tgt *)data;
 485         struct ath_rx_buf *bf = NULL;
 486         struct ath_hal *ah = sc->sc_ah;
 487         struct rx_frame_header *rxhdr;
 488         struct ath_rx_status *rxstats;
 489         adf_nbuf_t skb = ADF_NBUF_NULL;
 490
 491         do {
 492                 bf = asf_tailq_first(&sc->sc_rxbuf);
 493                 if (bf == NULL) {
 494                         break;
 495                 }
 496
 497                 if (!(bf->bf_status & ATH_BUFSTATUS_DONE)) {
 498                         break;
 499                 }
 500
 501                 skb = bf->bf_skb;
 502                 if (skb == NULL) {
 503                         continue;
 504                 }
 505
 506                 asf_tailq_remove(&sc->sc_rxbuf, bf, bf_list);
 507
 508                 bf->bf_skb = NULL;
 509
 510                 rxhdr = (struct rx_frame_header *)adf_nbuf_push_head(skb,
 511                                                      sizeof(struct rx_frame_header));
 512                 rxstats = (struct ath_rx_status *)(&rxhdr->rx_stats[0]);
 513                 adf_os_mem_copy(rxstats, &(bf->bf_rx_status),
 514                                 sizeof(struct ath_rx_status));
 515
 516                 rxstats->rs_tstamp = ath_extend_tsf(sc, (u_int32_t)rxstats->rs_tstamp);
 517
 518                 HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb);
 519                 sc->sc_rx_stats.ast_rx_send++;
 520
 521                 bf->bf_status &= ~ATH_BUFSTATUS_DONE;
 522                 asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list);
 523
 524         } while(1);
 525
 526         sc->sc_imask |= HAL_INT_RX;
 527         ath_hal_intrset(ah, sc->sc_imask);
 528 }
 529
 530 /*******************/
 531 /* Beacon Handling */
 532 /*******************/
 533
 534 /*
 535  * Setup the beacon frame for transmit.
 536  * FIXME: Short Preamble.
 537  */
 538 static void ath_beacon_setup(struct ath_softc_tgt *sc,
 539                              struct ath_buf *bf,
 540                              struct ath_vap_target *avp)
 541 {
 542         adf_nbuf_t skb = bf->bf_skb;
 543         struct ath_hal *ah = sc->sc_ah;
 544         struct ath_desc *ds;
 545         a_int32_t flags;
 546         const HAL_RATE_TABLE *rt;
 547         a_uint8_t rix, rate;
 548         HAL_11N_RATE_SERIES series[4] = {{ 0 }};
 549
 550         flags = HAL_TXDESC_NOACK;
 551
 552         ds = bf->bf_desc;
 553         ds->ds_link = 0;
 554         ds->ds_data = bf->bf_dmamap_info.dma_segs[0].paddr;
 555
 556         rix = ath_get_minrateidx(sc, avp);
 557         rt  = sc->sc_currates;
 558         rate = rt->info[rix].rateCode;
 559
 560         ath_hal_setuptxdesc(ah, ds
 561                             , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
 562                             , sizeof(struct ieee80211_frame)
 563                             , HAL_PKT_TYPE_BEACON
 564                             , MAX_RATE_POWER
 565                             , rate, 1
 566                             , HAL_TXKEYIX_INVALID
 567                             , 0
 568                             , flags
 569                             , 0
 570                             , 0
 571                             , 0
 572                             , 0
 573                             , ATH_COMP_PROC_NO_COMP_NO_CCS);
 574
 575         ath_hal_filltxdesc(ah, ds
 576                            , asf_roundup(adf_nbuf_len(skb), 4)
 577                            , AH_TRUE
 578                            , AH_TRUE
 579                            , ds);
 580
 581         series[0].Tries = 1;
 582         series[0].Rate = rate;
 583         series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
 584         series[0].RateFlags = 0;
 585         ath_hal_set11n_ratescenario(ah, ds, 0, 0, 0, series, 4, 0);
 586 }
 587
 588 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
 589                                 adf_nbuf_t nbuf, HTC_ENDPOINT_ID EndPt)
 590 {
 591         struct ath_hal *ah = sc->sc_ah;
 592         struct ath_tx_buf *bf;
 593         a_uint8_t vap_index, *anbdata;
 594         ath_beacon_hdr_t *bhdr;
 595         struct ieee80211vap_target  *vap;
 596         a_uint32_t anblen;
 597         struct ieee80211_frame *wh;
 598
 599         if (!bc_hdr) {
 600                 adf_nbuf_peek_header(nbuf, &anbdata, &anblen);
 601                 bhdr = (ath_beacon_hdr_t *)anbdata;
 602         } else {
 603                 adf_os_print("found bc_hdr! 0x%x\n", bc_hdr);
 604         }
 605
 606         vap_index = bhdr->vap_index;
 607         adf_os_assert(vap_index < TARGET_VAP_MAX);
 608         vap = &sc->sc_vap[vap_index];
 609
 610         wh = (struct ieee80211_frame *)adf_nbuf_pull_head(nbuf,
 611                                                   sizeof(ath_beacon_hdr_t));
 612
 613         bf = sc->sc_vap[vap_index].av_bcbuf;
 614         adf_os_assert(bf);
 615         bf->bf_endpt = EndPt;
 616
 617         if (bf->bf_skb) {
 618                 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
 619                 adf_nbuf_push_head(bf->bf_skb, sizeof(ath_beacon_hdr_t));
 620                 ath_free_tx_skb(sc->tgt_htc_handle, bf->bf_endpt, bf->bf_skb);
 621         }
 622
 623         bf->bf_skb = nbuf;
 624
 625         adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, nbuf, ADF_OS_DMA_TO_DEVICE);
 626         adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info);
 627
 628         ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]);
 629         ath_hal_stoptxdma(ah, sc->sc_bhalq);
 630         ath_hal_puttxbuf(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
 631         ath_hal_txstart(ah, sc->sc_bhalq);
 632 }
 633
 634 /******/
 635 /* TX */
 636 /******/
 637
 638 static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq)
 639 {
 640         struct ath_hal *ah = sc->sc_ah;
 641
 642         (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
 643 }
 644
 645 static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq)
 646 {
 647         owltgt_tx_processq(sc, txq, OWL_TXQ_STOPPED);
 648 }
 649
 650 static void ath_tx_draintxq(struct ath_softc_tgt *sc, struct ath_txq *txq)
 651 {
 652         owltgt_txq_drain(sc, txq);
 653 }
 654
 655 static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq)
 656 {
 657         struct ath_hal *ah = sc->sc_ah;
 658         a_uint16_t i;
 659         struct ath_txq *txq = NULL;
 660         struct ath_atx_tid *tid = NULL;
 661
 662         ath_tx_status_clear(sc);
 663         sc->sc_tx_draining = 1;
 664
 665         (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
 666
 667         for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
 668                 if (ATH_TXQ_SETUP(sc, i))
 669                         ath_tx_stopdma(sc, ATH_TXQ(sc, i));
 670
 671         for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
 672                 if (ATH_TXQ_SETUP(sc, i)) {
 673                         owltgt_tx_processq(sc, ATH_TXQ(sc,i), OWL_TXQ_STOPPED);
 674
 675                         txq = ATH_TXQ(sc,i);
 676                         while (!asf_tailq_empty(&txq->axq_tidq)){
 677                                 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
 678                                 if(tid == NULL)
 679                                         break;
 680                                 tid->sched = AH_FALSE;
 681                                 ath_tgt_tid_drain(sc,tid);
 682                         }
 683                 }
 684
 685         sc->sc_tx_draining = 0;
 686 }
 687
 688 static void ath_tgt_txq_setup(struct ath_softc_tgt *sc)
 689 {
 690         a_int32_t qnum;
 691         struct ath_txq *txq;
 692
 693         sc->sc_txqsetup=0;
 694
 695         for (qnum=0;qnum<HAL_NUM_TX_QUEUES;qnum++) {
 696                 txq= &sc->sc_txq[qnum];
 697                 txq->axq_qnum = qnum;
 698                 txq->axq_link = NULL;
 699                 asf_tailq_init(&txq->axq_q);
 700                 txq->axq_depth = 0;
 701                 txq->axq_linkbuf = NULL;
 702                 asf_tailq_init(&txq->axq_tidq);
 703                 sc->sc_txqsetup |= 1<<qnum;
 704         }
 705
 706         sc->sc_uapsdq  = &sc->sc_txq[UAPSDQ_NUM];
 707         sc->sc_cabq    = &sc->sc_txq[CABQ_NUM];
 708
 709         sc->sc_ac2q[WME_AC_BE]  = &sc->sc_txq[0];
 710         sc->sc_ac2q[WME_AC_BK]  = &sc->sc_txq[1];
 711         sc->sc_ac2q[WME_AC_VI]  = &sc->sc_txq[2];
 712         sc->sc_ac2q[WME_AC_VO]  = &sc->sc_txq[3];
 713
 714         return;
 715 #undef N
 716 }
 717
 718 static void tgt_HTCRecv_beaconhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 719                                       adf_nbuf_t buf, void *ServiceCtx)
 720 {
 721         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 722
 723         ath_tgt_send_beacon(sc, hdr_buf, buf, EndPt);
 724 }
 725
 726 static void tgt_HTCRecv_uapsdhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 727                                      adf_nbuf_t buf, void *ServiceCtx)
 728 {
 729 }
 730
 731 static void tgt_HTCRecv_mgmthandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 732                                     adf_nbuf_t buf, void *ServiceCtx)
 733 {
 734         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 735
 736         ath_tgt_send_mgt(sc,hdr_buf,buf,EndPt);
 737 }
 738
 739 static void tgt_HTCRecvMessageHandler(HTC_ENDPOINT_ID EndPt,
 740                                       adf_nbuf_t hdr_buf, adf_nbuf_t buf,
 741                                       void *ServiceCtx)
 742 {
 743         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 744         struct ath_tx_buf *bf;
 745         a_uint8_t *data;
 746         a_uint32_t len;
 747         ath_data_hdr_t *dh;
 748         struct ath_node_target *an;
 749         struct ath_atx_tid *tid;
 750
 751         if (!hdr_buf) {
 752                 adf_nbuf_peek_header(buf, &data, &len);
 753                 adf_nbuf_pull_head(buf, sizeof(ath_data_hdr_t));
 754         } else {
 755                 adf_nbuf_peek_header(hdr_buf, &data, &len);
 756         }
 757
 758         adf_os_assert(len >= sizeof(ath_data_hdr_t));
 759         dh = (ath_data_hdr_t *)data;
 760
 761         an = &sc->sc_sta[dh->ni_index];
 762         tid = ATH_AN_2_TID(an, dh->tidno);
 763
 764         sc->sc_tx_stats.tx_tgt++;
 765
 766         bf = ath_tgt_tx_prepare(sc, buf, dh);
 767         if (!bf) {
 768                 ath_free_tx_skb(sc->tgt_htc_handle,EndPt,buf);
 769                 return;
 770         }
 771
 772         bf->bf_endpt = EndPt;
 773         bf->bf_cookie = dh->cookie;
 774
 775         if (tid->flag & TID_AGGR_ENABLED)
 776                 ath_tgt_handle_aggr(sc, bf);
 777         else
 778                 ath_tgt_handle_normal(sc, bf);
 779 }
 780
 781 static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 782                                    adf_nbuf_t buf, void *ServiceCtx)
 783 {
 784         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 785         struct ath_hal *ah = sc->sc_ah;
 786         a_uint64_t tsf;
 787         a_uint32_t tmp;
 788
 789 #ifdef ATH_ENABLE_CABQ
 790         tsf = ath_hal_gettsf64(ah);
 791         tmp = tsf - sc->sc_swba_tsf;
 792
 793         if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
 794                 HTC_ReturnBuffers(sc->tgt_htc_handle, EndPt, buf);
 795                 return;
 796         }
 797
 798         tgt_HTCRecvMessageHandler(EndPt, hdr_buf, buf, ServiceCtx);
 799 #endif
 800 }
 801
 802 /***********************/
 803 /* Descriptor Handling */
 804 /***********************/
 805
 806 static a_int32_t ath_descdma_setup(struct ath_softc_tgt *sc,
 807                                    struct ath_descdma *dd, ath_bufhead *head,
 808                                    const char *name, a_int32_t nbuf, a_int32_t ndesc,
 809                                    a_uint32_t bfSize, a_uint32_t descSize)
 810 {
 811 #define DS2PHYS(_dd, _ds)                                               \
 812         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 813
 814         struct ath_desc *ds;
 815         struct ath_buf *bf;
 816         a_int32_t i, bsize, error;
 817         a_uint8_t *bf_addr;
 818         a_uint8_t *ds_addr;
 819
 820         dd->dd_name = name;
 821         dd->dd_desc_len = descSize * nbuf * ndesc;
 822
 823         dd->dd_desc = adf_os_dmamem_alloc(sc->sc_dev,
 824                                   dd->dd_desc_len, 1, &dd->dd_desc_dmamap);
 825         dd->dd_desc_paddr = adf_os_dmamem_map2addr(dd->dd_desc_dmamap);
 826         if (dd->dd_desc == NULL) {
 827                 error = -ENOMEM;
 828                 goto fail;
 829         }
 830         ds = dd->dd_desc;
 831
 832         bsize = bfSize * nbuf;
 833         bf = adf_os_mem_alloc(bsize);
 834         if (bf == NULL) {
 835                 error = -ENOMEM;
 836                 goto fail2;
 837         }
 838         adf_os_mem_set(bf, 0, bsize);
 839         dd->dd_bufptr = bf;
 840
 841         bf_addr = (a_uint8_t *)bf;
 842         ds_addr = (a_uint8_t *)ds;
 843
 844         asf_tailq_init(head);
 845
 846         for (i = 0; i < nbuf; i++) {
 847                 a_int32_t j;
 848
 849                 if (adf_nbuf_dmamap_create( sc->sc_dev, &bf->bf_dmamap) != A_STATUS_OK) {
 850                         goto fail2;
 851                 }
 852
 853                 bf->bf_desc = bf->bf_descarr = bf->bf_lastds = ds;
 854                 for (j = 0; j < ndesc; j++)
 855                         ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, j, (ds_addr + (j*descSize)));
 856
 857                 ATH_BUF_SET_DESC_PHY_ADDR(bf, ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, 0));
 858
 859                 adf_nbuf_queue_init(&bf->bf_skbhead);
 860                 asf_tailq_insert_tail(head, bf, bf_list);
 861
 862                 bf_addr += bfSize;
 863                 ds_addr += (ndesc * descSize);
 864                 bf = (struct ath_buf *)bf_addr;
 865                 ds = (struct ath_desc *)ds_addr;
 866         }
 867
 868         return 0;
 869 fail2:
 870         adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
 871                            1, dd->dd_desc, dd->dd_desc_dmamap);
 872 fail:
 873         adf_os_mem_set(dd, 0, sizeof(*dd));
 874         adf_os_assert(0);
 875         return error;
 876
 877 #undef DS2PHYS
 878 }
 879
 880 static void ath_descdma_cleanup(struct ath_softc_tgt *sc,
 881                                 struct ath_descdma *dd,
 882                                 ath_bufhead *head, a_int32_t dir)
 883 {
 884         struct ath_tx_buf *bf;
 885         struct ieee80211_node *ni;
 886
 887         asf_tailq_foreach(bf, head, bf_list) {
 888                 if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
 889                         adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, dir);
 890                         while(adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
 891                                 ath_free_rx_skb(sc,
 892                                         adf_nbuf_queue_remove(&bf->bf_skbhead));
 893                         }
 894                         bf->bf_skb = NULL;
 895                 } else if (bf->bf_skb != NULL) {
 896                         adf_nbuf_unmap(sc->sc_dev,bf->bf_dmamap, dir);
 897                         ath_free_rx_skb(sc, bf->bf_skb);
 898                         bf->bf_skb = NULL;
 899                 }
 900
 901                 adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap);
 902
 903                 ni = bf->bf_node;
 904                 bf->bf_node = NULL;
 905         }
 906
 907         adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
 908                            1, dd->dd_desc, dd->dd_desc_dmamap);
 909
 910         asf_tailq_init(head);
 911         adf_os_mem_free(dd->dd_bufptr);
 912         adf_os_mem_set(dd, 0, sizeof(*dd));
 913 }
 914
 915 static a_int32_t ath_desc_alloc(struct ath_softc_tgt *sc)
 916 {
 917 #define DS2PHYS(_dd, _ds)                                               \
 918         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 919
 920         a_int32_t error;
 921         struct ath_tx_buf *bf;
 922
 923         if(ath_numrxbufs == -1)
 924                 ath_numrxbufs = ATH_RXBUF;
 925
 926         if (ath_numrxdescs == -1)
 927                 ath_numrxdescs = ATH_RXDESC;
 928
 929         error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
 930                                   "rx", ath_numrxdescs, 1,
 931                                   sizeof(struct ath_rx_buf),
 932                                   sizeof(struct ath_rx_desc));
 933         if (error != 0)
 934                 return error;
 935
 936         a_uint32_t i;
 937         struct ath_descdma *dd = &sc->sc_rxdma;
 938         struct ath_rx_desc *ds = dd->dd_desc;
 939         struct ath_rx_desc *ds_prev = NULL;
 940
 941         asf_tailq_init(&sc->sc_rxdesc);
 942         asf_tailq_init(&sc->sc_rxdesc_idle);
 943
 944         for (i = 0; i < ath_numrxdescs; i++, ds++) {
 945
 946                 if (ds->ds_nbuf != ADF_NBUF_NULL) {
 947                         ds->ds_nbuf = ADF_NBUF_NULL;
 948                 }
 949
 950                 if (adf_nbuf_dmamap_create(sc->sc_dev, &ds->ds_dmap) != A_STATUS_OK) {
 951                         adf_os_assert(0);
 952                 }
 953
 954                 ds->ds_daddr = DS2PHYS(&sc->sc_rxdma, ds);
 955
 956                 if (ds_prev) {
 957                         ds_prev->ds_link = ds->ds_daddr;
 958                 }
 959
 960                 ds->ds_link = 0;
 961                 ds_prev = ds;
 962
 963                 asf_tailq_insert_tail(&sc->sc_rxdesc, ds, ds_list);
 964         }
 965
 966         error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
 967                                   "tx", ATH_TXBUF + 1, ATH_TXDESC,
 968                                   sizeof(struct ath_tx_buf),
 969                                   sizeof(struct ath_tx_desc));
 970         if (error != 0) {
 971                 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
 972                                     ADF_OS_DMA_FROM_DEVICE);
 973                 return error;
 974         }
 975
 976         error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
 977                                   "beacon", ATH_BCBUF, 1,
 978                                   sizeof(struct ath_tx_buf),
 979                                   sizeof(struct ath_tx_desc));
 980         if (error != 0) {
 981                 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf,
 982                                     ADF_OS_DMA_TO_DEVICE);
 983                 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
 984                                     ADF_OS_DMA_FROM_DEVICE);
 985                 return error;
 986         }
 987
 988         bf = asf_tailq_first(&sc->sc_txbuf);
 989         bf->bf_isaggr = bf->bf_isretried = bf->bf_retries = 0;
 990         asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
 991
 992         sc->sc_txbuf_held = bf;
 993
 994         return 0;
 995
 996 #undef DS2PHYS
 997 }
 998
 999 static void ath_desc_free(struct ath_softc_tgt *sc)
1000 {
1001         asf_tailq_insert_tail(&sc->sc_txbuf, sc->sc_txbuf_held, bf_list);
1002
1003         sc->sc_txbuf_held = NULL;
1004
1005         if (sc->sc_txdma.dd_desc_len != 0)
1006                 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf,
1007                                     ADF_OS_DMA_TO_DEVICE);
1008         if (sc->sc_rxdma.dd_desc_len != 0)
1009                 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
1010                                     ADF_OS_DMA_FROM_DEVICE);
1011 }
1012
1013 /**********************/
1014 /* Interrupt Handling */
1015 /**********************/
1016
1017 adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl)
1018 {
1019         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl;
1020         struct ath_hal *ah = sc->sc_ah;
1021         HAL_INT status;
1022
1023         if (sc->sc_invalid)
1024                 return ADF_OS_IRQ_NONE;
1025
1026         if (!ath_hal_intrpend(ah))
1027                 return ADF_OS_IRQ_NONE;
1028
1029         ath_hal_getisr(ah, &status);
1030
1031         status &= sc->sc_imask;
1032
1033         if (status & HAL_INT_FATAL) {
1034                 ath_hal_intrset(ah, 0);
1035                 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
1036         } else {
1037                 if (status & HAL_INT_SWBA) {
1038                         WMI_SWBA_EVENT swbaEvt;
1039                         struct ath_txq *txq = ATH_TXQ(sc, 8);
1040
1041                         swbaEvt.tsf = ath_hal_gettsf64(ah);
1042                         swbaEvt.beaconPendingCount = ath_hal_numtxpending(ah, sc->sc_bhalq);
1043                         sc->sc_swba_tsf = ath_hal_gettsf64(ah);
1044
1045                         wmi_event(sc->tgt_wmi_handle,
1046                                   WMI_SWBA_EVENTID,
1047                                   &swbaEvt,
1048                                   sizeof(WMI_SWBA_EVENT));
1049
1050                         ath_tx_draintxq(sc, txq);
1051                 }
1052
1053                 if (status & HAL_INT_RXORN)
1054                         sc->sc_int_stats.ast_rxorn++;
1055
1056                 if (status & HAL_INT_RXEOL)
1057                         sc->sc_int_stats.ast_rxeol++;
1058
1059                 if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
1060                         if (status & HAL_INT_RX)
1061                                 sc->sc_int_stats.ast_rx++;
1062
1063                         ath_uapsd_processtriggers(sc);
1064
1065                         sc->sc_imask &= ~HAL_INT_RX;
1066                         ath_hal_intrset(ah, sc->sc_imask);
1067
1068                         ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
1069                 }
1070
1071                 if (status & HAL_INT_TXURN) {
1072                         sc->sc_int_stats.ast_txurn++;
1073                         ath_hal_updatetxtriglevel(ah, AH_TRUE);
1074                 }
1075
1076                 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq);
1077
1078                 if (status & HAL_INT_BMISS) {
1079                         ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_bmisstq);
1080                 }
1081
1082                 if (status & HAL_INT_GTT)
1083                         sc->sc_int_stats.ast_txto++;
1084
1085                 if (status & HAL_INT_CST)
1086                         sc->sc_int_stats.ast_cst++;
1087         }
1088
1089         return ADF_OS_IRQ_HANDLED;
1090 }
1091
1092 static void ath_fatal_tasklet(TQUEUE_ARG data )
1093 {
1094         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1095
1096         wmi_event(sc->tgt_wmi_handle, WMI_FATAL_EVENTID, NULL, 0);
1097 }
1098
1099 static void ath_bmiss_tasklet(TQUEUE_ARG data)
1100 {
1101         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1102
1103         wmi_event(sc->tgt_wmi_handle, WMI_BMISS_EVENTID, NULL, 0);
1104 }
1105
1106 /****************/
1107 /* WMI Commands */
1108 /****************/
1109
1110 static void ath_enable_intr_tgt(void *Context, A_UINT16 Command,
1111                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1112 {
1113         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1114         struct ath_hal *ah = sc->sc_ah;
1115         a_uint32_t intr;
1116
1117         if (data)
1118                 intr = (*(a_uint32_t *)data);
1119
1120         intr = adf_os_ntohl(intr);
1121
1122         if (intr & HAL_INT_SWBA) {
1123                 sc->sc_imask |= HAL_INT_SWBA;
1124         } else {
1125                 sc->sc_imask &= ~HAL_INT_SWBA;
1126         }
1127
1128         if (intr & HAL_INT_BMISS) {
1129                 sc->sc_imask |= HAL_INT_BMISS;
1130         }
1131
1132         ath_hal_intrset(ah, sc->sc_imask);
1133         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1134 }
1135
1136 static void ath_init_tgt(void *Context, A_UINT16 Command,
1137                          A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1138 {
1139         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1140         struct ath_hal *ah = sc->sc_ah;
1141         a_uint32_t stbcsupport;
1142
1143         sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1144                 | HAL_INT_RXEOL | HAL_INT_RXORN
1145                 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1146
1147         sc->sc_imask |= HAL_INT_GTT;
1148
1149         if (ath_hal_htsupported(ah))
1150                 sc->sc_imask |= HAL_INT_CST;
1151
1152 #ifdef MAGPIE_MERLIN
1153         if (ath_hal_txstbcsupport(ah, &stbcsupport))
1154                 sc->sc_txstbcsupport = stbcsupport;
1155
1156         if (ath_hal_rxstbcsupport(ah, &stbcsupport))
1157                 sc->sc_rxstbcsupport = stbcsupport;
1158 #endif
1159         adf_os_setup_intr(sc->sc_dev, ath_intr);
1160         ath_hal_intrset(ah, sc->sc_imask);
1161
1162         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1163 }
1164
1165 static void ath_int_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1166                               A_UINT8 *data, a_int32_t datalen)
1167 {
1168         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1169
1170         struct fusion_stats {
1171                 a_uint32_t ast_rx;
1172                 a_uint32_t ast_rxorn;
1173                 a_uint32_t ast_rxeol;
1174                 a_uint32_t ast_txurn;
1175                 a_uint32_t ast_txto;
1176                 a_uint32_t ast_cst;
1177         };
1178
1179         struct fusion_stats stats;
1180
1181         stats.ast_rx = sc->sc_int_stats.ast_rx;
1182         stats.ast_rxorn = sc->sc_int_stats.ast_rxorn;
1183         stats.ast_rxeol = sc->sc_int_stats.ast_rxeol;
1184         stats.ast_txurn = sc->sc_int_stats.ast_txurn;
1185         stats.ast_txto = sc->sc_int_stats.ast_txto;
1186         stats.ast_cst = sc->sc_int_stats.ast_cst;
1187
1188         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1189 }
1190
1191 static void ath_tx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1192                              A_UINT8 *data, a_int32_t datalen)
1193 {
1194         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1195
1196         struct fusion_stats {
1197                 a_uint32_t   ast_tx_xretries;
1198                 a_uint32_t   ast_tx_fifoerr;
1199                 a_uint32_t   ast_tx_filtered;
1200                 a_uint32_t   ast_tx_timer_exp;
1201                 a_uint32_t   ast_tx_shortretry;
1202                 a_uint32_t   ast_tx_longretry;
1203
1204                 a_uint32_t   tx_qnull;
1205                 a_uint32_t   tx_noskbs;
1206                 a_uint32_t   tx_nobufs;
1207         };
1208
1209         struct fusion_stats stats;
1210
1211         stats.ast_tx_xretries = sc->sc_tx_stats.ast_tx_xretries;
1212         stats.ast_tx_fifoerr = sc->sc_tx_stats.ast_tx_fifoerr;
1213         stats.ast_tx_filtered = sc->sc_tx_stats.ast_tx_filtered;
1214         stats.ast_tx_timer_exp = sc->sc_tx_stats.ast_tx_timer_exp;
1215         stats.ast_tx_shortretry = sc->sc_tx_stats.ast_tx_shortretry;
1216         stats.ast_tx_longretry = sc->sc_tx_stats.ast_tx_longretry;
1217         stats.tx_qnull = sc->sc_tx_stats.tx_qnull;
1218         stats.tx_noskbs = sc->sc_tx_stats.tx_noskbs;
1219         stats.tx_nobufs = sc->sc_tx_stats.tx_nobufs;
1220
1221         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1222 }
1223
1224 static void ath_rx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1225                              A_UINT8 *data, a_int32_t datalen)
1226 {
1227         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1228
1229         struct fusion_stats {
1230                 a_uint32_t   ast_rx_nobuf;
1231                 a_uint32_t   ast_rx_send;
1232                 a_uint32_t   ast_rx_done;
1233         };
1234
1235         struct fusion_stats stats;
1236
1237         stats.ast_rx_nobuf = sc->sc_rx_stats.ast_rx_nobuf;
1238         stats.ast_rx_send = sc->sc_rx_stats.ast_rx_send;
1239         stats.ast_rx_done = sc->sc_rx_stats.ast_rx_done;
1240
1241         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1242 }
1243
1244 static void ath_get_tgt_version(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1245                                 A_UINT8 *data, a_int32_t datalen)
1246 {
1247         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1248         struct wmi_fw_version ver;
1249
1250         ver.major = ATH_VERSION_MAJOR;
1251         ver.minor = ATH_VERSION_MINOR;
1252
1253         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &ver, sizeof(ver));
1254 }
1255
1256 static void ath_enable_aggr_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1257                                 A_UINT8 *data, a_int32_t datalen)
1258 {
1259         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1260         struct ath_aggr_info *aggr = (struct ath_aggr_info *)data;
1261         a_uint8_t nodeindex = aggr->nodeindex;
1262         a_uint8_t tidno = aggr->tidno;
1263         struct ath_node_target *an = NULL ;
1264         struct ath_atx_tid  *tid = NULL;
1265
1266         if (nodeindex >= TARGET_NODE_MAX) {
1267                 goto done;
1268         }
1269
1270         an = &sc->sc_sta[nodeindex];
1271         if (!an->an_valid) {
1272                 goto done;
1273         }
1274
1275         if (tidno >= WME_NUM_TID) {
1276                 adf_os_print("[%s] enable_aggr with invalid tid %d(node = %d)\n",
1277                              __FUNCTION__, tidno, nodeindex);
1278                 goto done;
1279         }
1280
1281         tid = ATH_AN_2_TID(an, tidno);
1282
1283         if (aggr->aggr_enable) {
1284                 tid->flag |= TID_AGGR_ENABLED;
1285         } else if ( tid->flag & TID_AGGR_ENABLED ) {
1286                 tid->flag &= ~TID_AGGR_ENABLED;
1287                 ath_tgt_tx_cleanup(sc, an, tid, 1);
1288         }
1289 done:
1290         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1291 }
1292
1293 static void ath_ic_update_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1294                               A_UINT8 *data, a_int32_t datalen)
1295 {
1296         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1297         struct ieee80211com_target *ic = (struct ieee80211com_target * )data;
1298         struct ieee80211com_target *ictgt = &sc->sc_ic ;
1299
1300         adf_os_mem_copy(ictgt, ic, sizeof(struct  ieee80211com_target));
1301
1302         ictgt->ic_ampdu_limit         = adf_os_ntohl(ic->ic_ampdu_limit);
1303
1304         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1305 }
1306
1307 static void ath_vap_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1308                                A_UINT8 *data, a_int32_t datalen)
1309 {
1310         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1311         struct ieee80211vap_target *vap;
1312         a_uint8_t vap_index;
1313
1314         vap = (struct ieee80211vap_target *)data;
1315
1316         vap->iv_rtsthreshold    = adf_os_ntohs(vap->iv_rtsthreshold);
1317         vap->iv_opmode          = adf_os_ntohl(vap->iv_opmode);
1318
1319         vap_index = vap->iv_vapindex;
1320
1321         adf_os_assert(sc->sc_vap[vap_index].av_valid == 0);
1322
1323         adf_os_mem_copy(&(sc->sc_vap[vap_index].av_vap), vap,
1324                         VAP_TARGET_SIZE);
1325
1326         sc->sc_vap[vap_index].av_bcbuf = asf_tailq_first(&(sc->sc_bbuf));
1327         sc->sc_vap[vap_index].av_valid = 1;
1328
1329         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1330 }
1331
1332 static void ath_node_create_tgt(void *Context, A_UINT16 Command,
1333                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1334 {
1335         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1336         struct ieee80211_node_target *node;
1337         a_uint8_t vap_index;
1338         a_uint8_t node_index;
1339
1340         node = (struct ieee80211_node_target *)data;
1341
1342         node_index = node->ni_nodeindex;
1343
1344         node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1345         node->ni_flags = adf_os_ntohs(node->ni_flags);
1346         node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1347
1348         adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1349                         NODE_TARGET_SIZE);
1350
1351         vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1352         sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1353         if(sc->sc_sta[node_index].ni.ni_is_vapnode == 1)
1354                 sc->sc_vap[vap_index].av_vap.iv_nodeindex = node_index;
1355
1356         sc->sc_sta[node_index].an_valid = 1;
1357         sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1358         sc->sc_sta[node_index].ni.ni_iv16 = 0;
1359         sc->sc_sta[node_index].ni.ni_iv32 = 0;
1360
1361         owl_tgt_node_init(&sc->sc_sta[node_index]);
1362
1363         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1364 }
1365
1366 static void ath_node_cleanup_tgt(void *Context, A_UINT16 Command,
1367                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1368 {
1369         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1370         a_uint8_t node_index;
1371         a_uint8_t *nodedata;
1372
1373         nodedata = (a_uint8_t *)data;
1374         node_index = *nodedata;
1375         sc->sc_sta[node_index].an_valid = 0;
1376
1377         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1378 }
1379
1380 static void ath_node_update_tgt(void *Context, A_UINT16 Command,
1381                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1382 {
1383         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1384         struct ieee80211_node_target *node;
1385         a_uint8_t vap_index;
1386         a_uint8_t node_index;
1387
1388         node = (struct ieee80211_node_target *)data;
1389
1390         node_index = node->ni_nodeindex;
1391
1392         node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1393         node->ni_flags = adf_os_ntohs(node->ni_flags);
1394         node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1395
1396         adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1397                         NODE_TARGET_SIZE);
1398
1399         vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1400         sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1401
1402         sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1403         sc->sc_sta[node_index].ni.ni_iv16 = 0;
1404         sc->sc_sta[node_index].ni.ni_iv32 = 0;
1405
1406         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1407 }
1408
1409 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
1410                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1411 {
1412         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1413         struct ath_hal *ah = sc->sc_ah;
1414         a_uint32_t addr;
1415         a_uint32_t val[32];
1416         int i;
1417
1418         for (i = 0; i < datalen; i += sizeof(a_int32_t)) {
1419                 addr = *(a_uint32_t *)(data + i);
1420                 addr = adf_os_ntohl(addr);
1421
1422                 if ((addr & 0xffffe000) == 0x2000) {
1423                         /* SEEPROM */
1424                         ath_hal_reg_read_target(ah, addr);
1425                         if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) {
1426                                 adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
1427                         }
1428                         val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
1429                 } else if (addr > 0xffff) {
1430                         val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr;
1431                 } else
1432                         val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr);
1433
1434                 val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]);
1435         }
1436
1437         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
1438 }
1439
1440 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
1441                                   A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1442 {
1443         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1444         struct ath_hal *ah = sc->sc_ah;
1445         int i;
1446         struct registerWrite {
1447                 a_uint32_t reg;
1448                 a_uint32_t val;
1449         }*t;
1450
1451         for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
1452                 t = (struct registerWrite *)(data+i);
1453
1454                 if( t->reg > 0xffff ) {
1455                         a_uint32_t *pReg = (a_uint32_t *)t->reg;
1456
1457                         *pReg = t->val;
1458
1459 #if defined(PROJECT_K2)
1460                         if( t->reg == 0x50040 ) {
1461                                 static uint8_t flg=0;
1462
1463                                 if( flg == 0 ) {
1464                                         A_CLOCK_INIT(117);
1465                                         A_UART_HWINIT(117*1000*1000, 19200);
1466                                         flg = 1;
1467                                 }
1468                         }
1469 #endif
1470                 } else {
1471 #if defined(PROJECT_K2)
1472                         if( t->reg == 0x7014 ) {
1473                                 static uint8_t resetPLL = 0;
1474                                 a_uint32_t *pReg;
1475
1476                                 if( resetPLL == 0 ) {
1477                                         t->reg = 0x50044;
1478                                         pReg = (a_uint32_t *)t->reg;
1479                                         *pReg = 0;
1480                                         ath_hal_reg_write_target(ah, 0x786c,
1481                                                  ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
1482                                         ath_hal_reg_write_target(ah, 0x786c,
1483                                                  ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
1484                                         *pReg = 0x20;
1485                                         resetPLL = 1;
1486                                 }
1487                                 t->reg = 0x7014;
1488                         }
1489 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
1490                         if( t->reg == 0x7014 ){
1491                                 static uint8_t resetPLL = 0;
1492
1493                                 if( resetPLL == 0 ) {
1494                                         ath_hal_reg_write_target(ah, 0x7890,
1495                                                  ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
1496                                         ath_hal_reg_write_target(ah, 0x7890,
1497                                                  ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
1498                                         resetPLL = 1;
1499                                 }
1500                         }
1501 #endif
1502                         ath_hal_reg_write_target(ah,t->reg,t->val);
1503                 }
1504         }
1505
1506         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1507 }
1508
1509 static void ath_vap_delete_tgt(void *Context, A_UINT16 Command,
1510                                A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1511 {
1512         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1513         a_uint8_t vap_index;
1514
1515         vap_index = *(a_uint8_t *)data;
1516
1517         sc->sc_vap[vap_index].av_valid = 0;
1518         sc->sc_vap[vap_index].av_bcbuf = NULL;
1519         ath_node_vdelete_tgt(sc, vap_index);
1520         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1521 }
1522
1523 static void ath_disable_intr_tgt(void *Context, A_UINT16 Command,
1524                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1525 {
1526         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1527         struct ath_hal *ah = sc->sc_ah;
1528
1529         ath_hal_intrset(ah, 0);
1530         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1531 }
1532
1533 static void ath_flushrecv_tgt(void *Context, A_UINT16 Command,
1534                               A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1535 {
1536         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1537         struct ath_buf *bf;
1538
1539         asf_tailq_foreach(bf, &sc->sc_rxbuf, bf_list)
1540                 if (bf->bf_skb != NULL) {
1541                         adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap,
1542                                        ADF_OS_DMA_FROM_DEVICE);
1543                         ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead));
1544                         bf->bf_skb = NULL;
1545                 }
1546
1547         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1548 }
1549
1550 static void ath_tx_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1551                                 A_UINT8 *data, a_int32_t datalen)
1552 {
1553         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1554         a_uint32_t q = *(a_uint32_t *)data;
1555         struct ath_txq *txq = NULL;
1556
1557         q = adf_os_ntohl(q);
1558         txq = ATH_TXQ(sc, q);
1559
1560         ath_tx_draintxq(sc, txq);
1561         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1562 }
1563
1564 static void ath_draintxq_tgt(void *Context, A_UINT16 Command,
1565                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1566 {
1567         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1568         HAL_BOOL b = (HAL_BOOL) *(a_int32_t *)data;
1569
1570         ath_draintxq(Context, b);
1571         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1572 }
1573
1574 static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command,
1575                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1576 {
1577         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1578
1579         ath_hal_aborttxdma(sc->sc_ah);
1580         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1581 }
1582
1583 static void ath_aborttxq_tgt(void *Context, A_UINT16 Command,
1584                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1585 {
1586
1587         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1588         a_uint16_t i;
1589
1590         for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
1591                 if (ATH_TXQ_SETUP(sc, i))
1592                         ath_tx_draintxq(sc, ATH_TXQ(sc,i));
1593         }
1594
1595         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1596 }
1597
1598 static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command,
1599                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1600 {
1601         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1602         struct ath_hal *ah = sc->sc_ah;
1603         a_uint32_t q;
1604
1605         if (data)
1606                 q = *(a_uint32_t *)data;
1607
1608         q = adf_os_ntohl(q);
1609         ath_hal_stoptxdma(ah, q);
1610         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1611 }
1612
1613 static void ath_startrecv_tgt(void *Context, A_UINT16 Command,
1614                               A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1615 {
1616
1617         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1618
1619         ath_startrecv(sc);
1620         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1621 }
1622
1623 static void ath_stoprecv_tgt(void *Context, A_UINT16 Command,
1624                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1625 {
1626         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1627         struct ath_hal *ah = sc->sc_ah;
1628
1629         ath_hal_stoppcurecv(ah);
1630         ath_hal_setrxfilter(ah, 0);
1631         ath_hal_stopdmarecv(ah);
1632
1633         sc->sc_rxlink = NULL;
1634         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1635 }
1636
1637 static void ath_setcurmode_tgt(void *Context, A_UINT16 Command,
1638                                A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1639 {
1640         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1641         a_uint16_t mode;
1642
1643         mode= *((a_uint16_t *)data);
1644         mode = adf_os_ntohs(mode);
1645
1646         ath_setcurmode(sc, mode);
1647
1648         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1649 }
1650
1651 static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1652                                  A_UINT8 *data, a_int32_t datalen)
1653 {
1654         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1655         struct ath_hal *ah = sc->sc_ah;
1656
1657         ath_desc_free(sc);
1658         ath_hal_detach(ah);
1659         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1660         adf_os_mem_free(sc);
1661 }
1662
1663 static void handle_echo_command(void *pContext, A_UINT16 Command,
1664                                 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1665 {
1666         wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length);
1667 }
1668
1669 static void handle_rc_state_change_cmd(void *Context, A_UINT16 Command,
1670                                        A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1671
1672 {
1673         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1674         struct wmi_rc_state_change_cmd *wmi_data = (struct wmi_rc_state_change_cmd *)buffer;
1675
1676         a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1677
1678         ath_rate_newstate(sc, &sc->sc_vap[wmi_data->vap_index].av_vap,
1679                           wmi_data->vap_state,
1680                           capflag,
1681                           &wmi_data->rs);
1682
1683         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1684 }
1685
1686 static void handle_rc_rate_update_cmd(void *Context, A_UINT16 Command,
1687                                       A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1688 {
1689         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1690         struct wmi_rc_rate_update_cmd *wmi_data = (struct wmi_rc_rate_update_cmd *)buffer;
1691
1692         a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1693
1694         ath_rate_node_update(sc, &sc->sc_sta[wmi_data->node_index],
1695                              wmi_data->isNew,
1696                              capflag,
1697                              &wmi_data->rs);
1698
1699         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1700 }
1701
1702 static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command,
1703                                      A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1704 {
1705         adf_os_assert(0);
1706 }
1707
1708 static void ath_rc_mask_tgt(void *Context, A_UINT16 Command,
1709                             A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1710 {
1711         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1712         struct wmi_rc_rate_mask_cmd *wmi_data = (struct wmi_rc_rate_mask_cmd *)buffer;
1713         int idx, band, i;
1714
1715         idx = wmi_data->vap_index;
1716         band = wmi_data->band;
1717
1718         sc->sc_vap[idx].av_rate_mask[band] = adf_os_ntohl(wmi_data->mask);
1719
1720         if (sc->sc_vap[idx].av_rate_mask[band]) {
1721                 for (i = 0; i < RATE_TABLE_SIZE; i++) {
1722                         if ((1 << i) & sc->sc_vap[idx].av_rate_mask[band]) {
1723                                 sc->sc_vap[idx].av_minrateidx[band] = i;
1724                                 break;
1725                         }
1726                 }
1727         } else {
1728                 sc->sc_vap[idx].av_minrateidx[band] = 0;
1729         }
1730
1731         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1732 }
1733
1734 static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] =
1735 {
1736         {handle_echo_command,         WMI_ECHO_CMDID,               0},
1737         {dispatch_magpie_sys_cmds,    WMI_ACCESS_MEMORY_CMDID,      0},
1738         {ath_get_tgt_version,         WMI_GET_FW_VERSION,           0},
1739         {ath_disable_intr_tgt,        WMI_DISABLE_INTR_CMDID,       0},
1740         {ath_enable_intr_tgt,         WMI_ENABLE_INTR_CMDID,        0},
1741         {ath_init_tgt,                WMI_ATH_INIT_CMDID,           0},
1742         {ath_aborttxq_tgt,            WMI_ABORT_TXQ_CMDID,          0},
1743         {ath_stop_tx_dma_tgt,         WMI_STOP_TX_DMA_CMDID,        0},
1744         {ath_aborttx_dma_tgt,         WMI_ABORT_TX_DMA_CMDID,       0},
1745         {ath_tx_draintxq_tgt,         WMI_DRAIN_TXQ_CMDID,          0},
1746         {ath_draintxq_tgt,            WMI_DRAIN_TXQ_ALL_CMDID,      0},
1747         {ath_startrecv_tgt,           WMI_START_RECV_CMDID,         0},
1748         {ath_stoprecv_tgt,            WMI_STOP_RECV_CMDID,          0},
1749         {ath_flushrecv_tgt,           WMI_FLUSH_RECV_CMDID,         0},
1750         {ath_setcurmode_tgt,          WMI_SET_MODE_CMDID,           0},
1751         {ath_node_create_tgt,         WMI_NODE_CREATE_CMDID,        0},
1752         {ath_node_cleanup_tgt,        WMI_NODE_REMOVE_CMDID,        0},
1753         {ath_vap_delete_tgt,          WMI_VAP_REMOVE_CMDID,         0},
1754         {ath_vap_create_tgt,          WMI_VAP_CREATE_CMDID,         0},
1755         {ath_hal_reg_read_tgt,        WMI_REG_READ_CMDID,           0},
1756         {ath_hal_reg_write_tgt,       WMI_REG_WRITE_CMDID,          0},
1757         {handle_rc_state_change_cmd,  WMI_RC_STATE_CHANGE_CMDID,    0},
1758         {handle_rc_rate_update_cmd,   WMI_RC_RATE_UPDATE_CMDID,     0},
1759         {ath_ic_update_tgt,           WMI_TARGET_IC_UPDATE_CMDID,   0},
1760         {ath_enable_aggr_tgt,         WMI_TX_AGGR_ENABLE_CMDID,     0},
1761         {ath_detach_tgt,              WMI_TGT_DETACH_CMDID,         0},
1762         {ath_node_update_tgt,         WMI_NODE_UPDATE_CMDID,        0},
1763         {ath_int_stats_tgt,           WMI_INT_STATS_CMDID,          0},
1764         {ath_tx_stats_tgt,            WMI_TX_STATS_CMDID,           0},
1765         {ath_rx_stats_tgt,            WMI_RX_STATS_CMDID,           0},
1766         {ath_rc_mask_tgt,             WMI_BITRATE_MASK_CMDID,       0},
1767 };
1768
1769 /*****************/
1770 /* Init / Deinit */
1771 /*****************/
1772
1773 static void htc_setup_comp(void)
1774 {
1775 }
1776
1777 static A_UINT8 tgt_ServiceConnect(HTC_SERVICE *pService,
1778                                   HTC_ENDPOINT_ID eid,
1779                                   A_UINT8 *pDataIn,
1780                                   a_int32_t LengthIn,
1781                                   A_UINT8 *pDataOut,
1782                                   a_int32_t *pLengthOut)
1783 {
1784         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)pService->ServiceCtx;
1785
1786         switch(pService->ServiceID) {
1787         case WMI_CONTROL_SVC:
1788                 sc->wmi_command_ep= eid;
1789                 break;
1790         case WMI_BEACON_SVC:
1791                 sc->beacon_ep= eid;
1792                 break;
1793         case WMI_CAB_SVC:
1794                 sc->cab_ep= eid;
1795                 break;
1796         case WMI_UAPSD_SVC:
1797                 sc->uapsd_ep= eid;
1798                 break;
1799         case WMI_MGMT_SVC:
1800                 sc->mgmt_ep= eid;
1801                 break;
1802         case WMI_DATA_VO_SVC:
1803                 sc->data_VO_ep = eid;
1804                 break;
1805         case WMI_DATA_VI_SVC:
1806                 sc->data_VI_ep = eid;
1807                 break;
1808         case WMI_DATA_BE_SVC:
1809                 sc->data_BE_ep = eid;
1810                 break;
1811         case WMI_DATA_BK_SVC:
1812                 sc->data_BK_ep = eid;
1813                 break;
1814         default:
1815                 adf_os_assert(0);
1816         }
1817
1818         return HTC_SERVICE_SUCCESS;
1819 }
1820
1821 static void tgt_reg_service(struct ath_softc_tgt *sc, HTC_SERVICE *svc,
1822                             int svcId, HTC_SERVICE_ProcessRecvMsg recvMsg)
1823 {
1824         svc->ProcessRecvMsg = recvMsg;
1825         svc->ProcessSendBufferComplete = tgt_HTCSendCompleteHandler;
1826         svc->ProcessConnect = tgt_ServiceConnect;
1827         svc->MaxSvcMsgSize = 1600;
1828         svc->TrailerSpcCheckLimit = 0;
1829         svc->ServiceID = svcId;
1830         svc->ServiceCtx = sc;
1831         HTC_RegisterService(sc->tgt_htc_handle, svc);
1832 }
1833
1834 static void tgt_hif_htc_wmi_init(struct ath_softc_tgt *sc)
1835 {
1836         HTC_CONFIG htc_conf;
1837         WMI_SVC_CONFIG wmiConfig;
1838         WMI_DISPATCH_TABLE *Magpie_Sys_Commands_Tbl;
1839
1840         /* Init dynamic buf pool */
1841         sc->pool_handle = BUF_Pool_init(sc->sc_hdl);
1842
1843         /* Init target-side HIF */
1844         sc->tgt_hif_handle = HIF_init(0);
1845
1846         /* Init target-side HTC */
1847         htc_conf.HIFHandle = sc->tgt_hif_handle;
1848         htc_conf.CreditSize = 320;
1849         htc_conf.CreditNumber = ATH_TXBUF;
1850         htc_conf.OSHandle = sc->sc_hdl;
1851         htc_conf.PoolHandle = sc->pool_handle;
1852         sc->tgt_htc_handle = HTC_init(htc_setup_comp, &htc_conf);
1853 #if defined(PROJECT_MAGPIE)
1854         init_htc_handle = sc->tgt_htc_handle;
1855 #endif
1856
1857         tgt_reg_service(sc, &sc->htc_beacon_service, WMI_BEACON_SVC, tgt_HTCRecv_beaconhandler);
1858         tgt_reg_service(sc, &sc->htc_cab_service, WMI_CAB_SVC, tgt_HTCRecv_cabhandler);
1859         tgt_reg_service(sc, &sc->htc_uapsd_service, WMI_UAPSD_SVC, tgt_HTCRecv_uapsdhandler);
1860         tgt_reg_service(sc, &sc->htc_mgmt_service, WMI_MGMT_SVC, tgt_HTCRecv_mgmthandler);
1861         tgt_reg_service(sc, &sc->htc_data_BE_service, WMI_DATA_BE_SVC, tgt_HTCRecvMessageHandler);
1862         tgt_reg_service(sc, &sc->htc_data_BK_service, WMI_DATA_BK_SVC, tgt_HTCRecvMessageHandler);
1863         tgt_reg_service(sc, &sc->htc_data_VI_service, WMI_DATA_VI_SVC, tgt_HTCRecvMessageHandler);
1864         tgt_reg_service(sc, &sc->htc_data_VO_service, WMI_DATA_VO_SVC, tgt_HTCRecvMessageHandler);
1865
1866         /* Init target-side WMI */
1867         Magpie_Sys_Commands_Tbl = (WMI_DISPATCH_TABLE *)adf_os_mem_alloc(sizeof(WMI_DISPATCH_TABLE));
1868         adf_os_mem_zero(Magpie_Sys_Commands_Tbl, sizeof(WMI_DISPATCH_TABLE));
1869         Magpie_Sys_Commands_Tbl->NumberOfEntries = WMI_DISPATCH_ENTRY_COUNT(Magpie_Sys_DispatchEntries);
1870         Magpie_Sys_Commands_Tbl->pTable = Magpie_Sys_DispatchEntries;
1871
1872         adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG));
1873         wmiConfig.HtcHandle = sc->tgt_htc_handle;
1874         wmiConfig.PoolHandle = sc->pool_handle;
1875         wmiConfig.MaxCmdReplyEvts = ATH_WMI_MAX_CMD_REPLY;
1876         wmiConfig.MaxEventEvts = ATH_WMI_MAX_EVENTS;
1877
1878         sc->tgt_wmi_handle = WMI_Init(&wmiConfig);
1879         Magpie_Sys_Commands_Tbl->pContext = sc;
1880         WMI_RegisterDispatchTable(sc->tgt_wmi_handle, Magpie_Sys_Commands_Tbl);
1881
1882         HTC_NotifyTargetInserted(sc->tgt_htc_handle);
1883
1884         /* Start HTC messages exchange */
1885         HTC_Ready(sc->tgt_htc_handle);
1886 }
1887
1888 a_int32_t ath_tgt_attach(a_uint32_t devid,a_uint32_t mem_start,
1889                          struct ath_softc_tgt *sc, adf_os_device_t osdev)
1890 {
1891         struct ath_hal *ah;
1892         HAL_STATUS status;
1893         a_int32_t error = 0, i, flags = 0;
1894         a_uint8_t csz;
1895
1896         adf_os_pci_config_read8(osdev, ATH_PCI_CACHE_LINE_SIZE, &csz);
1897
1898         if (csz == 0)
1899                 csz = 16;
1900         sc->sc_cachelsz = csz << 2;
1901
1902         sc->sc_dev = osdev;
1903         sc->sc_hdl = osdev;
1904
1905         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_rxtq, ath_tgt_rx_tasklet, sc);
1906         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_txtq, owl_tgt_tx_tasklet, sc);
1907         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_bmisstq, ath_bmiss_tasklet, sc);
1908         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_fataltq, ath_fatal_tasklet, sc);
1909
1910         flags |= AH_USE_EEPROM;
1911         ah = _ath_hal_attach_tgt(devid,sc,sc->sc_dev,mem_start, flags, &status);
1912         if (ah == NULL) {
1913                 error = ENXIO;
1914                 goto bad;
1915         }
1916         sc->sc_ah = ah;
1917
1918         tgt_hif_htc_wmi_init(sc);
1919
1920         sc->sc_bhalq = HAL_NUM_TX_QUEUES - 1;
1921
1922         ath_rate_setup(sc, IEEE80211_MODE_11NA);
1923         ath_rate_setup(sc, IEEE80211_MODE_11NG);
1924
1925         sc->sc_rc = ath_rate_attach(sc);
1926         if (sc->sc_rc == NULL) {
1927                 error = EIO;
1928                 goto bad2;
1929         }
1930
1931         for (i=0; i < TARGET_NODE_MAX; i++) {
1932                 sc->sc_sta[i].an_rcnode = adf_os_mem_alloc(sc->sc_rc->arc_space);
1933         }
1934
1935         error = ath_desc_alloc(sc);
1936         if (error != 0) {
1937                 goto bad;
1938         }
1939
1940         BUF_Pool_create_pool(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ath_numrxdescs, 1664);
1941
1942         ath_tgt_txq_setup(sc);
1943         sc->sc_imask =0;
1944         ath_hal_intrset(ah,0);
1945
1946         return 0;
1947 bad:
1948 bad2:
1949         ath_desc_free(sc);
1950         if (ah)
1951                 ath_hal_detach(ah);
1952 }
1953
1954 static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)
1955 {
1956         HTC_NotifyTargetDetached(sc->tgt_htc_handle);
1957
1958         WMI_Shutdown(sc->tgt_wmi_handle);
1959         HTC_Shutdown(sc->tgt_htc_handle);
1960         HIF_shutdown(sc->tgt_hif_handle);
1961         BUF_Pool_shutdown(sc->pool_handle);
1962 }
1963
1964 a_int32_t ath_detach(struct ath_softc_tgt *sc)
1965 {
1966         tgt_hif_htc_wmi_shutdown(sc);
1967 }