target_firmware/wlan/if_ath.c

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <adf_os_types.h>
  37 #include <adf_os_pci.h>
  38 #include <adf_os_dma.h>
  39 #include <adf_os_timer.h>
  40 #include <adf_os_lock.h>
  41 #include <adf_os_io.h>
  42 #include <adf_os_mem.h>
  43 #include <adf_os_util.h>
  44 #include <adf_os_stdtypes.h>
  45 #include <adf_os_defer.h>
  46 #include <adf_os_atomic.h>
  47 #include <adf_nbuf.h>
  48 #include <adf_net.h>
  49 #include <adf_net_wcmd.h>
  50 #include <adf_os_irq.h>
  51
  52 #include <if_ath_pci.h>
  53 #include "if_llc.h"
  54 #include "ieee80211_var.h"
  55 #include "if_athrate.h"
  56 #include "if_athvar.h"
  57 #include "ah_desc.h"
  58 #include "ah.h"
  59
  60 static a_int32_t ath_numrxbufs = -1;
  61 static a_int32_t ath_numrxdescs = -1;
  62
  63 #if defined(PROJECT_MAGPIE)
  64 uint32_t *init_htc_handle = 0;
  65 #endif
  66
  67 #define RX_ENDPOINT_ID 3
  68 #define ATH_CABQ_HANDLING_THRESHOLD 9000
  69 #define UAPSDQ_NUM   9
  70 #define CABQ_NUM     8
  71
  72 void owl_tgt_tx_tasklet(TQUEUE_ARG data);
  73 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
  74 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
  75 extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
  76 extern void  ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
  77 extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
  78 extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,  owl_txq_state_t txqstate);
  79 void owl_tgt_node_init(struct ath_node_target * an);
  80 void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
  81 void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
  82
  83 /*
  84  * Extend a 32 bit TSF to 64 bit, taking wrapping into account.
  85  */
  86 static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
  87 {
  88         struct ath_hal *ah = sc->sc_ah;
  89         u_int64_t tsf;
  90         u_int32_t tsf_low;
  91         u_int64_t tsf64;
  92
  93         tsf = ah->ah_getTsf64(ah);
  94         tsf_low = tsf & 0xffffffff;
  95         tsf64 = (tsf & ~0xffffffffULL) | rstamp;
  96
  97         if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000))
  98                 tsf64 -= 0x100000000ULL;
  99
 100         if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000))
 101                 tsf64 += 0x100000000ULL;
 102
 103         return tsf64;
 104 }
 105
 106 static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode)
 107 {
 108         struct ath_hal *ah = sc->sc_ah;
 109         const HAL_RATE_TABLE *rt;
 110
 111         switch (mode) {
 112         case IEEE80211_MODE_11NA:
 113                 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NA);
 114                 break;
 115         case IEEE80211_MODE_11NG:
 116                 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NG);
 117                 break;
 118         default:
 119                 return 0;
 120         }
 121         rt = sc->sc_rates[mode];
 122         if (rt == NULL)
 123                 return 0;
 124
 125         return 1;
 126 }
 127
 128 static void ath_setcurmode(struct ath_softc_tgt *sc,
 129                            enum ieee80211_phymode mode)
 130 {
 131         const HAL_RATE_TABLE *rt;
 132         a_int32_t i;
 133
 134         adf_os_mem_set(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
 135
 136         rt = sc->sc_rates[mode];
 137         adf_os_assert(rt != NULL);
 138
 139         for (i = 0; i < rt->rateCount; i++) {
 140                 sc->sc_rixmap[rt->info[i].rateCode] = i;
 141         }
 142
 143         sc->sc_currates = rt;
 144         sc->sc_curmode = mode;
 145         sc->sc_protrix = ((mode == IEEE80211_MODE_11NG) ? 3 : 0);
 146
 147 }
 148
 149 void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
 150                void *buffer, a_int32_t Length)
 151 {
 152         adf_nbuf_t netbuf = ADF_NBUF_NULL;
 153         a_uint8_t *pData;
 154
 155         netbuf = WMI_AllocEvent(handle, WMI_EVT_CLASS_CMD_EVENT,
 156                                 sizeof(WMI_CMD_HDR) + Length);
 157
 158         if (netbuf == ADF_NBUF_NULL) {
 159                 adf_os_print("Buf null\n");
 160                 return;
 161         }
 162
 163         if (buffer != NULL && Length != 0 && Length < WMI_SVC_MAX_BUFFERED_EVENT_SIZE) {
 164                 pData = adf_nbuf_put_tail(netbuf, Length);
 165                 adf_os_mem_copy(pData, buffer, Length);
 166         }
 167
 168         WMI_SendEvent(handle, netbuf, evt_id, 0, Length);
 169 }
 170
 171 void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo,
 172                  void *buffer, a_int32_t Length)
 173 {
 174         adf_nbuf_t netbuf = ADF_NBUF_NULL;
 175         A_UINT8 *pData;
 176
 177         netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY,
 178                                 sizeof(WMI_CMD_HDR) + Length);
 179
 180         if (netbuf == ADF_NBUF_NULL) {
 181                 adf_os_assert(0);
 182                 return;
 183         }
 184
 185         if (Length != 0 && buffer != NULL) {
 186                 pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length);
 187                 adf_os_mem_copy(pData, buffer, Length);
 188         }
 189
 190         WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length);
 191 }
 192
 193 static void ath_node_vdelete_tgt(struct ath_softc_tgt *sc, a_uint8_t vap_index)
 194 {
 195         a_int32_t i;
 196
 197         for (i = 0; i < TARGET_NODE_MAX; i++) {
 198                 if(sc->sc_sta[i].ni.ni_vapindex == vap_index)
 199                         sc->sc_sta[i].an_valid = 0;
 200         }
 201 }
 202
 203 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp)
 204 {
 205         if (sc->sc_curmode == IEEE80211_MODE_11NG)
 206                 return avp->av_minrateidx[0];
 207         else if (sc->sc_curmode == IEEE80211_MODE_11NA)
 208                 return avp->av_minrateidx[1];
 209
 210         return 0;
 211 }
 212
 213 /******/
 214 /* RX */
 215 /******/
 216
 217 static adf_nbuf_t ath_alloc_skb_align(struct ath_softc_tgt *sc,
 218                                       a_uint32_t size, a_uint32_t align)
 219 {
 220         adf_nbuf_t skb;
 221
 222         skb = BUF_Pool_alloc_buf_align(sc->pool_handle, POOL_ID_WLAN_RX_BUF,
 223                                        RX_HEADER_SPACE, align);
 224         return skb;
 225 }
 226
 227 static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *ds)
 228 {
 229         struct ath_hal *ah = sc->sc_ah;
 230         struct ath_rx_desc *ds_held;
 231         a_uint8_t *anbdata;
 232         a_uint32_t anblen;
 233
 234         if (!sc->sc_rxdesc_held) {
 235                 sc->sc_rxdesc_held = ds;
 236                 return 0;
 237         }
 238
 239         ds_held = sc->sc_rxdesc_held;
 240         sc->sc_rxdesc_held = ds;
 241         ds = ds_held;
 242
 243         if (ds->ds_nbuf == ADF_NBUF_NULL) {
 244                 ds->ds_nbuf = ath_alloc_skb_align(sc, sc->sc_rxbufsize, sc->sc_cachelsz);
 245                 if (ds->ds_nbuf == ADF_NBUF_NULL) {
 246                         sc->sc_rxdesc_held = ds;
 247                         sc->sc_rx_stats.ast_rx_nobuf++;
 248                         return ENOMEM;
 249                 }
 250                 adf_nbuf_map(sc->sc_dev, ds->ds_dmap, ds->ds_nbuf, ADF_OS_DMA_FROM_DEVICE);
 251                 adf_nbuf_dmamap_info(ds->ds_dmap, &ds->ds_dmap_info);
 252                 ds->ds_data = ds->ds_dmap_info.dma_segs[0].paddr;
 253         }
 254
 255         ds->ds_link = 0;
 256         adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
 257
 258         ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0);
 259
 260         if (sc->sc_rxlink == NULL) {
 261                 ah->ah_setRxDP(ah, ds->ds_daddr);
 262         }
 263         else {
 264                 *sc->sc_rxlink = ds->ds_daddr;
 265         }
 266         sc->sc_rxlink = &ds->ds_link;
 267         ah->ah_enableReceive(ah);
 268
 269         return 0;
 270 }
 271
 272 static void ath_rx_complete(struct ath_softc_tgt *sc, adf_nbuf_t buf)
 273 {
 274         struct ath_rx_desc *ds;
 275         adf_nbuf_t buf_tmp;
 276         adf_nbuf_queue_t nbuf_head;
 277
 278         adf_nbuf_split_to_frag(buf, &nbuf_head);
 279         ds = asf_tailq_first(&sc->sc_rxdesc_idle);
 280
 281         while (ds) {
 282                 struct ath_rx_desc *ds_tmp;
 283                 buf_tmp = adf_nbuf_queue_remove(&nbuf_head);
 284
 285                 if (buf_tmp == NULL) {
 286                         break;
 287                 }
 288
 289                 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, buf_tmp);
 290
 291                 ds_tmp = ds;
 292                 ds = asf_tailq_next(ds, ds_list);
 293
 294                 ath_rxdesc_init(sc, ds_tmp);
 295
 296                 asf_tailq_remove(&sc->sc_rxdesc_idle, ds_tmp, ds_list);
 297                 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_tmp, ds_list);
 298         }
 299 }
 300
 301 static void tgt_HTCSendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t buf, void *ServiceCtx)
 302 {
 303         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 304
 305         if (Endpt == RX_ENDPOINT_ID) {
 306                 sc->sc_rx_stats.ast_rx_done++;
 307                 ath_rx_complete(sc, buf);
 308         }
 309 }
 310
 311 static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc)
 312 {
 313         struct ath_hal *ah = sc->sc_ah;
 314         struct ath_rx_buf *bf = NULL;
 315         struct ath_rx_desc *ds, *ds_head, *ds_tail, *ds_tmp;
 316         a_int32_t retval;
 317         a_uint32_t cnt = 0;
 318         a_uint16_t frame_len = 0;
 319         a_uint64_t tsf;
 320
 321 #define PA2DESC(_sc, _pa)                                               \
 322         ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc +         \
 323                              ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
 324
 325         tsf = ah->ah_getTsf64(ah);
 326         bf = asf_tailq_first(&sc->sc_rxbuf);
 327
 328         ds = asf_tailq_first(&sc->sc_rxdesc);
 329         ds_head = ds;
 330
 331         while(ds) {
 332                 ++cnt;
 333
 334                 if (cnt == ath_numrxbufs - 1) {
 335                         adf_os_print("VERY LONG PACKET!!!!!\n");
 336                         ds_tail = ds;
 337                         ds_tmp = ds_head;
 338                         while (ds_tmp) {
 339                                 struct ath_rx_desc *ds_rmv;
 340                                 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
 341                                 ds_rmv = ds_tmp;
 342                                 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
 343
 344                                 if (ds_tmp == NULL) {
 345                                         adf_os_print("ds_tmp is NULL\n");
 346                                         adf_os_assert(0);
 347                                 }
 348
 349                                 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ds_rmv->ds_nbuf);
 350                                 ds_rmv->ds_nbuf = ADF_NBUF_NULL;
 351
 352                                 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
 353                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 354                                         asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
 355                                 }
 356                                 else {
 357                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 358                                         asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
 359                                 }
 360
 361                                 if (ds_rmv == ds_tail) {
 362                                         break;
 363                                 }
 364                         }
 365                         break;
 366                 }
 367
 368                 if (ds->ds_link == 0) {
 369                         break;
 370                 }
 371
 372                 if (bf->bf_status & ATH_BUFSTATUS_DONE) {
 373                         continue;
 374                 }
 375
 376                 retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr,
 377                                                 PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
 378                 if (HAL_EINPROGRESS == retval) {
 379                         break;
 380                 }
 381
 382                 if (adf_nbuf_len(ds->ds_nbuf) == 0) {
 383                         adf_nbuf_put_tail(ds->ds_nbuf, bf->bf_rx_status.rs_datalen);
 384                 }
 385
 386                 frame_len += bf->bf_rx_status.rs_datalen;
 387
 388                 if (bf->bf_rx_status.rs_more == 0) {
 389                         adf_nbuf_queue_t nbuf_head;
 390                         adf_nbuf_queue_init(&nbuf_head);
 391
 392                         cnt = 0;
 393
 394                         ds_tail = ds;
 395                         ds = asf_tailq_next(ds, ds_list);
 396
 397                         ds_tmp = ds_head;
 398                         ds_head = asf_tailq_next(ds_tail, ds_list);
 399
 400                         while (ds_tmp) {
 401                                 struct ath_rx_desc *ds_rmv;
 402
 403                                 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
 404                                 adf_nbuf_queue_add(&nbuf_head, ds_tmp->ds_nbuf);
 405                                 ds_tmp->ds_nbuf = ADF_NBUF_NULL;
 406
 407                                 ds_rmv = ds_tmp;
 408                                 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
 409                                 if (ds_tmp == NULL) {
 410                                         adf_os_assert(0);
 411                                 }
 412
 413                                 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
 414                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 415                                         asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
 416                                 }  else {
 417                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 418                                         asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
 419                                 }
 420
 421                                 if (ds_rmv == ds_tail) {
 422                                         break;
 423                                 }
 424                         }
 425
 426
 427                         bf->bf_rx_status.rs_datalen = frame_len;
 428                         frame_len = 0;
 429
 430                         bf->bf_skb = adf_nbuf_create_frm_frag(&nbuf_head);
 431
 432                         bf->bf_status |= ATH_BUFSTATUS_DONE;
 433
 434                         bf = (struct ath_rx_buf *)asf_tailq_next(bf, bf_list);
 435                 }
 436                 else {
 437                         ds = asf_tailq_next(ds, ds_list);
 438                 }
 439         }
 440
 441 #undef PA2DESC
 442 }
 443
 444 static a_int32_t ath_startrecv(struct ath_softc_tgt *sc)
 445 {
 446         struct ath_hal *ah = sc->sc_ah;
 447         struct ath_rx_desc *ds;
 448
 449         sc->sc_rxbufsize = 1024+512+128;
 450         sc->sc_rxlink = NULL;
 451
 452         sc->sc_rxdesc_held = NULL;
 453
 454         asf_tailq_foreach(ds, &sc->sc_rxdesc, ds_list) {
 455                 a_int32_t error = ath_rxdesc_init(sc, ds);
 456                 if (error != 0) {
 457                         return error;
 458                 }
 459         }
 460
 461         ds = asf_tailq_first(&sc->sc_rxdesc);
 462         ah->ah_setRxDP(ah, ds->ds_daddr);
 463
 464         return 0;
 465 }
 466
 467 static void ath_tgt_rx_tasklet(TQUEUE_ARG data)
 468 {
 469         struct ath_softc_tgt *sc  = (struct ath_softc_tgt *)data;
 470         struct ath_rx_buf *bf = NULL;
 471         struct ath_hal *ah = sc->sc_ah;
 472         struct rx_frame_header *rxhdr;
 473         struct ath_rx_status *rxstats;
 474         adf_nbuf_t skb = ADF_NBUF_NULL;
 475
 476         do {
 477                 bf = asf_tailq_first(&sc->sc_rxbuf);
 478                 if (bf == NULL) {
 479                         break;
 480                 }
 481
 482                 if (!(bf->bf_status & ATH_BUFSTATUS_DONE)) {
 483                         break;
 484                 }
 485
 486                 skb = bf->bf_skb;
 487                 if (skb == NULL) {
 488                         continue;
 489                 }
 490
 491                 asf_tailq_remove(&sc->sc_rxbuf, bf, bf_list);
 492
 493                 bf->bf_skb = NULL;
 494
 495                 rxhdr = (struct rx_frame_header *)adf_nbuf_push_head(skb,
 496                                                      sizeof(struct rx_frame_header));
 497                 rxstats = (struct ath_rx_status *)(&rxhdr->rx_stats[0]);
 498                 adf_os_mem_copy(rxstats, &(bf->bf_rx_status),
 499                                 sizeof(struct ath_rx_status));
 500
 501                 rxstats->rs_tstamp = ath_extend_tsf(sc, (u_int32_t)rxstats->rs_tstamp);
 502
 503                 HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb);
 504                 sc->sc_rx_stats.ast_rx_send++;
 505
 506                 bf->bf_status &= ~ATH_BUFSTATUS_DONE;
 507                 asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list);
 508
 509         } while(1);
 510
 511         sc->sc_imask |= HAL_INT_RX;
 512         ah->ah_setInterrupts(ah, sc->sc_imask);
 513 }
 514
 515 /*******************/
 516 /* Beacon Handling */
 517 /*******************/
 518
 519 /*
 520  * Setup the beacon frame for transmit.
 521  * FIXME: Short Preamble.
 522  */
 523 static void ath_beacon_setup(struct ath_softc_tgt *sc,
 524                              struct ath_tx_buf *bf,
 525                              struct ath_vap_target *avp)
 526 {
 527         adf_nbuf_t skb = bf->bf_skb;
 528         struct ath_hal *ah = sc->sc_ah;
 529         struct ath_tx_desc *ds;
 530         a_int32_t flags;
 531         const HAL_RATE_TABLE *rt;
 532         a_uint8_t rix, rate;
 533         HAL_11N_RATE_SERIES series[4] = {{ 0 }};
 534
 535         flags = HAL_TXDESC_NOACK;
 536
 537         ds = bf->bf_desc;
 538         ds->ds_link = 0;
 539         ds->ds_data = bf->bf_dmamap_info.dma_segs[0].paddr;
 540
 541         rix = ath_get_minrateidx(sc, avp);
 542         rt  = sc->sc_currates;
 543         rate = rt->info[rix].rateCode;
 544
 545         ah->ah_setupTxDesc(ds
 546                             , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
 547                             , sizeof(struct ieee80211_frame)
 548                             , HAL_PKT_TYPE_BEACON
 549                             , MAX_RATE_POWER
 550                             , rate, 1
 551                             , HAL_TXKEYIX_INVALID
 552                             , flags
 553                             , 0
 554                             , 0);
 555
 556         ah->ah_fillTxDesc(ds
 557                            , asf_roundup(adf_nbuf_len(skb), 4)
 558                            , AH_TRUE
 559                            , AH_TRUE
 560                            , ds);
 561
 562         series[0].Tries = 1;
 563         series[0].Rate = rate;
 564         series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
 565         series[0].RateFlags = 0;
 566         ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0);
 567 }
 568
 569 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
 570                                 adf_nbuf_t nbuf, HTC_ENDPOINT_ID EndPt)
 571 {
 572         struct ath_hal *ah = sc->sc_ah;
 573         struct ath_tx_buf *bf;
 574         a_uint8_t vap_index, *anbdata;
 575         ath_beacon_hdr_t *bhdr;
 576         struct ieee80211vap_target  *vap;
 577         a_uint32_t anblen;
 578         struct ieee80211_frame *wh;
 579
 580         if (!bc_hdr) {
 581                 adf_nbuf_peek_header(nbuf, &anbdata, &anblen);
 582                 bhdr = (ath_beacon_hdr_t *)anbdata;
 583         } else {
 584                 adf_os_print("found bc_hdr! 0x%x\n", bc_hdr);
 585         }
 586
 587         vap_index = bhdr->vap_index;
 588         adf_os_assert(vap_index < TARGET_VAP_MAX);
 589         vap = &sc->sc_vap[vap_index].av_vap;
 590
 591         wh = (struct ieee80211_frame *)adf_nbuf_pull_head(nbuf,
 592                                                   sizeof(ath_beacon_hdr_t));
 593
 594         bf = sc->sc_vap[vap_index].av_bcbuf;
 595         adf_os_assert(bf);
 596         bf->bf_endpt = EndPt;
 597
 598         if (bf->bf_skb) {
 599                 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
 600                 adf_nbuf_push_head(bf->bf_skb, sizeof(ath_beacon_hdr_t));
 601                 ath_free_tx_skb(sc->tgt_htc_handle, bf->bf_endpt, bf->bf_skb);
 602         }
 603
 604         bf->bf_skb = nbuf;
 605
 606         adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, nbuf, ADF_OS_DMA_TO_DEVICE);
 607         adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info);
 608
 609         ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]);
 610         ah->ah_stopTxDma(ah, sc->sc_bhalq);
 611         ah->ah_setTxDP(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
 612         ah->ah_startTxDma(ah, sc->sc_bhalq);
 613 }
 614
 615 /******/
 616 /* TX */
 617 /******/
 618
 619 static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq)
 620 {
 621         struct ath_hal *ah = sc->sc_ah;
 622
 623         ah->ah_stopTxDma(ah, txq->axq_qnum);
 624 }
 625
 626 static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq)
 627 {
 628         owltgt_tx_processq(sc, txq, OWL_TXQ_STOPPED);
 629 }
 630
 631 static void ath_tx_draintxq(struct ath_softc_tgt *sc, struct ath_txq *txq)
 632 {
 633         owltgt_txq_drain(sc, txq);
 634 }
 635
 636 static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq)
 637 {
 638         struct ath_hal *ah = sc->sc_ah;
 639         a_uint16_t i;
 640         struct ath_txq *txq = NULL;
 641         struct ath_atx_tid *tid = NULL;
 642
 643         ath_tx_status_clear(sc);
 644         sc->sc_tx_draining = 1;
 645
 646         ah->ah_stopTxDma(ah, sc->sc_bhalq);
 647
 648         for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
 649                 if (ATH_TXQ_SETUP(sc, i))
 650                         ath_tx_stopdma(sc, ATH_TXQ(sc, i));
 651
 652         for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
 653                 if (ATH_TXQ_SETUP(sc, i)) {
 654                         owltgt_tx_processq(sc, ATH_TXQ(sc,i), OWL_TXQ_STOPPED);
 655
 656                         txq = ATH_TXQ(sc,i);
 657                         while (!asf_tailq_empty(&txq->axq_tidq)){
 658                                 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
 659                                 if(tid == NULL)
 660                                         break;
 661                                 tid->sched = AH_FALSE;
 662                                 ath_tgt_tid_drain(sc,tid);
 663                         }
 664                 }
 665
 666         sc->sc_tx_draining = 0;
 667 }
 668
 669 static void ath_tgt_txq_setup(struct ath_softc_tgt *sc)
 670 {
 671         a_int32_t qnum;
 672         struct ath_txq *txq;
 673
 674         sc->sc_txqsetup=0;
 675
 676         for (qnum=0;qnum<HAL_NUM_TX_QUEUES;qnum++) {
 677                 txq= &sc->sc_txq[qnum];
 678                 txq->axq_qnum = qnum;
 679                 txq->axq_link = NULL;
 680                 asf_tailq_init(&txq->axq_q);
 681                 txq->axq_depth = 0;
 682                 txq->axq_linkbuf = NULL;
 683                 asf_tailq_init(&txq->axq_tidq);
 684                 sc->sc_txqsetup |= 1<<qnum;
 685         }
 686
 687         sc->sc_uapsdq  = &sc->sc_txq[UAPSDQ_NUM];
 688         sc->sc_cabq    = &sc->sc_txq[CABQ_NUM];
 689
 690         sc->sc_ac2q[WME_AC_BE]  = &sc->sc_txq[0];
 691         sc->sc_ac2q[WME_AC_BK]  = &sc->sc_txq[1];
 692         sc->sc_ac2q[WME_AC_VI]  = &sc->sc_txq[2];
 693         sc->sc_ac2q[WME_AC_VO]  = &sc->sc_txq[3];
 694
 695         return;
 696 #undef N
 697 }
 698
 699 static void tgt_HTCRecv_beaconhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 700                                       adf_nbuf_t buf, void *ServiceCtx)
 701 {
 702         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 703
 704         ath_tgt_send_beacon(sc, hdr_buf, buf, EndPt);
 705 }
 706
 707 static void tgt_HTCRecv_uapsdhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 708                                      adf_nbuf_t buf, void *ServiceCtx)
 709 {
 710 }
 711
 712 static void tgt_HTCRecv_mgmthandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 713                                     adf_nbuf_t buf, void *ServiceCtx)
 714 {
 715         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 716
 717         ath_tgt_send_mgt(sc,hdr_buf,buf,EndPt);
 718 }
 719
 720 static void tgt_HTCRecvMessageHandler(HTC_ENDPOINT_ID EndPt,
 721                                       adf_nbuf_t hdr_buf, adf_nbuf_t buf,
 722                                       void *ServiceCtx)
 723 {
 724         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 725         struct ath_tx_buf *bf;
 726         a_uint8_t *data;
 727         a_uint32_t len;
 728         ath_data_hdr_t *dh;
 729         struct ath_node_target *an;
 730         struct ath_atx_tid *tid;
 731
 732         if (!hdr_buf) {
 733                 adf_nbuf_peek_header(buf, &data, &len);
 734                 adf_nbuf_pull_head(buf, sizeof(ath_data_hdr_t));
 735         } else {
 736                 adf_nbuf_peek_header(hdr_buf, &data, &len);
 737         }
 738
 739         adf_os_assert(len >= sizeof(ath_data_hdr_t));
 740         dh = (ath_data_hdr_t *)data;
 741
 742         an = &sc->sc_sta[dh->ni_index];
 743         tid = ATH_AN_2_TID(an, dh->tidno);
 744
 745         sc->sc_tx_stats.tx_tgt++;
 746
 747         bf = ath_tgt_tx_prepare(sc, buf, dh);
 748         if (!bf) {
 749                 ath_free_tx_skb(sc->tgt_htc_handle,EndPt,buf);
 750                 return;
 751         }
 752
 753         bf->bf_endpt = EndPt;
 754         bf->bf_cookie = dh->cookie;
 755
 756         if (tid->flag & TID_AGGR_ENABLED)
 757                 ath_tgt_handle_aggr(sc, bf);
 758         else
 759                 ath_tgt_handle_normal(sc, bf);
 760 }
 761
 762 static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 763                                    adf_nbuf_t buf, void *ServiceCtx)
 764 {
 765         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 766         struct ath_hal *ah = sc->sc_ah;
 767         a_uint64_t tsf;
 768         a_uint32_t tmp;
 769
 770 #ifdef ATH_ENABLE_CABQ
 771         tsf = ah->ah_getTsf64(ah);
 772         tmp = tsf - sc->sc_swba_tsf;
 773
 774         if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
 775                 HTC_ReturnBuffers(sc->tgt_htc_handle, EndPt, buf);
 776                 return;
 777         }
 778
 779         tgt_HTCRecvMessageHandler(EndPt, hdr_buf, buf, ServiceCtx);
 780 #endif
 781 }
 782
 783 /***********************/
 784 /* Descriptor Handling */
 785 /***********************/
 786
 787 static a_int32_t ath_descdma_setup(struct ath_softc_tgt *sc,
 788                                    struct ath_descdma *dd, ath_bufhead *head,
 789                                    const char *name, a_int32_t nbuf, a_int32_t ndesc,
 790                                    a_uint32_t bfSize, a_uint32_t descSize)
 791 {
 792 #define DS2PHYS(_dd, _ds)                                               \
 793         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 794
 795         struct ath_desc *ds;
 796         struct ath_buf *bf;
 797         a_int32_t i, bsize, error;
 798         a_uint8_t *bf_addr;
 799         a_uint8_t *ds_addr;
 800
 801         dd->dd_name = name;
 802         dd->dd_desc_len = descSize * nbuf * ndesc;
 803
 804         dd->dd_desc = adf_os_dmamem_alloc(sc->sc_dev,
 805                                   dd->dd_desc_len, 1, &dd->dd_desc_dmamap);
 806         dd->dd_desc_paddr = adf_os_dmamem_map2addr(dd->dd_desc_dmamap);
 807         if (dd->dd_desc == NULL) {
 808                 error = -ENOMEM;
 809                 goto fail;
 810         }
 811         ds = dd->dd_desc;
 812
 813         bsize = bfSize * nbuf;
 814         bf = adf_os_mem_alloc(bsize);
 815         if (bf == NULL) {
 816                 error = -ENOMEM;
 817                 goto fail2;
 818         }
 819         adf_os_mem_set(bf, 0, bsize);
 820         dd->dd_bufptr = bf;
 821
 822         bf_addr = (a_uint8_t *)bf;
 823         ds_addr = (a_uint8_t *)ds;
 824
 825         asf_tailq_init(head);
 826
 827         for (i = 0; i < nbuf; i++) {
 828                 a_int32_t j;
 829
 830                 if (adf_nbuf_dmamap_create( sc->sc_dev, &bf->bf_dmamap) != A_STATUS_OK) {
 831                         goto fail2;
 832                 }
 833
 834                 bf->bf_desc = bf->bf_descarr = bf->bf_lastds = ds;
 835                 for (j = 0; j < ndesc; j++)
 836                         ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, j, (ds_addr + (j*descSize)));
 837
 838                 ATH_BUF_SET_DESC_PHY_ADDR(bf, ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, 0));
 839
 840                 adf_nbuf_queue_init(&bf->bf_skbhead);
 841                 asf_tailq_insert_tail(head, bf, bf_list);
 842
 843                 bf_addr += bfSize;
 844                 ds_addr += (ndesc * descSize);
 845                 bf = (struct ath_buf *)bf_addr;
 846                 ds = (struct ath_desc *)ds_addr;
 847         }
 848
 849         return 0;
 850 fail2:
 851         adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
 852                            1, dd->dd_desc, dd->dd_desc_dmamap);
 853 fail:
 854         adf_os_mem_set(dd, 0, sizeof(*dd));
 855         adf_os_assert(0);
 856         return error;
 857
 858 #undef DS2PHYS
 859 }
 860
 861 static void ath_descdma_cleanup(struct ath_softc_tgt *sc,
 862                                 struct ath_descdma *dd,
 863                                 ath_bufhead *head, a_int32_t dir)
 864 {
 865         struct ath_buf *bf;
 866         struct ieee80211_node_target *ni;
 867
 868         asf_tailq_foreach(bf, head, bf_list) {
 869                 if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
 870                         adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, dir);
 871                         while(adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
 872                                 ath_free_rx_skb(sc,
 873                                         adf_nbuf_queue_remove(&bf->bf_skbhead));
 874                         }
 875                         bf->bf_skb = NULL;
 876                 } else if (bf->bf_skb != NULL) {
 877                         adf_nbuf_unmap(sc->sc_dev,bf->bf_dmamap, dir);
 878                         ath_free_rx_skb(sc, bf->bf_skb);
 879                         bf->bf_skb = NULL;
 880                 }
 881
 882                 adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap);
 883
 884                 ni = bf->bf_node;
 885                 bf->bf_node = NULL;
 886         }
 887
 888         adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
 889                            1, dd->dd_desc, dd->dd_desc_dmamap);
 890
 891         asf_tailq_init(head);
 892         adf_os_mem_free(dd->dd_bufptr);
 893         adf_os_mem_set(dd, 0, sizeof(*dd));
 894 }
 895
 896 static a_int32_t ath_desc_alloc(struct ath_softc_tgt *sc)
 897 {
 898 #define DS2PHYS(_dd, _ds)                                               \
 899         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 900
 901         a_int32_t error;
 902         struct ath_tx_buf *bf;
 903
 904         if(ath_numrxbufs == -1)
 905                 ath_numrxbufs = ATH_RXBUF;
 906
 907         if (ath_numrxdescs == -1)
 908                 ath_numrxdescs = ATH_RXDESC;
 909
 910         error = ath_descdma_setup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 911                                   "rx", ath_numrxdescs, 1,
 912                                   sizeof(struct ath_rx_buf),
 913                                   sizeof(struct ath_rx_desc));
 914         if (error != 0)
 915                 return error;
 916
 917         a_uint32_t i;
 918         struct ath_descdma *dd = &sc->sc_rxdma;
 919         struct ath_rx_desc *ds = (struct ath_rx_desc *)dd->dd_desc;
 920         struct ath_rx_desc *ds_prev = NULL;
 921
 922         asf_tailq_init(&sc->sc_rxdesc);
 923         asf_tailq_init(&sc->sc_rxdesc_idle);
 924
 925         for (i = 0; i < ath_numrxdescs; i++, ds++) {
 926
 927                 if (ds->ds_nbuf != ADF_NBUF_NULL) {
 928                         ds->ds_nbuf = ADF_NBUF_NULL;
 929                 }
 930
 931                 if (adf_nbuf_dmamap_create(sc->sc_dev, &ds->ds_dmap) != A_STATUS_OK) {
 932                         adf_os_assert(0);
 933                 }
 934
 935                 ds->ds_daddr = DS2PHYS(&sc->sc_rxdma, ds);
 936
 937                 if (ds_prev) {
 938                         ds_prev->ds_link = ds->ds_daddr;
 939                 }
 940
 941                 ds->ds_link = 0;
 942                 ds_prev = ds;
 943
 944                 asf_tailq_insert_tail(&sc->sc_rxdesc, ds, ds_list);
 945         }
 946
 947         error = ath_descdma_setup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 948                                   "tx", ATH_TXBUF + 1, ATH_TXDESC,
 949                                   sizeof(struct ath_tx_buf),
 950                                   sizeof(struct ath_tx_desc));
 951         if (error != 0) {
 952                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 953                                     ADF_OS_DMA_FROM_DEVICE);
 954                 return error;
 955         }
 956
 957         error = ath_descdma_setup(sc, &sc->sc_bdma, (ath_bufhead *)&sc->sc_bbuf,
 958                                   "beacon", ATH_BCBUF, 1,
 959                                   sizeof(struct ath_tx_buf),
 960                                   sizeof(struct ath_tx_desc));
 961         if (error != 0) {
 962                 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 963                                     ADF_OS_DMA_TO_DEVICE);
 964                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 965                                     ADF_OS_DMA_FROM_DEVICE);
 966                 return error;
 967         }
 968
 969         bf = asf_tailq_first(&sc->sc_txbuf);
 970         bf->bf_isaggr = bf->bf_isretried = bf->bf_retries = 0;
 971         asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
 972
 973         sc->sc_txbuf_held = bf;
 974
 975         return 0;
 976
 977 #undef DS2PHYS
 978 }
 979
 980 static void ath_desc_free(struct ath_softc_tgt *sc)
 981 {
 982         asf_tailq_insert_tail(&sc->sc_txbuf, sc->sc_txbuf_held, bf_list);
 983
 984         sc->sc_txbuf_held = NULL;
 985
 986         if (sc->sc_txdma.dd_desc_len != 0)
 987                 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 988                                     ADF_OS_DMA_TO_DEVICE);
 989         if (sc->sc_rxdma.dd_desc_len != 0)
 990                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 991                                     ADF_OS_DMA_FROM_DEVICE);
 992 }
 993
 994 /**********************/
 995 /* Interrupt Handling */
 996 /**********************/
 997
 998 adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl)
 999 {
1000         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl;
1001         struct ath_hal *ah = sc->sc_ah;
1002         HAL_INT status;
1003
1004         if (sc->sc_invalid)
1005                 return ADF_OS_IRQ_NONE;
1006
1007         if (!ah->ah_isInterruptPending(ah))
1008                 return ADF_OS_IRQ_NONE;
1009
1010         ah->ah_getPendingInterrupts(ah, &status);
1011
1012         status &= sc->sc_imask;
1013
1014         if (status & HAL_INT_FATAL) {
1015                 ah->ah_setInterrupts(ah, 0);
1016                 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
1017         } else {
1018                 if (status & HAL_INT_SWBA) {
1019                         WMI_SWBA_EVENT swbaEvt;
1020                         struct ath_txq *txq = ATH_TXQ(sc, 8);
1021
1022                         swbaEvt.tsf = ah->ah_getTsf64(ah);
1023                         swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq);
1024                         sc->sc_swba_tsf = ah->ah_getTsf64(ah);
1025
1026                         wmi_event(sc->tgt_wmi_handle,
1027                                   WMI_SWBA_EVENTID,
1028                                   &swbaEvt,
1029                                   sizeof(WMI_SWBA_EVENT));
1030
1031                         ath_tx_draintxq(sc, txq);
1032                 }
1033
1034                 if (status & HAL_INT_RXORN)
1035                         sc->sc_int_stats.ast_rxorn++;
1036
1037                 if (status & HAL_INT_RXEOL)
1038                         sc->sc_int_stats.ast_rxeol++;
1039
1040                 if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
1041                         if (status & HAL_INT_RX)
1042                                 sc->sc_int_stats.ast_rx++;
1043
1044                         ath_uapsd_processtriggers(sc);
1045
1046                         sc->sc_imask &= ~HAL_INT_RX;
1047                         ah->ah_setInterrupts(ah, sc->sc_imask);
1048
1049                         ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
1050                 }
1051
1052                 if (status & HAL_INT_TXURN) {
1053                         sc->sc_int_stats.ast_txurn++;
1054                         ah->ah_updateTxTrigLevel(ah, AH_TRUE);
1055                 }
1056
1057                 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq);
1058
1059                 if (status & HAL_INT_BMISS) {
1060                         ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_bmisstq);
1061                 }
1062
1063                 if (status & HAL_INT_GTT)
1064                         sc->sc_int_stats.ast_txto++;
1065
1066                 if (status & HAL_INT_CST)
1067                         sc->sc_int_stats.ast_cst++;
1068         }
1069
1070         return ADF_OS_IRQ_HANDLED;
1071 }
1072
1073 static void ath_fatal_tasklet(TQUEUE_ARG data )
1074 {
1075         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1076
1077         wmi_event(sc->tgt_wmi_handle, WMI_FATAL_EVENTID, NULL, 0);
1078 }
1079
1080 static void ath_bmiss_tasklet(TQUEUE_ARG data)
1081 {
1082         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1083
1084         wmi_event(sc->tgt_wmi_handle, WMI_BMISS_EVENTID, NULL, 0);
1085 }
1086
1087 /****************/
1088 /* WMI Commands */
1089 /****************/
1090
1091 static void ath_enable_intr_tgt(void *Context, A_UINT16 Command,
1092                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1093 {
1094         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1095         struct ath_hal *ah = sc->sc_ah;
1096         a_uint32_t intr;
1097
1098         if (data)
1099                 intr = (*(a_uint32_t *)data);
1100
1101         intr = adf_os_ntohl(intr);
1102
1103         if (intr & HAL_INT_SWBA) {
1104                 sc->sc_imask |= HAL_INT_SWBA;
1105         } else {
1106                 sc->sc_imask &= ~HAL_INT_SWBA;
1107         }
1108
1109         if (intr & HAL_INT_BMISS) {
1110                 sc->sc_imask |= HAL_INT_BMISS;
1111         }
1112
1113         ah->ah_setInterrupts(ah, sc->sc_imask);
1114         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1115 }
1116
1117 static void ath_init_tgt(void *Context, A_UINT16 Command,
1118                          A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1119 {
1120         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1121         struct ath_hal *ah = sc->sc_ah;
1122
1123         sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1124                 | HAL_INT_RXEOL | HAL_INT_RXORN
1125                 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1126
1127         sc->sc_imask |= HAL_INT_GTT;
1128
1129         if (ath_hal_getcapability(ah, HAL_CAP_HT))
1130                 sc->sc_imask |= HAL_INT_CST;
1131
1132         adf_os_setup_intr(sc->sc_dev, ath_intr);
1133         ah->ah_setInterrupts(ah, sc->sc_imask);
1134
1135         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1136 }
1137
1138 static void ath_int_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1139                               A_UINT8 *data, a_int32_t datalen)
1140 {
1141         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1142
1143         struct fusion_stats {
1144                 a_uint32_t ast_rx;
1145                 a_uint32_t ast_rxorn;
1146                 a_uint32_t ast_rxeol;
1147                 a_uint32_t ast_txurn;
1148                 a_uint32_t ast_txto;
1149                 a_uint32_t ast_cst;
1150         };
1151
1152         struct fusion_stats stats;
1153
1154         stats.ast_rx = sc->sc_int_stats.ast_rx;
1155         stats.ast_rxorn = sc->sc_int_stats.ast_rxorn;
1156         stats.ast_rxeol = sc->sc_int_stats.ast_rxeol;
1157         stats.ast_txurn = sc->sc_int_stats.ast_txurn;
1158         stats.ast_txto = sc->sc_int_stats.ast_txto;
1159         stats.ast_cst = sc->sc_int_stats.ast_cst;
1160
1161         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1162 }
1163
1164 static void ath_tx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1165                              A_UINT8 *data, a_int32_t datalen)
1166 {
1167         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1168
1169         struct fusion_stats {
1170                 a_uint32_t   ast_tx_xretries;
1171                 a_uint32_t   ast_tx_fifoerr;
1172                 a_uint32_t   ast_tx_filtered;
1173                 a_uint32_t   ast_tx_timer_exp;
1174                 a_uint32_t   ast_tx_shortretry;
1175                 a_uint32_t   ast_tx_longretry;
1176
1177                 a_uint32_t   tx_qnull;
1178                 a_uint32_t   tx_noskbs;
1179                 a_uint32_t   tx_nobufs;
1180         };
1181
1182         struct fusion_stats stats;
1183
1184         stats.ast_tx_xretries = sc->sc_tx_stats.ast_tx_xretries;
1185         stats.ast_tx_fifoerr = sc->sc_tx_stats.ast_tx_fifoerr;
1186         stats.ast_tx_filtered = sc->sc_tx_stats.ast_tx_filtered;
1187         stats.ast_tx_timer_exp = sc->sc_tx_stats.ast_tx_timer_exp;
1188         stats.ast_tx_shortretry = sc->sc_tx_stats.ast_tx_shortretry;
1189         stats.ast_tx_longretry = sc->sc_tx_stats.ast_tx_longretry;
1190         stats.tx_qnull = sc->sc_tx_stats.tx_qnull;
1191         stats.tx_noskbs = sc->sc_tx_stats.tx_noskbs;
1192         stats.tx_nobufs = sc->sc_tx_stats.tx_nobufs;
1193
1194         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1195 }
1196
1197 static void ath_rx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1198                              A_UINT8 *data, a_int32_t datalen)
1199 {
1200         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1201
1202         struct fusion_stats {
1203                 a_uint32_t   ast_rx_nobuf;
1204                 a_uint32_t   ast_rx_send;
1205                 a_uint32_t   ast_rx_done;
1206         };
1207
1208         struct fusion_stats stats;
1209
1210         stats.ast_rx_nobuf = sc->sc_rx_stats.ast_rx_nobuf;
1211         stats.ast_rx_send = sc->sc_rx_stats.ast_rx_send;
1212         stats.ast_rx_done = sc->sc_rx_stats.ast_rx_done;
1213
1214         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1215 }
1216
1217 static void ath_get_tgt_version(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1218                                 A_UINT8 *data, a_int32_t datalen)
1219 {
1220         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1221         struct wmi_fw_version ver;
1222
1223         ver.major = ATH_VERSION_MAJOR;
1224         ver.minor = ATH_VERSION_MINOR;
1225
1226         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &ver, sizeof(ver));
1227 }
1228
1229 static void ath_enable_aggr_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1230                                 A_UINT8 *data, a_int32_t datalen)
1231 {
1232         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1233         struct ath_aggr_info *aggr = (struct ath_aggr_info *)data;
1234         a_uint8_t nodeindex = aggr->nodeindex;
1235         a_uint8_t tidno = aggr->tidno;
1236         struct ath_node_target *an = NULL ;
1237         struct ath_atx_tid  *tid = NULL;
1238
1239         if (nodeindex >= TARGET_NODE_MAX) {
1240                 goto done;
1241         }
1242
1243         an = &sc->sc_sta[nodeindex];
1244         if (!an->an_valid) {
1245                 goto done;
1246         }
1247
1248         if (tidno >= WME_NUM_TID) {
1249                 adf_os_print("[%s] enable_aggr with invalid tid %d(node = %d)\n",
1250                              __FUNCTION__, tidno, nodeindex);
1251                 goto done;
1252         }
1253
1254         tid = ATH_AN_2_TID(an, tidno);
1255
1256         if (aggr->aggr_enable) {
1257                 tid->flag |= TID_AGGR_ENABLED;
1258         } else if ( tid->flag & TID_AGGR_ENABLED ) {
1259                 tid->flag &= ~TID_AGGR_ENABLED;
1260                 ath_tgt_tx_cleanup(sc, an, tid, 1);
1261         }
1262 done:
1263         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1264 }
1265
1266 static void ath_ic_update_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1267                               A_UINT8 *data, a_int32_t datalen)
1268 {
1269         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1270         struct ieee80211com_target *ic = (struct ieee80211com_target * )data;
1271         struct ieee80211com_target *ictgt = &sc->sc_ic ;
1272
1273         adf_os_mem_copy(ictgt, ic, sizeof(struct  ieee80211com_target));
1274
1275         ictgt->ic_ampdu_limit         = adf_os_ntohl(ic->ic_ampdu_limit);
1276
1277         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1278 }
1279
1280 static void ath_vap_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1281                                A_UINT8 *data, a_int32_t datalen)
1282 {
1283         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1284         struct ieee80211vap_target *vap;
1285         a_uint8_t vap_index;
1286
1287         vap = (struct ieee80211vap_target *)data;
1288
1289         vap->iv_rtsthreshold    = adf_os_ntohs(vap->iv_rtsthreshold);
1290         vap->iv_opmode          = adf_os_ntohl(vap->iv_opmode);
1291
1292         vap_index = vap->iv_vapindex;
1293
1294         adf_os_assert(sc->sc_vap[vap_index].av_valid == 0);
1295
1296         adf_os_mem_copy(&(sc->sc_vap[vap_index].av_vap), vap,
1297                         VAP_TARGET_SIZE);
1298
1299         sc->sc_vap[vap_index].av_bcbuf = asf_tailq_first(&(sc->sc_bbuf));
1300         sc->sc_vap[vap_index].av_valid = 1;
1301
1302         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1303 }
1304
1305 static void ath_node_create_tgt(void *Context, A_UINT16 Command,
1306                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1307 {
1308         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1309         struct ieee80211_node_target *node;
1310         a_uint8_t vap_index;
1311         a_uint8_t node_index;
1312
1313         node = (struct ieee80211_node_target *)data;
1314
1315         node_index = node->ni_nodeindex;
1316
1317         node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1318         node->ni_flags = adf_os_ntohs(node->ni_flags);
1319         node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1320
1321         adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1322                         NODE_TARGET_SIZE);
1323
1324         vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1325         sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1326         if(sc->sc_sta[node_index].ni.ni_is_vapnode == 1)
1327                 sc->sc_vap[vap_index].av_vap.iv_nodeindex = node_index;
1328
1329         sc->sc_sta[node_index].an_valid = 1;
1330         sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1331         sc->sc_sta[node_index].ni.ni_iv16 = 0;
1332         sc->sc_sta[node_index].ni.ni_iv32 = 0;
1333
1334         owl_tgt_node_init(&sc->sc_sta[node_index]);
1335
1336         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1337 }
1338
1339 static void ath_node_cleanup_tgt(void *Context, A_UINT16 Command,
1340                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1341 {
1342         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1343         a_uint8_t node_index;
1344         a_uint8_t *nodedata;
1345
1346         nodedata = (a_uint8_t *)data;
1347         node_index = *nodedata;
1348         sc->sc_sta[node_index].an_valid = 0;
1349
1350         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1351 }
1352
1353 static void ath_node_update_tgt(void *Context, A_UINT16 Command,
1354                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1355 {
1356         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1357         struct ieee80211_node_target *node;
1358         a_uint8_t vap_index;
1359         a_uint8_t node_index;
1360
1361         node = (struct ieee80211_node_target *)data;
1362
1363         node_index = node->ni_nodeindex;
1364
1365         node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1366         node->ni_flags = adf_os_ntohs(node->ni_flags);
1367         node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1368
1369         adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1370                         NODE_TARGET_SIZE);
1371
1372         vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1373         sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1374
1375         sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1376         sc->sc_sta[node_index].ni.ni_iv16 = 0;
1377         sc->sc_sta[node_index].ni.ni_iv32 = 0;
1378
1379         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1380 }
1381
1382 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
1383                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1384 {
1385         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1386         struct ath_hal *ah = sc->sc_ah;
1387         a_uint32_t addr;
1388         a_uint32_t val[32];
1389         int i;
1390
1391         for (i = 0; i < datalen; i += sizeof(a_int32_t)) {
1392                 addr = *(a_uint32_t *)(data + i);
1393                 addr = adf_os_ntohl(addr);
1394
1395                 if ((addr & 0xffffe000) == 0x2000) {
1396                         /* SEEPROM */
1397                         ath_hal_reg_read_target(ah, addr);
1398                         if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) {
1399                                 adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
1400                         }
1401                         val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
1402                 } else if (addr > 0xffff) {
1403                         val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr;
1404                 } else
1405                         val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr);
1406
1407                 val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]);
1408         }
1409
1410         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
1411 }
1412
1413 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
1414                                   A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1415 {
1416         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1417         struct ath_hal *ah = sc->sc_ah;
1418         int i;
1419         struct registerWrite {
1420                 a_uint32_t reg;
1421                 a_uint32_t val;
1422         }*t;
1423
1424         for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
1425                 t = (struct registerWrite *)(data+i);
1426
1427                 if( t->reg > 0xffff ) {
1428                         HAL_WORD_REG_WRITE(t->reg, t->val);
1429 #if defined(PROJECT_K2)
1430                         if( t->reg == 0x50040 ) {
1431                                 static uint8_t flg=0;
1432
1433                                 if( flg == 0 ) {
1434                                         A_CLOCK_INIT(117);
1435                                         A_UART_HWINIT(117*1000*1000, 19200);
1436                                         flg = 1;
1437                                 }
1438                         }
1439 #endif
1440                 } else {
1441 #if defined(PROJECT_K2)
1442                         if( t->reg == 0x7014 ) {
1443                                 static uint8_t resetPLL = 0;
1444
1445                                 if( resetPLL == 0 ) {
1446                                         /* here we write to core register */
1447                                         HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
1448                                         /* and here to mac register */
1449                                         ath_hal_reg_write_target(ah, 0x786c,
1450                                                  ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
1451                                         ath_hal_reg_write_target(ah, 0x786c,
1452                                                  ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
1453
1454                                         HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
1455                                         resetPLL = 1;
1456                                 }
1457                         }
1458 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
1459                         if( t->reg == 0x7014 ){
1460                                 static uint8_t resetPLL = 0;
1461
1462                                 if( resetPLL == 0 ) {
1463                                         ath_hal_reg_write_target(ah, 0x7890,
1464                                                  ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
1465                                         ath_hal_reg_write_target(ah, 0x7890,
1466                                                  ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
1467                                         resetPLL = 1;
1468                                 }
1469                         }
1470 #endif
1471                         ath_hal_reg_write_target(ah,t->reg,t->val);
1472                 }
1473         }
1474
1475         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1476 }
1477
1478 static void ath_vap_delete_tgt(void *Context, A_UINT16 Command,
1479                                A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1480 {
1481         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1482         a_uint8_t vap_index;
1483
1484         vap_index = *(a_uint8_t *)data;
1485
1486         sc->sc_vap[vap_index].av_valid = 0;
1487         sc->sc_vap[vap_index].av_bcbuf = NULL;
1488         ath_node_vdelete_tgt(sc, vap_index);
1489         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1490 }
1491
1492 static void ath_disable_intr_tgt(void *Context, A_UINT16 Command,
1493                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1494 {
1495         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1496         struct ath_hal *ah = sc->sc_ah;
1497
1498         ah->ah_setInterrupts(ah, 0);
1499         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1500 }
1501
1502 static void ath_flushrecv_tgt(void *Context, A_UINT16 Command,
1503                               A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1504 {
1505         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1506         struct ath_rx_buf *bf;
1507
1508         asf_tailq_foreach(bf, &sc->sc_rxbuf, bf_list)
1509                 if (bf->bf_skb != NULL) {
1510                         adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap,
1511                                        ADF_OS_DMA_FROM_DEVICE);
1512                         ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead));
1513                         bf->bf_skb = NULL;
1514                 }
1515
1516         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1517 }
1518
1519 static void ath_tx_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1520                                 A_UINT8 *data, a_int32_t datalen)
1521 {
1522         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1523         a_uint32_t q = *(a_uint32_t *)data;
1524         struct ath_txq *txq = NULL;
1525
1526         q = adf_os_ntohl(q);
1527         txq = ATH_TXQ(sc, q);
1528
1529         ath_tx_draintxq(sc, txq);
1530         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1531 }
1532
1533 static void ath_draintxq_tgt(void *Context, A_UINT16 Command,
1534                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1535 {
1536         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1537         HAL_BOOL b = (HAL_BOOL) *(a_int32_t *)data;
1538
1539         ath_draintxq(Context, b);
1540         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1541 }
1542
1543 static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command,
1544                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1545 {
1546         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1547         struct ath_hal *ah = sc->sc_ah;
1548
1549         ah->ah_abortTxDma(sc->sc_ah);
1550         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1551 }
1552
1553 static void ath_aborttxq_tgt(void *Context, A_UINT16 Command,
1554                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1555 {
1556
1557         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1558         a_uint16_t i;
1559
1560         for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
1561                 if (ATH_TXQ_SETUP(sc, i))
1562                         ath_tx_draintxq(sc, ATH_TXQ(sc,i));
1563         }
1564
1565         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1566 }
1567
1568 static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command,
1569                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1570 {
1571         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1572         struct ath_hal *ah = sc->sc_ah;
1573         a_uint32_t q;
1574
1575         if (data)
1576                 q = *(a_uint32_t *)data;
1577
1578         q = adf_os_ntohl(q);
1579         ah->ah_stopTxDma(ah, q);
1580         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1581 }
1582
1583 static void ath_startrecv_tgt(void *Context, A_UINT16 Command,
1584                               A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1585 {
1586
1587         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1588
1589         ath_startrecv(sc);
1590         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1591 }
1592
1593 static void ath_stoprecv_tgt(void *Context, A_UINT16 Command,
1594                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1595 {
1596         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1597         struct ath_hal *ah = sc->sc_ah;
1598
1599         ah->ah_stopPcuReceive(ah);
1600         ah->ah_setRxFilter(ah, 0);
1601         ah->ah_stopDmaReceive(ah);
1602
1603         sc->sc_rxlink = NULL;
1604         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1605 }
1606
1607 static void ath_setcurmode_tgt(void *Context, A_UINT16 Command,
1608                                A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1609 {
1610         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1611         a_uint16_t mode;
1612
1613         mode= *((a_uint16_t *)data);
1614         mode = adf_os_ntohs(mode);
1615
1616         ath_setcurmode(sc, mode);
1617
1618         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1619 }
1620
1621 static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1622                                  A_UINT8 *data, a_int32_t datalen)
1623 {
1624         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1625         struct ath_hal *ah = sc->sc_ah;
1626
1627         ath_desc_free(sc);
1628         ah->ah_detach(ah);
1629         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1630         adf_os_mem_free(sc);
1631 }
1632
1633 static void handle_echo_command(void *pContext, A_UINT16 Command,
1634                                 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1635 {
1636         wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length);
1637 }
1638
1639 static void handle_rc_state_change_cmd(void *Context, A_UINT16 Command,
1640                                        A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1641
1642 {
1643         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1644         struct wmi_rc_state_change_cmd *wmi_data = (struct wmi_rc_state_change_cmd *)buffer;
1645
1646         a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1647
1648         ath_rate_newstate(sc, &sc->sc_vap[wmi_data->vap_index].av_vap,
1649                           wmi_data->vap_state,
1650                           capflag,
1651                           &wmi_data->rs);
1652
1653         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1654 }
1655
1656 static void handle_rc_rate_update_cmd(void *Context, A_UINT16 Command,
1657                                       A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1658 {
1659         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1660         struct wmi_rc_rate_update_cmd *wmi_data = (struct wmi_rc_rate_update_cmd *)buffer;
1661
1662         a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1663
1664         ath_rate_node_update(sc, &sc->sc_sta[wmi_data->node_index],
1665                              wmi_data->isNew,
1666                              capflag,
1667                              &wmi_data->rs);
1668
1669         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1670 }
1671
1672 static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command,
1673                                      A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1674 {
1675         adf_os_assert(0);
1676 }
1677
1678 static void ath_rc_mask_tgt(void *Context, A_UINT16 Command,
1679                             A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1680 {
1681         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1682         struct wmi_rc_rate_mask_cmd *wmi_data = (struct wmi_rc_rate_mask_cmd *)buffer;
1683         int idx, band, i;
1684
1685         idx = wmi_data->vap_index;
1686         band = wmi_data->band;
1687
1688         sc->sc_vap[idx].av_rate_mask[band] = adf_os_ntohl(wmi_data->mask);
1689
1690         if (sc->sc_vap[idx].av_rate_mask[band]) {
1691                 for (i = 0; i < RATE_TABLE_SIZE; i++) {
1692                         if ((1 << i) & sc->sc_vap[idx].av_rate_mask[band]) {
1693                                 sc->sc_vap[idx].av_minrateidx[band] = i;
1694                                 break;
1695                         }
1696                 }
1697         } else {
1698                 sc->sc_vap[idx].av_minrateidx[band] = 0;
1699         }
1700
1701         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1702 }
1703
1704 static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] =
1705 {
1706         {handle_echo_command,         WMI_ECHO_CMDID,               0},
1707         {dispatch_magpie_sys_cmds,    WMI_ACCESS_MEMORY_CMDID,      0},
1708         {ath_get_tgt_version,         WMI_GET_FW_VERSION,           0},
1709         {ath_disable_intr_tgt,        WMI_DISABLE_INTR_CMDID,       0},
1710         {ath_enable_intr_tgt,         WMI_ENABLE_INTR_CMDID,        0},
1711         {ath_init_tgt,                WMI_ATH_INIT_CMDID,           0},
1712         {ath_aborttxq_tgt,            WMI_ABORT_TXQ_CMDID,          0},
1713         {ath_stop_tx_dma_tgt,         WMI_STOP_TX_DMA_CMDID,        0},
1714         {ath_aborttx_dma_tgt,         WMI_ABORT_TX_DMA_CMDID,       0},
1715         {ath_tx_draintxq_tgt,         WMI_DRAIN_TXQ_CMDID,          0},
1716         {ath_draintxq_tgt,            WMI_DRAIN_TXQ_ALL_CMDID,      0},
1717         {ath_startrecv_tgt,           WMI_START_RECV_CMDID,         0},
1718         {ath_stoprecv_tgt,            WMI_STOP_RECV_CMDID,          0},
1719         {ath_flushrecv_tgt,           WMI_FLUSH_RECV_CMDID,         0},
1720         {ath_setcurmode_tgt,          WMI_SET_MODE_CMDID,           0},
1721         {ath_node_create_tgt,         WMI_NODE_CREATE_CMDID,        0},
1722         {ath_node_cleanup_tgt,        WMI_NODE_REMOVE_CMDID,        0},
1723         {ath_vap_delete_tgt,          WMI_VAP_REMOVE_CMDID,         0},
1724         {ath_vap_create_tgt,          WMI_VAP_CREATE_CMDID,         0},
1725         {ath_hal_reg_read_tgt,        WMI_REG_READ_CMDID,           0},
1726         {ath_hal_reg_write_tgt,       WMI_REG_WRITE_CMDID,          0},
1727         {handle_rc_state_change_cmd,  WMI_RC_STATE_CHANGE_CMDID,    0},
1728         {handle_rc_rate_update_cmd,   WMI_RC_RATE_UPDATE_CMDID,     0},
1729         {ath_ic_update_tgt,           WMI_TARGET_IC_UPDATE_CMDID,   0},
1730         {ath_enable_aggr_tgt,         WMI_TX_AGGR_ENABLE_CMDID,     0},
1731         {ath_detach_tgt,              WMI_TGT_DETACH_CMDID,         0},
1732         {ath_node_update_tgt,         WMI_NODE_UPDATE_CMDID,        0},
1733         {ath_int_stats_tgt,           WMI_INT_STATS_CMDID,          0},
1734         {ath_tx_stats_tgt,            WMI_TX_STATS_CMDID,           0},
1735         {ath_rx_stats_tgt,            WMI_RX_STATS_CMDID,           0},
1736         {ath_rc_mask_tgt,             WMI_BITRATE_MASK_CMDID,       0},
1737 };
1738
1739 /*****************/
1740 /* Init / Deinit */
1741 /*****************/
1742
1743 static void htc_setup_comp(void)
1744 {
1745 }
1746
1747 static A_UINT8 tgt_ServiceConnect(HTC_SERVICE *pService,
1748                                   HTC_ENDPOINT_ID eid,
1749                                   A_UINT8 *pDataIn,
1750                                   a_int32_t LengthIn,
1751                                   A_UINT8 *pDataOut,
1752                                   a_int32_t *pLengthOut)
1753 {
1754         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)pService->ServiceCtx;
1755
1756         switch(pService->ServiceID) {
1757         case WMI_CONTROL_SVC:
1758                 sc->wmi_command_ep= eid;
1759                 break;
1760         case WMI_BEACON_SVC:
1761                 sc->beacon_ep= eid;
1762                 break;
1763         case WMI_CAB_SVC:
1764                 sc->cab_ep= eid;
1765                 break;
1766         case WMI_UAPSD_SVC:
1767                 sc->uapsd_ep= eid;
1768                 break;
1769         case WMI_MGMT_SVC:
1770                 sc->mgmt_ep= eid;
1771                 break;
1772         case WMI_DATA_VO_SVC:
1773                 sc->data_VO_ep = eid;
1774                 break;
1775         case WMI_DATA_VI_SVC:
1776                 sc->data_VI_ep = eid;
1777                 break;
1778         case WMI_DATA_BE_SVC:
1779                 sc->data_BE_ep = eid;
1780                 break;
1781         case WMI_DATA_BK_SVC:
1782                 sc->data_BK_ep = eid;
1783                 break;
1784         default:
1785                 adf_os_assert(0);
1786         }
1787
1788         return HTC_SERVICE_SUCCESS;
1789 }
1790
1791 static void tgt_reg_service(struct ath_softc_tgt *sc, HTC_SERVICE *svc,
1792                             int svcId, HTC_SERVICE_ProcessRecvMsg recvMsg)
1793 {
1794         svc->ProcessRecvMsg = recvMsg;
1795         svc->ProcessSendBufferComplete = tgt_HTCSendCompleteHandler;
1796         svc->ProcessConnect = tgt_ServiceConnect;
1797         svc->MaxSvcMsgSize = 1600;
1798         svc->TrailerSpcCheckLimit = 0;
1799         svc->ServiceID = svcId;
1800         svc->ServiceCtx = sc;
1801         HTC_RegisterService(sc->tgt_htc_handle, svc);
1802 }
1803
1804 static void tgt_hif_htc_wmi_init(struct ath_softc_tgt *sc)
1805 {
1806         HTC_CONFIG htc_conf;
1807         WMI_SVC_CONFIG wmiConfig;
1808         WMI_DISPATCH_TABLE *Magpie_Sys_Commands_Tbl;
1809
1810         /* Init dynamic buf pool */
1811         sc->pool_handle = BUF_Pool_init(sc->sc_hdl);
1812
1813         /* Init target-side HIF */
1814         sc->tgt_hif_handle = HIF_init(0);
1815
1816         /* Init target-side HTC */
1817         htc_conf.HIFHandle = sc->tgt_hif_handle;
1818         htc_conf.CreditSize = 320;
1819         htc_conf.CreditNumber = ATH_TXBUF;
1820         htc_conf.OSHandle = sc->sc_hdl;
1821         htc_conf.PoolHandle = sc->pool_handle;
1822         sc->tgt_htc_handle = HTC_init(htc_setup_comp, &htc_conf);
1823 #if defined(PROJECT_MAGPIE)
1824         init_htc_handle = sc->tgt_htc_handle;
1825 #endif
1826
1827         tgt_reg_service(sc, &sc->htc_beacon_service, WMI_BEACON_SVC, tgt_HTCRecv_beaconhandler);
1828         tgt_reg_service(sc, &sc->htc_cab_service, WMI_CAB_SVC, tgt_HTCRecv_cabhandler);
1829         tgt_reg_service(sc, &sc->htc_uapsd_service, WMI_UAPSD_SVC, tgt_HTCRecv_uapsdhandler);
1830         tgt_reg_service(sc, &sc->htc_mgmt_service, WMI_MGMT_SVC, tgt_HTCRecv_mgmthandler);
1831         tgt_reg_service(sc, &sc->htc_data_BE_service, WMI_DATA_BE_SVC, tgt_HTCRecvMessageHandler);
1832         tgt_reg_service(sc, &sc->htc_data_BK_service, WMI_DATA_BK_SVC, tgt_HTCRecvMessageHandler);
1833         tgt_reg_service(sc, &sc->htc_data_VI_service, WMI_DATA_VI_SVC, tgt_HTCRecvMessageHandler);
1834         tgt_reg_service(sc, &sc->htc_data_VO_service, WMI_DATA_VO_SVC, tgt_HTCRecvMessageHandler);
1835
1836         /* Init target-side WMI */
1837         Magpie_Sys_Commands_Tbl = (WMI_DISPATCH_TABLE *)adf_os_mem_alloc(sizeof(WMI_DISPATCH_TABLE));
1838         adf_os_mem_zero(Magpie_Sys_Commands_Tbl, sizeof(WMI_DISPATCH_TABLE));
1839         Magpie_Sys_Commands_Tbl->NumberOfEntries = WMI_DISPATCH_ENTRY_COUNT(Magpie_Sys_DispatchEntries);
1840         Magpie_Sys_Commands_Tbl->pTable = Magpie_Sys_DispatchEntries;
1841
1842         adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG));
1843         wmiConfig.HtcHandle = sc->tgt_htc_handle;
1844         wmiConfig.PoolHandle = sc->pool_handle;
1845         wmiConfig.MaxCmdReplyEvts = ATH_WMI_MAX_CMD_REPLY;
1846         wmiConfig.MaxEventEvts = ATH_WMI_MAX_EVENTS;
1847
1848         sc->tgt_wmi_handle = WMI_Init(&wmiConfig);
1849         Magpie_Sys_Commands_Tbl->pContext = sc;
1850         WMI_RegisterDispatchTable(sc->tgt_wmi_handle, Magpie_Sys_Commands_Tbl);
1851
1852         HTC_NotifyTargetInserted(sc->tgt_htc_handle);
1853
1854         /* Start HTC messages exchange */
1855         HTC_Ready(sc->tgt_htc_handle);
1856 }
1857
1858 a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_device_t osdev)
1859 {
1860         struct ath_hal *ah;
1861         HAL_STATUS status;
1862         a_int32_t error = 0, i, flags = 0;
1863         a_uint8_t csz;
1864
1865         adf_os_pci_config_read8(osdev, ATH_PCI_CACHE_LINE_SIZE, &csz);
1866
1867         if (csz == 0)
1868                 csz = 16;
1869         sc->sc_cachelsz = csz << 2;
1870
1871         sc->sc_dev = osdev;
1872         sc->sc_hdl = osdev;
1873
1874         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_rxtq, ath_tgt_rx_tasklet, sc);
1875         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_txtq, owl_tgt_tx_tasklet, sc);
1876         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_bmisstq, ath_bmiss_tasklet, sc);
1877         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_fataltq, ath_fatal_tasklet, sc);
1878
1879         flags |= AH_USE_EEPROM;
1880         ah = _ath_hal_attach_tgt(devid, sc, sc->sc_dev, flags, &status);
1881         if (ah == NULL) {
1882                 error = ENXIO;
1883                 goto bad;
1884         }
1885         sc->sc_ah = ah;
1886
1887         tgt_hif_htc_wmi_init(sc);
1888
1889         sc->sc_bhalq = HAL_NUM_TX_QUEUES - 1;
1890
1891         ath_rate_setup(sc, IEEE80211_MODE_11NA);
1892         ath_rate_setup(sc, IEEE80211_MODE_11NG);
1893
1894         sc->sc_rc = ath_rate_attach(sc);
1895         if (sc->sc_rc == NULL) {
1896                 error = EIO;
1897                 goto bad2;
1898         }
1899
1900         for (i=0; i < TARGET_NODE_MAX; i++) {
1901                 sc->sc_sta[i].an_rcnode = adf_os_mem_alloc(sc->sc_rc->arc_space);
1902         }
1903
1904         error = ath_desc_alloc(sc);
1905         if (error != 0) {
1906                 goto bad;
1907         }
1908
1909         BUF_Pool_create_pool(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ath_numrxdescs, 1664);
1910
1911         ath_tgt_txq_setup(sc);
1912         sc->sc_imask =0;
1913         ah->ah_setInterrupts(ah, 0);
1914
1915         return 0;
1916 bad:
1917 bad2:
1918         ath_desc_free(sc);
1919         if (ah)
1920                 ah->ah_detach(ah);
1921 }
1922
1923 static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)
1924 {
1925         HTC_NotifyTargetDetached(sc->tgt_htc_handle);
1926
1927         WMI_Shutdown(sc->tgt_wmi_handle);
1928         HTC_Shutdown(sc->tgt_htc_handle);
1929         HIF_shutdown(sc->tgt_hif_handle);
1930         BUF_Pool_shutdown(sc->pool_handle);
1931 }
1932
1933 a_int32_t ath_detach(struct ath_softc_tgt *sc)
1934 {
1935         tgt_hif_htc_wmi_shutdown(sc);
1936 }