target_firmware/wlan/if_ath.c

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <adf_os_types.h>
  37 #include <adf_os_pci.h>
  38 #include <adf_os_dma.h>
  39 #include <adf_os_timer.h>
  40 #include <adf_os_lock.h>
  41 #include <adf_os_io.h>
  42 #include <adf_os_mem.h>
  43 #include <adf_os_util.h>
  44 #include <adf_os_stdtypes.h>
  45 #include <adf_os_defer.h>
  46 #include <adf_os_atomic.h>
  47 #include <adf_nbuf.h>
  48 #include <adf_net.h>
  49 #include <adf_net_wcmd.h>
  50 #include <adf_os_irq.h>
  51
  52 #include <if_ath_pci.h>
  53 #include "if_llc.h"
  54 #include "ieee80211_var.h"
  55 #include "if_athrate.h"
  56 #include "if_athvar.h"
  57 #include "ah_desc.h"
  58 #include "ah.h"
  59
  60 static a_int32_t ath_numrxbufs = -1;
  61 static a_int32_t ath_numrxdescs = -1;
  62
  63 #if defined(PROJECT_MAGPIE)
  64 uint32_t *init_htc_handle = 0;
  65 #endif
  66
  67 #define RX_ENDPOINT_ID 3
  68 #define ATH_CABQ_HANDLING_THRESHOLD 9000
  69 #define UAPSDQ_NUM   9
  70 #define CABQ_NUM     8
  71
  72 void owl_tgt_tx_tasklet(TQUEUE_ARG data);
  73 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
  74 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
  75 extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
  76 extern void  ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
  77 extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
  78 extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,  owl_txq_state_t txqstate);
  79 void owl_tgt_node_init(struct ath_node_target * an);
  80 void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
  81 void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
  82
  83 /*************/
  84 /* Utilities */
  85 /*************/
  86
  87 #undef adf_os_cpu_to_le16
  88
  89 static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
  90 {
  91         return ((((x) & 0xff00) >> 8) |   (((x) & 0x00ff) << 8));
  92 }
  93
  94 /*
  95  * Extend a 32 bit TSF to 64 bit, taking wrapping into account.
  96  */
  97 static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
  98 {
  99         struct ath_hal *ah = sc->sc_ah;
 100         u_int64_t tsf;
 101         u_int32_t tsf_low;
 102         u_int64_t tsf64;
 103
 104         tsf = ah->ah_getTsf64(ah);
 105         tsf_low = tsf & 0xffffffff;
 106         tsf64 = (tsf & ~0xffffffffULL) | rstamp;
 107
 108         if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000))
 109                 tsf64 -= 0x100000000ULL;
 110
 111         if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000))
 112                 tsf64 += 0x100000000ULL;
 113
 114         return tsf64;
 115 }
 116
 117 static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode)
 118 {
 119         struct ath_hal *ah = sc->sc_ah;
 120         const HAL_RATE_TABLE *rt;
 121
 122         switch (mode) {
 123         case IEEE80211_MODE_11NA:
 124                 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NA);
 125                 break;
 126         case IEEE80211_MODE_11NG:
 127                 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NG);
 128                 break;
 129         default:
 130                 return 0;
 131         }
 132         rt = sc->sc_rates[mode];
 133         if (rt == NULL)
 134                 return 0;
 135
 136         return 1;
 137 }
 138
 139 static void ath_setcurmode(struct ath_softc_tgt *sc,
 140                            enum ieee80211_phymode mode)
 141 {
 142         const HAL_RATE_TABLE *rt;
 143         a_int32_t i;
 144
 145         adf_os_mem_set(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
 146
 147         rt = sc->sc_rates[mode];
 148         adf_os_assert(rt != NULL);
 149
 150         for (i = 0; i < rt->rateCount; i++) {
 151                 sc->sc_rixmap[rt->info[i].rateCode] = i;
 152         }
 153
 154         sc->sc_currates = rt;
 155         sc->sc_curmode = mode;
 156         sc->sc_protrix = ((mode == IEEE80211_MODE_11NG) ? 3 : 0);
 157
 158 }
 159
 160 void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
 161                void *buffer, a_int32_t Length)
 162 {
 163         adf_nbuf_t netbuf = ADF_NBUF_NULL;
 164         a_uint8_t *pData;
 165
 166         netbuf = WMI_AllocEvent(handle, WMI_EVT_CLASS_CMD_EVENT,
 167                                 sizeof(WMI_CMD_HDR) + Length);
 168
 169         if (netbuf == ADF_NBUF_NULL) {
 170                 adf_os_print("Buf null\n");
 171                 return;
 172         }
 173
 174         if (buffer != NULL && Length != 0 && Length < WMI_SVC_MAX_BUFFERED_EVENT_SIZE) {
 175                 pData = adf_nbuf_put_tail(netbuf, Length);
 176                 adf_os_mem_copy(pData, buffer, Length);
 177         }
 178
 179         WMI_SendEvent(handle, netbuf, evt_id, 0, Length);
 180 }
 181
 182 void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo,
 183                  void *buffer, a_int32_t Length)
 184 {
 185         adf_nbuf_t netbuf = ADF_NBUF_NULL;
 186         A_UINT8 *pData;
 187
 188         netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY,
 189                                 sizeof(WMI_CMD_HDR) + Length);
 190
 191         if (netbuf == ADF_NBUF_NULL) {
 192                 adf_os_assert(0);
 193                 return;
 194         }
 195
 196         if (Length != 0 && buffer != NULL) {
 197                 pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length);
 198                 adf_os_mem_copy(pData, buffer, Length);
 199         }
 200
 201         WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length);
 202 }
 203
 204 static void ath_node_vdelete_tgt(struct ath_softc_tgt *sc, a_uint8_t vap_index)
 205 {
 206         a_int32_t i;
 207
 208         for (i = 0; i < TARGET_NODE_MAX; i++) {
 209                 if(sc->sc_sta[i].ni.ni_vapindex == vap_index)
 210                         sc->sc_sta[i].an_valid = 0;
 211         }
 212 }
 213
 214 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp)
 215 {
 216         if (sc->sc_curmode == IEEE80211_MODE_11NG)
 217                 return avp->av_minrateidx[0];
 218         else if (sc->sc_curmode == IEEE80211_MODE_11NA)
 219                 return avp->av_minrateidx[1];
 220
 221         return 0;
 222 }
 223
 224 /******/
 225 /* RX */
 226 /******/
 227
 228 static adf_nbuf_t ath_alloc_skb_align(struct ath_softc_tgt *sc,
 229                                       a_uint32_t size, a_uint32_t align)
 230 {
 231         adf_nbuf_t skb;
 232
 233         skb = BUF_Pool_alloc_buf_align(sc->pool_handle, POOL_ID_WLAN_RX_BUF,
 234                                        RX_HEADER_SPACE, align);
 235         return skb;
 236 }
 237
 238 static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *ds)
 239 {
 240         struct ath_hal *ah = sc->sc_ah;
 241         struct ath_rx_desc *ds_held;
 242         a_uint8_t *anbdata;
 243         a_uint32_t anblen;
 244
 245         if (!sc->sc_rxdesc_held) {
 246                 sc->sc_rxdesc_held = ds;
 247                 return 0;
 248         }
 249
 250         ds_held = sc->sc_rxdesc_held;
 251         sc->sc_rxdesc_held = ds;
 252         ds = ds_held;
 253
 254         if (ds->ds_nbuf == ADF_NBUF_NULL) {
 255                 ds->ds_nbuf = ath_alloc_skb_align(sc, sc->sc_rxbufsize, sc->sc_cachelsz);
 256                 if (ds->ds_nbuf == ADF_NBUF_NULL) {
 257                         sc->sc_rxdesc_held = ds;
 258                         sc->sc_rx_stats.ast_rx_nobuf++;
 259                         return ENOMEM;
 260                 }
 261                 adf_nbuf_map(sc->sc_dev, ds->ds_dmap, ds->ds_nbuf, ADF_OS_DMA_FROM_DEVICE);
 262                 adf_nbuf_dmamap_info(ds->ds_dmap, &ds->ds_dmap_info);
 263                 ds->ds_data = ds->ds_dmap_info.dma_segs[0].paddr;
 264         }
 265
 266         ds->ds_link = 0;
 267         adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
 268
 269         ath_hal_setuprxdesc(ah, ds,
 270                             adf_nbuf_tailroom(ds->ds_nbuf),
 271                             0);
 272
 273         if (sc->sc_rxlink == NULL) {
 274                 ah->ah_setRxDP(ah, ds->ds_daddr);
 275         }
 276         else {
 277                 *sc->sc_rxlink = ds->ds_daddr;
 278         }
 279         sc->sc_rxlink = &ds->ds_link;
 280         ah->ah_enableReceive(ah);
 281
 282         return 0;
 283 }
 284
 285 static void ath_rx_complete(struct ath_softc_tgt *sc, adf_nbuf_t buf)
 286 {
 287         struct ath_rx_desc *ds;
 288         adf_nbuf_t buf_tmp;
 289         adf_nbuf_queue_t nbuf_head;
 290
 291         adf_nbuf_split_to_frag(buf, &nbuf_head);
 292         ds = asf_tailq_first(&sc->sc_rxdesc_idle);
 293
 294         while (ds) {
 295                 struct ath_rx_desc *ds_tmp;
 296                 buf_tmp = adf_nbuf_queue_remove(&nbuf_head);
 297
 298                 if (buf_tmp == NULL) {
 299                         break;
 300                 }
 301
 302                 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, buf_tmp);
 303
 304                 ds_tmp = ds;
 305                 ds = asf_tailq_next(ds, ds_list);
 306
 307                 ath_rxdesc_init(sc, ds_tmp);
 308
 309                 asf_tailq_remove(&sc->sc_rxdesc_idle, ds_tmp, ds_list);
 310                 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_tmp, ds_list);
 311         }
 312 }
 313
 314 static void tgt_HTCSendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t buf, void *ServiceCtx)
 315 {
 316         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 317
 318         if (Endpt == RX_ENDPOINT_ID) {
 319                 sc->sc_rx_stats.ast_rx_done++;
 320                 ath_rx_complete(sc, buf);
 321         }
 322 }
 323
 324 static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc)
 325 {
 326         struct ath_hal *ah = sc->sc_ah;
 327         struct ath_rx_buf *bf = NULL;
 328         struct ath_rx_desc *ds, *ds_head, *ds_tail, *ds_tmp;
 329         a_int32_t retval;
 330         a_uint32_t cnt = 0;
 331         a_uint16_t frame_len = 0;
 332         a_uint64_t tsf;
 333
 334 #define PA2DESC(_sc, _pa)                                               \
 335         ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc +         \
 336                              ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
 337
 338         tsf = ah->ah_getTsf64(ah);
 339         bf = asf_tailq_first(&sc->sc_rxbuf);
 340
 341         ds = asf_tailq_first(&sc->sc_rxdesc);
 342         ds_head = ds;
 343
 344         while(ds) {
 345                 ++cnt;
 346
 347                 if (cnt == ath_numrxbufs - 1) {
 348                         adf_os_print("VERY LONG PACKET!!!!!\n");
 349                         ds_tail = ds;
 350                         ds_tmp = ds_head;
 351                         while (ds_tmp) {
 352                                 struct ath_rx_desc *ds_rmv;
 353                                 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
 354                                 ds_rmv = ds_tmp;
 355                                 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
 356
 357                                 if (ds_tmp == NULL) {
 358                                         adf_os_print("ds_tmp is NULL\n");
 359                                         adf_os_assert(0);
 360                                 }
 361
 362                                 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ds_rmv->ds_nbuf);
 363                                 ds_rmv->ds_nbuf = ADF_NBUF_NULL;
 364
 365                                 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
 366                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 367                                         asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
 368                                 }
 369                                 else {
 370                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 371                                         asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
 372                                 }
 373
 374                                 if (ds_rmv == ds_tail) {
 375                                         break;
 376                                 }
 377                         }
 378                         break;
 379                 }
 380
 381                 if (ds->ds_link == 0) {
 382                         break;
 383                 }
 384
 385                 if (bf->bf_status & ATH_BUFSTATUS_DONE) {
 386                         continue;
 387                 }
 388
 389                 retval = ath_hal_rxprocdescfast(ah, ds, ds->ds_daddr,
 390                                                 PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
 391                 if (HAL_EINPROGRESS == retval) {
 392                         break;
 393                 }
 394
 395                 if (adf_nbuf_len(ds->ds_nbuf) == 0) {
 396                         adf_nbuf_put_tail(ds->ds_nbuf, bf->bf_rx_status.rs_datalen);
 397                 }
 398
 399                 frame_len += bf->bf_rx_status.rs_datalen;
 400
 401                 if (bf->bf_rx_status.rs_more == 0) {
 402                         adf_nbuf_queue_t nbuf_head;
 403                         adf_nbuf_queue_init(&nbuf_head);
 404
 405                         cnt = 0;
 406
 407                         ds_tail = ds;
 408                         ds = asf_tailq_next(ds, ds_list);
 409
 410                         ds_tmp = ds_head;
 411                         ds_head = asf_tailq_next(ds_tail, ds_list);
 412
 413                         while (ds_tmp) {
 414                                 struct ath_rx_desc *ds_rmv;
 415
 416                                 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
 417                                 adf_nbuf_queue_add(&nbuf_head, ds_tmp->ds_nbuf);
 418                                 ds_tmp->ds_nbuf = ADF_NBUF_NULL;
 419
 420                                 ds_rmv = ds_tmp;
 421                                 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
 422                                 if (ds_tmp == NULL) {
 423                                         adf_os_assert(0);
 424                                 }
 425
 426                                 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
 427                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 428                                         asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
 429                                 }  else {
 430                                         asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
 431                                         asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
 432                                 }
 433
 434                                 if (ds_rmv == ds_tail) {
 435                                         break;
 436                                 }
 437                         }
 438
 439
 440                         bf->bf_rx_status.rs_datalen = frame_len;
 441                         frame_len = 0;
 442
 443                         bf->bf_skb = adf_nbuf_create_frm_frag(&nbuf_head);
 444
 445                         bf->bf_status |= ATH_BUFSTATUS_DONE;
 446
 447                         bf = (struct ath_rx_buf *)asf_tailq_next(bf, bf_list);
 448                 }
 449                 else {
 450                         ds = asf_tailq_next(ds, ds_list);
 451                 }
 452         }
 453
 454 #undef PA2DESC
 455 }
 456
 457 static a_int32_t ath_startrecv(struct ath_softc_tgt *sc)
 458 {
 459         struct ath_hal *ah = sc->sc_ah;
 460         struct ath_rx_desc *ds;
 461
 462         sc->sc_rxbufsize = 1024+512+128;
 463         sc->sc_rxlink = NULL;
 464
 465         sc->sc_rxdesc_held = NULL;
 466
 467         asf_tailq_foreach(ds, &sc->sc_rxdesc, ds_list) {
 468                 a_int32_t error = ath_rxdesc_init(sc, ds);
 469                 if (error != 0) {
 470                         return error;
 471                 }
 472         }
 473
 474         ds = asf_tailq_first(&sc->sc_rxdesc);
 475         ah->ah_setRxDP(ah, ds->ds_daddr);
 476
 477         return 0;
 478 }
 479
 480 static void ath_tgt_rx_tasklet(TQUEUE_ARG data)
 481 {
 482         struct ath_softc_tgt *sc  = (struct ath_softc_tgt *)data;
 483         struct ath_rx_buf *bf = NULL;
 484         struct ath_hal *ah = sc->sc_ah;
 485         struct rx_frame_header *rxhdr;
 486         struct ath_rx_status *rxstats;
 487         adf_nbuf_t skb = ADF_NBUF_NULL;
 488
 489         do {
 490                 bf = asf_tailq_first(&sc->sc_rxbuf);
 491                 if (bf == NULL) {
 492                         break;
 493                 }
 494
 495                 if (!(bf->bf_status & ATH_BUFSTATUS_DONE)) {
 496                         break;
 497                 }
 498
 499                 skb = bf->bf_skb;
 500                 if (skb == NULL) {
 501                         continue;
 502                 }
 503
 504                 asf_tailq_remove(&sc->sc_rxbuf, bf, bf_list);
 505
 506                 bf->bf_skb = NULL;
 507
 508                 rxhdr = (struct rx_frame_header *)adf_nbuf_push_head(skb,
 509                                                      sizeof(struct rx_frame_header));
 510                 rxstats = (struct ath_rx_status *)(&rxhdr->rx_stats[0]);
 511                 adf_os_mem_copy(rxstats, &(bf->bf_rx_status),
 512                                 sizeof(struct ath_rx_status));
 513
 514                 rxstats->rs_tstamp = ath_extend_tsf(sc, (u_int32_t)rxstats->rs_tstamp);
 515
 516                 HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb);
 517                 sc->sc_rx_stats.ast_rx_send++;
 518
 519                 bf->bf_status &= ~ATH_BUFSTATUS_DONE;
 520                 asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list);
 521
 522         } while(1);
 523
 524         sc->sc_imask |= HAL_INT_RX;
 525         ath_hal_intrset(ah, sc->sc_imask);
 526 }
 527
 528 /*******************/
 529 /* Beacon Handling */
 530 /*******************/
 531
 532 /*
 533  * Setup the beacon frame for transmit.
 534  * FIXME: Short Preamble.
 535  */
 536 static void ath_beacon_setup(struct ath_softc_tgt *sc,
 537                              struct ath_tx_buf *bf,
 538                              struct ath_vap_target *avp)
 539 {
 540         adf_nbuf_t skb = bf->bf_skb;
 541         struct ath_hal *ah = sc->sc_ah;
 542         struct ath_tx_desc *ds;
 543         a_int32_t flags;
 544         const HAL_RATE_TABLE *rt;
 545         a_uint8_t rix, rate;
 546         HAL_11N_RATE_SERIES series[4] = {{ 0 }};
 547
 548         flags = HAL_TXDESC_NOACK;
 549
 550         ds = bf->bf_desc;
 551         ds->ds_link = 0;
 552         ds->ds_data = bf->bf_dmamap_info.dma_segs[0].paddr;
 553
 554         rix = ath_get_minrateidx(sc, avp);
 555         rt  = sc->sc_currates;
 556         rate = rt->info[rix].rateCode;
 557
 558         ath_hal_setuptxdesc(ah, ds
 559                             , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
 560                             , sizeof(struct ieee80211_frame)
 561                             , HAL_PKT_TYPE_BEACON
 562                             , MAX_RATE_POWER
 563                             , rate, 1
 564                             , HAL_TXKEYIX_INVALID
 565                             , 0
 566                             , flags
 567                             , 0
 568                             , 0
 569                             , 0
 570                             , 0
 571                             , ATH_COMP_PROC_NO_COMP_NO_CCS);
 572
 573         ath_hal_filltxdesc(ah, ds
 574                            , asf_roundup(adf_nbuf_len(skb), 4)
 575                            , AH_TRUE
 576                            , AH_TRUE
 577                            , ds);
 578
 579         series[0].Tries = 1;
 580         series[0].Rate = rate;
 581         series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
 582         series[0].RateFlags = 0;
 583         ath_hal_set11n_ratescenario(ah, ds, 0, 0, 0, series, 4, 0);
 584 }
 585
 586 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
 587                                 adf_nbuf_t nbuf, HTC_ENDPOINT_ID EndPt)
 588 {
 589         struct ath_hal *ah = sc->sc_ah;
 590         struct ath_tx_buf *bf;
 591         a_uint8_t vap_index, *anbdata;
 592         ath_beacon_hdr_t *bhdr;
 593         struct ieee80211vap_target  *vap;
 594         a_uint32_t anblen;
 595         struct ieee80211_frame *wh;
 596
 597         if (!bc_hdr) {
 598                 adf_nbuf_peek_header(nbuf, &anbdata, &anblen);
 599                 bhdr = (ath_beacon_hdr_t *)anbdata;
 600         } else {
 601                 adf_os_print("found bc_hdr! 0x%x\n", bc_hdr);
 602         }
 603
 604         vap_index = bhdr->vap_index;
 605         adf_os_assert(vap_index < TARGET_VAP_MAX);
 606         vap = &sc->sc_vap[vap_index].av_vap;
 607
 608         wh = (struct ieee80211_frame *)adf_nbuf_pull_head(nbuf,
 609                                                   sizeof(ath_beacon_hdr_t));
 610
 611         bf = sc->sc_vap[vap_index].av_bcbuf;
 612         adf_os_assert(bf);
 613         bf->bf_endpt = EndPt;
 614
 615         if (bf->bf_skb) {
 616                 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
 617                 adf_nbuf_push_head(bf->bf_skb, sizeof(ath_beacon_hdr_t));
 618                 ath_free_tx_skb(sc->tgt_htc_handle, bf->bf_endpt, bf->bf_skb);
 619         }
 620
 621         bf->bf_skb = nbuf;
 622
 623         adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, nbuf, ADF_OS_DMA_TO_DEVICE);
 624         adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info);
 625
 626         ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]);
 627         ah->ah_stopTxDma(ah, sc->sc_bhalq);
 628         ah->ah_setTxDP(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
 629         ah->ah_startTxDma(ah, sc->sc_bhalq);
 630 }
 631
 632 /******/
 633 /* TX */
 634 /******/
 635
 636 static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq)
 637 {
 638         struct ath_hal *ah = sc->sc_ah;
 639
 640         ah->ah_stopTxDma(ah, txq->axq_qnum);
 641 }
 642
 643 static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq)
 644 {
 645         owltgt_tx_processq(sc, txq, OWL_TXQ_STOPPED);
 646 }
 647
 648 static void ath_tx_draintxq(struct ath_softc_tgt *sc, struct ath_txq *txq)
 649 {
 650         owltgt_txq_drain(sc, txq);
 651 }
 652
 653 static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq)
 654 {
 655         struct ath_hal *ah = sc->sc_ah;
 656         a_uint16_t i;
 657         struct ath_txq *txq = NULL;
 658         struct ath_atx_tid *tid = NULL;
 659
 660         ath_tx_status_clear(sc);
 661         sc->sc_tx_draining = 1;
 662
 663         ah->ah_stopTxDma(ah, sc->sc_bhalq);
 664
 665         for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
 666                 if (ATH_TXQ_SETUP(sc, i))
 667                         ath_tx_stopdma(sc, ATH_TXQ(sc, i));
 668
 669         for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
 670                 if (ATH_TXQ_SETUP(sc, i)) {
 671                         owltgt_tx_processq(sc, ATH_TXQ(sc,i), OWL_TXQ_STOPPED);
 672
 673                         txq = ATH_TXQ(sc,i);
 674                         while (!asf_tailq_empty(&txq->axq_tidq)){
 675                                 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
 676                                 if(tid == NULL)
 677                                         break;
 678                                 tid->sched = AH_FALSE;
 679                                 ath_tgt_tid_drain(sc,tid);
 680                         }
 681                 }
 682
 683         sc->sc_tx_draining = 0;
 684 }
 685
 686 static void ath_tgt_txq_setup(struct ath_softc_tgt *sc)
 687 {
 688         a_int32_t qnum;
 689         struct ath_txq *txq;
 690
 691         sc->sc_txqsetup=0;
 692
 693         for (qnum=0;qnum<HAL_NUM_TX_QUEUES;qnum++) {
 694                 txq= &sc->sc_txq[qnum];
 695                 txq->axq_qnum = qnum;
 696                 txq->axq_link = NULL;
 697                 asf_tailq_init(&txq->axq_q);
 698                 txq->axq_depth = 0;
 699                 txq->axq_linkbuf = NULL;
 700                 asf_tailq_init(&txq->axq_tidq);
 701                 sc->sc_txqsetup |= 1<<qnum;
 702         }
 703
 704         sc->sc_uapsdq  = &sc->sc_txq[UAPSDQ_NUM];
 705         sc->sc_cabq    = &sc->sc_txq[CABQ_NUM];
 706
 707         sc->sc_ac2q[WME_AC_BE]  = &sc->sc_txq[0];
 708         sc->sc_ac2q[WME_AC_BK]  = &sc->sc_txq[1];
 709         sc->sc_ac2q[WME_AC_VI]  = &sc->sc_txq[2];
 710         sc->sc_ac2q[WME_AC_VO]  = &sc->sc_txq[3];
 711
 712         return;
 713 #undef N
 714 }
 715
 716 static void tgt_HTCRecv_beaconhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 717                                       adf_nbuf_t buf, void *ServiceCtx)
 718 {
 719         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 720
 721         ath_tgt_send_beacon(sc, hdr_buf, buf, EndPt);
 722 }
 723
 724 static void tgt_HTCRecv_uapsdhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 725                                      adf_nbuf_t buf, void *ServiceCtx)
 726 {
 727 }
 728
 729 static void tgt_HTCRecv_mgmthandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 730                                     adf_nbuf_t buf, void *ServiceCtx)
 731 {
 732         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 733
 734         ath_tgt_send_mgt(sc,hdr_buf,buf,EndPt);
 735 }
 736
 737 static void tgt_HTCRecvMessageHandler(HTC_ENDPOINT_ID EndPt,
 738                                       adf_nbuf_t hdr_buf, adf_nbuf_t buf,
 739                                       void *ServiceCtx)
 740 {
 741         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 742         struct ath_tx_buf *bf;
 743         a_uint8_t *data;
 744         a_uint32_t len;
 745         ath_data_hdr_t *dh;
 746         struct ath_node_target *an;
 747         struct ath_atx_tid *tid;
 748
 749         if (!hdr_buf) {
 750                 adf_nbuf_peek_header(buf, &data, &len);
 751                 adf_nbuf_pull_head(buf, sizeof(ath_data_hdr_t));
 752         } else {
 753                 adf_nbuf_peek_header(hdr_buf, &data, &len);
 754         }
 755
 756         adf_os_assert(len >= sizeof(ath_data_hdr_t));
 757         dh = (ath_data_hdr_t *)data;
 758
 759         an = &sc->sc_sta[dh->ni_index];
 760         tid = ATH_AN_2_TID(an, dh->tidno);
 761
 762         sc->sc_tx_stats.tx_tgt++;
 763
 764         bf = ath_tgt_tx_prepare(sc, buf, dh);
 765         if (!bf) {
 766                 ath_free_tx_skb(sc->tgt_htc_handle,EndPt,buf);
 767                 return;
 768         }
 769
 770         bf->bf_endpt = EndPt;
 771         bf->bf_cookie = dh->cookie;
 772
 773         if (tid->flag & TID_AGGR_ENABLED)
 774                 ath_tgt_handle_aggr(sc, bf);
 775         else
 776                 ath_tgt_handle_normal(sc, bf);
 777 }
 778
 779 static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
 780                                    adf_nbuf_t buf, void *ServiceCtx)
 781 {
 782         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
 783         struct ath_hal *ah = sc->sc_ah;
 784         a_uint64_t tsf;
 785         a_uint32_t tmp;
 786
 787 #ifdef ATH_ENABLE_CABQ
 788         tsf = ah->ah_getTsf64(ah);
 789         tmp = tsf - sc->sc_swba_tsf;
 790
 791         if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
 792                 HTC_ReturnBuffers(sc->tgt_htc_handle, EndPt, buf);
 793                 return;
 794         }
 795
 796         tgt_HTCRecvMessageHandler(EndPt, hdr_buf, buf, ServiceCtx);
 797 #endif
 798 }
 799
 800 /***********************/
 801 /* Descriptor Handling */
 802 /***********************/
 803
 804 static a_int32_t ath_descdma_setup(struct ath_softc_tgt *sc,
 805                                    struct ath_descdma *dd, ath_bufhead *head,
 806                                    const char *name, a_int32_t nbuf, a_int32_t ndesc,
 807                                    a_uint32_t bfSize, a_uint32_t descSize)
 808 {
 809 #define DS2PHYS(_dd, _ds)                                               \
 810         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 811
 812         struct ath_desc *ds;
 813         struct ath_buf *bf;
 814         a_int32_t i, bsize, error;
 815         a_uint8_t *bf_addr;
 816         a_uint8_t *ds_addr;
 817
 818         dd->dd_name = name;
 819         dd->dd_desc_len = descSize * nbuf * ndesc;
 820
 821         dd->dd_desc = adf_os_dmamem_alloc(sc->sc_dev,
 822                                   dd->dd_desc_len, 1, &dd->dd_desc_dmamap);
 823         dd->dd_desc_paddr = adf_os_dmamem_map2addr(dd->dd_desc_dmamap);
 824         if (dd->dd_desc == NULL) {
 825                 error = -ENOMEM;
 826                 goto fail;
 827         }
 828         ds = dd->dd_desc;
 829
 830         bsize = bfSize * nbuf;
 831         bf = adf_os_mem_alloc(bsize);
 832         if (bf == NULL) {
 833                 error = -ENOMEM;
 834                 goto fail2;
 835         }
 836         adf_os_mem_set(bf, 0, bsize);
 837         dd->dd_bufptr = bf;
 838
 839         bf_addr = (a_uint8_t *)bf;
 840         ds_addr = (a_uint8_t *)ds;
 841
 842         asf_tailq_init(head);
 843
 844         for (i = 0; i < nbuf; i++) {
 845                 a_int32_t j;
 846
 847                 if (adf_nbuf_dmamap_create( sc->sc_dev, &bf->bf_dmamap) != A_STATUS_OK) {
 848                         goto fail2;
 849                 }
 850
 851                 bf->bf_desc = bf->bf_descarr = bf->bf_lastds = ds;
 852                 for (j = 0; j < ndesc; j++)
 853                         ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, j, (ds_addr + (j*descSize)));
 854
 855                 ATH_BUF_SET_DESC_PHY_ADDR(bf, ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, 0));
 856
 857                 adf_nbuf_queue_init(&bf->bf_skbhead);
 858                 asf_tailq_insert_tail(head, bf, bf_list);
 859
 860                 bf_addr += bfSize;
 861                 ds_addr += (ndesc * descSize);
 862                 bf = (struct ath_buf *)bf_addr;
 863                 ds = (struct ath_desc *)ds_addr;
 864         }
 865
 866         return 0;
 867 fail2:
 868         adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
 869                            1, dd->dd_desc, dd->dd_desc_dmamap);
 870 fail:
 871         adf_os_mem_set(dd, 0, sizeof(*dd));
 872         adf_os_assert(0);
 873         return error;
 874
 875 #undef DS2PHYS
 876 }
 877
 878 static void ath_descdma_cleanup(struct ath_softc_tgt *sc,
 879                                 struct ath_descdma *dd,
 880                                 ath_bufhead *head, a_int32_t dir)
 881 {
 882         struct ath_buf *bf;
 883         struct ieee80211_node_target *ni;
 884
 885         asf_tailq_foreach(bf, head, bf_list) {
 886                 if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
 887                         adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, dir);
 888                         while(adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
 889                                 ath_free_rx_skb(sc,
 890                                         adf_nbuf_queue_remove(&bf->bf_skbhead));
 891                         }
 892                         bf->bf_skb = NULL;
 893                 } else if (bf->bf_skb != NULL) {
 894                         adf_nbuf_unmap(sc->sc_dev,bf->bf_dmamap, dir);
 895                         ath_free_rx_skb(sc, bf->bf_skb);
 896                         bf->bf_skb = NULL;
 897                 }
 898
 899                 adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap);
 900
 901                 ni = bf->bf_node;
 902                 bf->bf_node = NULL;
 903         }
 904
 905         adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
 906                            1, dd->dd_desc, dd->dd_desc_dmamap);
 907
 908         asf_tailq_init(head);
 909         adf_os_mem_free(dd->dd_bufptr);
 910         adf_os_mem_set(dd, 0, sizeof(*dd));
 911 }
 912
 913 static a_int32_t ath_desc_alloc(struct ath_softc_tgt *sc)
 914 {
 915 #define DS2PHYS(_dd, _ds)                                               \
 916         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 917
 918         a_int32_t error;
 919         struct ath_tx_buf *bf;
 920
 921         if(ath_numrxbufs == -1)
 922                 ath_numrxbufs = ATH_RXBUF;
 923
 924         if (ath_numrxdescs == -1)
 925                 ath_numrxdescs = ATH_RXDESC;
 926
 927         error = ath_descdma_setup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 928                                   "rx", ath_numrxdescs, 1,
 929                                   sizeof(struct ath_rx_buf),
 930                                   sizeof(struct ath_rx_desc));
 931         if (error != 0)
 932                 return error;
 933
 934         a_uint32_t i;
 935         struct ath_descdma *dd = &sc->sc_rxdma;
 936         struct ath_rx_desc *ds = (struct ath_rx_desc *)dd->dd_desc;
 937         struct ath_rx_desc *ds_prev = NULL;
 938
 939         asf_tailq_init(&sc->sc_rxdesc);
 940         asf_tailq_init(&sc->sc_rxdesc_idle);
 941
 942         for (i = 0; i < ath_numrxdescs; i++, ds++) {
 943
 944                 if (ds->ds_nbuf != ADF_NBUF_NULL) {
 945                         ds->ds_nbuf = ADF_NBUF_NULL;
 946                 }
 947
 948                 if (adf_nbuf_dmamap_create(sc->sc_dev, &ds->ds_dmap) != A_STATUS_OK) {
 949                         adf_os_assert(0);
 950                 }
 951
 952                 ds->ds_daddr = DS2PHYS(&sc->sc_rxdma, ds);
 953
 954                 if (ds_prev) {
 955                         ds_prev->ds_link = ds->ds_daddr;
 956                 }
 957
 958                 ds->ds_link = 0;
 959                 ds_prev = ds;
 960
 961                 asf_tailq_insert_tail(&sc->sc_rxdesc, ds, ds_list);
 962         }
 963
 964         error = ath_descdma_setup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 965                                   "tx", ATH_TXBUF + 1, ATH_TXDESC,
 966                                   sizeof(struct ath_tx_buf),
 967                                   sizeof(struct ath_tx_desc));
 968         if (error != 0) {
 969                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 970                                     ADF_OS_DMA_FROM_DEVICE);
 971                 return error;
 972         }
 973
 974         error = ath_descdma_setup(sc, &sc->sc_bdma, (ath_bufhead *)&sc->sc_bbuf,
 975                                   "beacon", ATH_BCBUF, 1,
 976                                   sizeof(struct ath_tx_buf),
 977                                   sizeof(struct ath_tx_desc));
 978         if (error != 0) {
 979                 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
 980                                     ADF_OS_DMA_TO_DEVICE);
 981                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
 982                                     ADF_OS_DMA_FROM_DEVICE);
 983                 return error;
 984         }
 985
 986         bf = asf_tailq_first(&sc->sc_txbuf);
 987         bf->bf_isaggr = bf->bf_isretried = bf->bf_retries = 0;
 988         asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
 989
 990         sc->sc_txbuf_held = bf;
 991
 992         return 0;
 993
 994 #undef DS2PHYS
 995 }
 996
 997 static void ath_desc_free(struct ath_softc_tgt *sc)
 998 {
 999         asf_tailq_insert_tail(&sc->sc_txbuf, sc->sc_txbuf_held, bf_list);
1000
1001         sc->sc_txbuf_held = NULL;
1002
1003         if (sc->sc_txdma.dd_desc_len != 0)
1004                 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
1005                                     ADF_OS_DMA_TO_DEVICE);
1006         if (sc->sc_rxdma.dd_desc_len != 0)
1007                 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
1008                                     ADF_OS_DMA_FROM_DEVICE);
1009 }
1010
1011 /**********************/
1012 /* Interrupt Handling */
1013 /**********************/
1014
1015 adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl)
1016 {
1017         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl;
1018         struct ath_hal *ah = sc->sc_ah;
1019         HAL_INT status;
1020
1021         if (sc->sc_invalid)
1022                 return ADF_OS_IRQ_NONE;
1023
1024         if (!ah->ah_isInterruptPending(ah))
1025                 return ADF_OS_IRQ_NONE;
1026
1027         ah->ah_getPendingInterrupts(ah, &status);
1028
1029         status &= sc->sc_imask;
1030
1031         if (status & HAL_INT_FATAL) {
1032                 ath_hal_intrset(ah, 0);
1033                 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
1034         } else {
1035                 if (status & HAL_INT_SWBA) {
1036                         WMI_SWBA_EVENT swbaEvt;
1037                         struct ath_txq *txq = ATH_TXQ(sc, 8);
1038
1039                         swbaEvt.tsf = ah->ah_getTsf64(ah);
1040                         swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq);
1041                         sc->sc_swba_tsf = ah->ah_getTsf64(ah);
1042
1043                         wmi_event(sc->tgt_wmi_handle,
1044                                   WMI_SWBA_EVENTID,
1045                                   &swbaEvt,
1046                                   sizeof(WMI_SWBA_EVENT));
1047
1048                         ath_tx_draintxq(sc, txq);
1049                 }
1050
1051                 if (status & HAL_INT_RXORN)
1052                         sc->sc_int_stats.ast_rxorn++;
1053
1054                 if (status & HAL_INT_RXEOL)
1055                         sc->sc_int_stats.ast_rxeol++;
1056
1057                 if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
1058                         if (status & HAL_INT_RX)
1059                                 sc->sc_int_stats.ast_rx++;
1060
1061                         ath_uapsd_processtriggers(sc);
1062
1063                         sc->sc_imask &= ~HAL_INT_RX;
1064                         ath_hal_intrset(ah, sc->sc_imask);
1065
1066                         ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
1067                 }
1068
1069                 if (status & HAL_INT_TXURN) {
1070                         sc->sc_int_stats.ast_txurn++;
1071                         ah->ah_updateTxTrigLevel(ah, AH_TRUE);
1072                 }
1073
1074                 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq);
1075
1076                 if (status & HAL_INT_BMISS) {
1077                         ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_bmisstq);
1078                 }
1079
1080                 if (status & HAL_INT_GTT)
1081                         sc->sc_int_stats.ast_txto++;
1082
1083                 if (status & HAL_INT_CST)
1084                         sc->sc_int_stats.ast_cst++;
1085         }
1086
1087         return ADF_OS_IRQ_HANDLED;
1088 }
1089
1090 static void ath_fatal_tasklet(TQUEUE_ARG data )
1091 {
1092         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1093
1094         wmi_event(sc->tgt_wmi_handle, WMI_FATAL_EVENTID, NULL, 0);
1095 }
1096
1097 static void ath_bmiss_tasklet(TQUEUE_ARG data)
1098 {
1099         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1100
1101         wmi_event(sc->tgt_wmi_handle, WMI_BMISS_EVENTID, NULL, 0);
1102 }
1103
1104 /****************/
1105 /* WMI Commands */
1106 /****************/
1107
1108 static void ath_enable_intr_tgt(void *Context, A_UINT16 Command,
1109                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1110 {
1111         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1112         struct ath_hal *ah = sc->sc_ah;
1113         a_uint32_t intr;
1114
1115         if (data)
1116                 intr = (*(a_uint32_t *)data);
1117
1118         intr = adf_os_ntohl(intr);
1119
1120         if (intr & HAL_INT_SWBA) {
1121                 sc->sc_imask |= HAL_INT_SWBA;
1122         } else {
1123                 sc->sc_imask &= ~HAL_INT_SWBA;
1124         }
1125
1126         if (intr & HAL_INT_BMISS) {
1127                 sc->sc_imask |= HAL_INT_BMISS;
1128         }
1129
1130         ath_hal_intrset(ah, sc->sc_imask);
1131         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1132 }
1133
1134 static void ath_init_tgt(void *Context, A_UINT16 Command,
1135                          A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1136 {
1137         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1138         struct ath_hal *ah = sc->sc_ah;
1139
1140         sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1141                 | HAL_INT_RXEOL | HAL_INT_RXORN
1142                 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1143
1144         sc->sc_imask |= HAL_INT_GTT;
1145
1146         if (ath_hal_htsupported(ah))
1147                 sc->sc_imask |= HAL_INT_CST;
1148
1149         adf_os_setup_intr(sc->sc_dev, ath_intr);
1150         ath_hal_intrset(ah, sc->sc_imask);
1151
1152         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1153 }
1154
1155 static void ath_int_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1156                               A_UINT8 *data, a_int32_t datalen)
1157 {
1158         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1159
1160         struct fusion_stats {
1161                 a_uint32_t ast_rx;
1162                 a_uint32_t ast_rxorn;
1163                 a_uint32_t ast_rxeol;
1164                 a_uint32_t ast_txurn;
1165                 a_uint32_t ast_txto;
1166                 a_uint32_t ast_cst;
1167         };
1168
1169         struct fusion_stats stats;
1170
1171         stats.ast_rx = sc->sc_int_stats.ast_rx;
1172         stats.ast_rxorn = sc->sc_int_stats.ast_rxorn;
1173         stats.ast_rxeol = sc->sc_int_stats.ast_rxeol;
1174         stats.ast_txurn = sc->sc_int_stats.ast_txurn;
1175         stats.ast_txto = sc->sc_int_stats.ast_txto;
1176         stats.ast_cst = sc->sc_int_stats.ast_cst;
1177
1178         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1179 }
1180
1181 static void ath_tx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1182                              A_UINT8 *data, a_int32_t datalen)
1183 {
1184         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1185
1186         struct fusion_stats {
1187                 a_uint32_t   ast_tx_xretries;
1188                 a_uint32_t   ast_tx_fifoerr;
1189                 a_uint32_t   ast_tx_filtered;
1190                 a_uint32_t   ast_tx_timer_exp;
1191                 a_uint32_t   ast_tx_shortretry;
1192                 a_uint32_t   ast_tx_longretry;
1193
1194                 a_uint32_t   tx_qnull;
1195                 a_uint32_t   tx_noskbs;
1196                 a_uint32_t   tx_nobufs;
1197         };
1198
1199         struct fusion_stats stats;
1200
1201         stats.ast_tx_xretries = sc->sc_tx_stats.ast_tx_xretries;
1202         stats.ast_tx_fifoerr = sc->sc_tx_stats.ast_tx_fifoerr;
1203         stats.ast_tx_filtered = sc->sc_tx_stats.ast_tx_filtered;
1204         stats.ast_tx_timer_exp = sc->sc_tx_stats.ast_tx_timer_exp;
1205         stats.ast_tx_shortretry = sc->sc_tx_stats.ast_tx_shortretry;
1206         stats.ast_tx_longretry = sc->sc_tx_stats.ast_tx_longretry;
1207         stats.tx_qnull = sc->sc_tx_stats.tx_qnull;
1208         stats.tx_noskbs = sc->sc_tx_stats.tx_noskbs;
1209         stats.tx_nobufs = sc->sc_tx_stats.tx_nobufs;
1210
1211         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1212 }
1213
1214 static void ath_rx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1215                              A_UINT8 *data, a_int32_t datalen)
1216 {
1217         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1218
1219         struct fusion_stats {
1220                 a_uint32_t   ast_rx_nobuf;
1221                 a_uint32_t   ast_rx_send;
1222                 a_uint32_t   ast_rx_done;
1223         };
1224
1225         struct fusion_stats stats;
1226
1227         stats.ast_rx_nobuf = sc->sc_rx_stats.ast_rx_nobuf;
1228         stats.ast_rx_send = sc->sc_rx_stats.ast_rx_send;
1229         stats.ast_rx_done = sc->sc_rx_stats.ast_rx_done;
1230
1231         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1232 }
1233
1234 static void ath_get_tgt_version(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1235                                 A_UINT8 *data, a_int32_t datalen)
1236 {
1237         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1238         struct wmi_fw_version ver;
1239
1240         ver.major = ATH_VERSION_MAJOR;
1241         ver.minor = ATH_VERSION_MINOR;
1242
1243         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &ver, sizeof(ver));
1244 }
1245
1246 static void ath_enable_aggr_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1247                                 A_UINT8 *data, a_int32_t datalen)
1248 {
1249         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1250         struct ath_aggr_info *aggr = (struct ath_aggr_info *)data;
1251         a_uint8_t nodeindex = aggr->nodeindex;
1252         a_uint8_t tidno = aggr->tidno;
1253         struct ath_node_target *an = NULL ;
1254         struct ath_atx_tid  *tid = NULL;
1255
1256         if (nodeindex >= TARGET_NODE_MAX) {
1257                 goto done;
1258         }
1259
1260         an = &sc->sc_sta[nodeindex];
1261         if (!an->an_valid) {
1262                 goto done;
1263         }
1264
1265         if (tidno >= WME_NUM_TID) {
1266                 adf_os_print("[%s] enable_aggr with invalid tid %d(node = %d)\n",
1267                              __FUNCTION__, tidno, nodeindex);
1268                 goto done;
1269         }
1270
1271         tid = ATH_AN_2_TID(an, tidno);
1272
1273         if (aggr->aggr_enable) {
1274                 tid->flag |= TID_AGGR_ENABLED;
1275         } else if ( tid->flag & TID_AGGR_ENABLED ) {
1276                 tid->flag &= ~TID_AGGR_ENABLED;
1277                 ath_tgt_tx_cleanup(sc, an, tid, 1);
1278         }
1279 done:
1280         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1281 }
1282
1283 static void ath_ic_update_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1284                               A_UINT8 *data, a_int32_t datalen)
1285 {
1286         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1287         struct ieee80211com_target *ic = (struct ieee80211com_target * )data;
1288         struct ieee80211com_target *ictgt = &sc->sc_ic ;
1289
1290         adf_os_mem_copy(ictgt, ic, sizeof(struct  ieee80211com_target));
1291
1292         ictgt->ic_ampdu_limit         = adf_os_ntohl(ic->ic_ampdu_limit);
1293
1294         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1295 }
1296
1297 static void ath_vap_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1298                                A_UINT8 *data, a_int32_t datalen)
1299 {
1300         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1301         struct ieee80211vap_target *vap;
1302         a_uint8_t vap_index;
1303
1304         vap = (struct ieee80211vap_target *)data;
1305
1306         vap->iv_rtsthreshold    = adf_os_ntohs(vap->iv_rtsthreshold);
1307         vap->iv_opmode          = adf_os_ntohl(vap->iv_opmode);
1308
1309         vap_index = vap->iv_vapindex;
1310
1311         adf_os_assert(sc->sc_vap[vap_index].av_valid == 0);
1312
1313         adf_os_mem_copy(&(sc->sc_vap[vap_index].av_vap), vap,
1314                         VAP_TARGET_SIZE);
1315
1316         sc->sc_vap[vap_index].av_bcbuf = asf_tailq_first(&(sc->sc_bbuf));
1317         sc->sc_vap[vap_index].av_valid = 1;
1318
1319         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1320 }
1321
1322 static void ath_node_create_tgt(void *Context, A_UINT16 Command,
1323                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1324 {
1325         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1326         struct ieee80211_node_target *node;
1327         a_uint8_t vap_index;
1328         a_uint8_t node_index;
1329
1330         node = (struct ieee80211_node_target *)data;
1331
1332         node_index = node->ni_nodeindex;
1333
1334         node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1335         node->ni_flags = adf_os_ntohs(node->ni_flags);
1336         node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1337
1338         adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1339                         NODE_TARGET_SIZE);
1340
1341         vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1342         sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1343         if(sc->sc_sta[node_index].ni.ni_is_vapnode == 1)
1344                 sc->sc_vap[vap_index].av_vap.iv_nodeindex = node_index;
1345
1346         sc->sc_sta[node_index].an_valid = 1;
1347         sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1348         sc->sc_sta[node_index].ni.ni_iv16 = 0;
1349         sc->sc_sta[node_index].ni.ni_iv32 = 0;
1350
1351         owl_tgt_node_init(&sc->sc_sta[node_index]);
1352
1353         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1354 }
1355
1356 static void ath_node_cleanup_tgt(void *Context, A_UINT16 Command,
1357                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1358 {
1359         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1360         a_uint8_t node_index;
1361         a_uint8_t *nodedata;
1362
1363         nodedata = (a_uint8_t *)data;
1364         node_index = *nodedata;
1365         sc->sc_sta[node_index].an_valid = 0;
1366
1367         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1368 }
1369
1370 static void ath_node_update_tgt(void *Context, A_UINT16 Command,
1371                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1372 {
1373         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1374         struct ieee80211_node_target *node;
1375         a_uint8_t vap_index;
1376         a_uint8_t node_index;
1377
1378         node = (struct ieee80211_node_target *)data;
1379
1380         node_index = node->ni_nodeindex;
1381
1382         node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1383         node->ni_flags = adf_os_ntohs(node->ni_flags);
1384         node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1385
1386         adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1387                         NODE_TARGET_SIZE);
1388
1389         vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1390         sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1391
1392         sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1393         sc->sc_sta[node_index].ni.ni_iv16 = 0;
1394         sc->sc_sta[node_index].ni.ni_iv32 = 0;
1395
1396         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1397 }
1398
1399 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
1400                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1401 {
1402         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1403         struct ath_hal *ah = sc->sc_ah;
1404         a_uint32_t addr;
1405         a_uint32_t val[32];
1406         int i;
1407
1408         for (i = 0; i < datalen; i += sizeof(a_int32_t)) {
1409                 addr = *(a_uint32_t *)(data + i);
1410                 addr = adf_os_ntohl(addr);
1411
1412                 if ((addr & 0xffffe000) == 0x2000) {
1413                         /* SEEPROM */
1414                         ath_hal_reg_read_target(ah, addr);
1415                         if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) {
1416                                 adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
1417                         }
1418                         val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
1419                 } else if (addr > 0xffff) {
1420                         val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr;
1421                 } else
1422                         val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr);
1423
1424                 val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]);
1425         }
1426
1427         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
1428 }
1429
1430 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
1431                                   A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1432 {
1433         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1434         struct ath_hal *ah = sc->sc_ah;
1435         int i;
1436         struct registerWrite {
1437                 a_uint32_t reg;
1438                 a_uint32_t val;
1439         }*t;
1440
1441         for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
1442                 t = (struct registerWrite *)(data+i);
1443
1444                 if( t->reg > 0xffff ) {
1445                         a_uint32_t *pReg = (a_uint32_t *)t->reg;
1446
1447                         *pReg = t->val;
1448
1449 #if defined(PROJECT_K2)
1450                         if( t->reg == 0x50040 ) {
1451                                 static uint8_t flg=0;
1452
1453                                 if( flg == 0 ) {
1454                                         A_CLOCK_INIT(117);
1455                                         A_UART_HWINIT(117*1000*1000, 19200);
1456                                         flg = 1;
1457                                 }
1458                         }
1459 #endif
1460                 } else {
1461 #if defined(PROJECT_K2)
1462                         if( t->reg == 0x7014 ) {
1463                                 static uint8_t resetPLL = 0;
1464                                 a_uint32_t *pReg;
1465
1466                                 if( resetPLL == 0 ) {
1467                                         t->reg = 0x50044;
1468                                         pReg = (a_uint32_t *)t->reg;
1469                                         *pReg = 0;
1470                                         ath_hal_reg_write_target(ah, 0x786c,
1471                                                  ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
1472                                         ath_hal_reg_write_target(ah, 0x786c,
1473                                                  ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
1474                                         *pReg = 0x20;
1475                                         resetPLL = 1;
1476                                 }
1477                                 t->reg = 0x7014;
1478                         }
1479 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
1480                         if( t->reg == 0x7014 ){
1481                                 static uint8_t resetPLL = 0;
1482
1483                                 if( resetPLL == 0 ) {
1484                                         ath_hal_reg_write_target(ah, 0x7890,
1485                                                  ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
1486                                         ath_hal_reg_write_target(ah, 0x7890,
1487                                                  ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
1488                                         resetPLL = 1;
1489                                 }
1490                         }
1491 #endif
1492                         ath_hal_reg_write_target(ah,t->reg,t->val);
1493                 }
1494         }
1495
1496         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1497 }
1498
1499 static void ath_vap_delete_tgt(void *Context, A_UINT16 Command,
1500                                A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1501 {
1502         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1503         a_uint8_t vap_index;
1504
1505         vap_index = *(a_uint8_t *)data;
1506
1507         sc->sc_vap[vap_index].av_valid = 0;
1508         sc->sc_vap[vap_index].av_bcbuf = NULL;
1509         ath_node_vdelete_tgt(sc, vap_index);
1510         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1511 }
1512
1513 static void ath_disable_intr_tgt(void *Context, A_UINT16 Command,
1514                                  A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1515 {
1516         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1517         struct ath_hal *ah = sc->sc_ah;
1518
1519         ath_hal_intrset(ah, 0);
1520         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1521 }
1522
1523 static void ath_flushrecv_tgt(void *Context, A_UINT16 Command,
1524                               A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1525 {
1526         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1527         struct ath_rx_buf *bf;
1528
1529         asf_tailq_foreach(bf, &sc->sc_rxbuf, bf_list)
1530                 if (bf->bf_skb != NULL) {
1531                         adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap,
1532                                        ADF_OS_DMA_FROM_DEVICE);
1533                         ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead));
1534                         bf->bf_skb = NULL;
1535                 }
1536
1537         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1538 }
1539
1540 static void ath_tx_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1541                                 A_UINT8 *data, a_int32_t datalen)
1542 {
1543         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1544         a_uint32_t q = *(a_uint32_t *)data;
1545         struct ath_txq *txq = NULL;
1546
1547         q = adf_os_ntohl(q);
1548         txq = ATH_TXQ(sc, q);
1549
1550         ath_tx_draintxq(sc, txq);
1551         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1552 }
1553
1554 static void ath_draintxq_tgt(void *Context, A_UINT16 Command,
1555                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1556 {
1557         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1558         HAL_BOOL b = (HAL_BOOL) *(a_int32_t *)data;
1559
1560         ath_draintxq(Context, b);
1561         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1562 }
1563
1564 static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command,
1565                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1566 {
1567         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1568         struct ath_hal *ah = sc->sc_ah;
1569
1570         ah->ah_abortTxDma(sc->sc_ah);
1571         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1572 }
1573
1574 static void ath_aborttxq_tgt(void *Context, A_UINT16 Command,
1575                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1576 {
1577
1578         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1579         a_uint16_t i;
1580
1581         for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
1582                 if (ATH_TXQ_SETUP(sc, i))
1583                         ath_tx_draintxq(sc, ATH_TXQ(sc,i));
1584         }
1585
1586         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1587 }
1588
1589 static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command,
1590                                 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1591 {
1592         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1593         struct ath_hal *ah = sc->sc_ah;
1594         a_uint32_t q;
1595
1596         if (data)
1597                 q = *(a_uint32_t *)data;
1598
1599         q = adf_os_ntohl(q);
1600         ah->ah_stopTxDma(ah, q);
1601         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1602 }
1603
1604 static void ath_startrecv_tgt(void *Context, A_UINT16 Command,
1605                               A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1606 {
1607
1608         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1609
1610         ath_startrecv(sc);
1611         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1612 }
1613
1614 static void ath_stoprecv_tgt(void *Context, A_UINT16 Command,
1615                              A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1616 {
1617         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1618         struct ath_hal *ah = sc->sc_ah;
1619
1620         ah->ah_stopPcuReceive(ah);
1621         ah->ah_setRxFilter(ah, 0);
1622         ah->ah_stopDmaReceive(ah);
1623
1624         sc->sc_rxlink = NULL;
1625         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1626 }
1627
1628 static void ath_setcurmode_tgt(void *Context, A_UINT16 Command,
1629                                A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1630 {
1631         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1632         a_uint16_t mode;
1633
1634         mode= *((a_uint16_t *)data);
1635         mode = adf_os_ntohs(mode);
1636
1637         ath_setcurmode(sc, mode);
1638
1639         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1640 }
1641
1642 static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1643                                  A_UINT8 *data, a_int32_t datalen)
1644 {
1645         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1646         struct ath_hal *ah = sc->sc_ah;
1647
1648         ath_desc_free(sc);
1649         ah->ah_detach(ah);
1650         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1651         adf_os_mem_free(sc);
1652 }
1653
1654 static void handle_echo_command(void *pContext, A_UINT16 Command,
1655                                 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1656 {
1657         wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length);
1658 }
1659
1660 static void handle_rc_state_change_cmd(void *Context, A_UINT16 Command,
1661                                        A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1662
1663 {
1664         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1665         struct wmi_rc_state_change_cmd *wmi_data = (struct wmi_rc_state_change_cmd *)buffer;
1666
1667         a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1668
1669         ath_rate_newstate(sc, &sc->sc_vap[wmi_data->vap_index].av_vap,
1670                           wmi_data->vap_state,
1671                           capflag,
1672                           &wmi_data->rs);
1673
1674         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1675 }
1676
1677 static void handle_rc_rate_update_cmd(void *Context, A_UINT16 Command,
1678                                       A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1679 {
1680         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1681         struct wmi_rc_rate_update_cmd *wmi_data = (struct wmi_rc_rate_update_cmd *)buffer;
1682
1683         a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1684
1685         ath_rate_node_update(sc, &sc->sc_sta[wmi_data->node_index],
1686                              wmi_data->isNew,
1687                              capflag,
1688                              &wmi_data->rs);
1689
1690         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1691 }
1692
1693 static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command,
1694                                      A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1695 {
1696         adf_os_assert(0);
1697 }
1698
1699 static void ath_rc_mask_tgt(void *Context, A_UINT16 Command,
1700                             A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1701 {
1702         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1703         struct wmi_rc_rate_mask_cmd *wmi_data = (struct wmi_rc_rate_mask_cmd *)buffer;
1704         int idx, band, i;
1705
1706         idx = wmi_data->vap_index;
1707         band = wmi_data->band;
1708
1709         sc->sc_vap[idx].av_rate_mask[band] = adf_os_ntohl(wmi_data->mask);
1710
1711         if (sc->sc_vap[idx].av_rate_mask[band]) {
1712                 for (i = 0; i < RATE_TABLE_SIZE; i++) {
1713                         if ((1 << i) & sc->sc_vap[idx].av_rate_mask[band]) {
1714                                 sc->sc_vap[idx].av_minrateidx[band] = i;
1715                                 break;
1716                         }
1717                 }
1718         } else {
1719                 sc->sc_vap[idx].av_minrateidx[band] = 0;
1720         }
1721
1722         wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1723 }
1724
1725 static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] =
1726 {
1727         {handle_echo_command,         WMI_ECHO_CMDID,               0},
1728         {dispatch_magpie_sys_cmds,    WMI_ACCESS_MEMORY_CMDID,      0},
1729         {ath_get_tgt_version,         WMI_GET_FW_VERSION,           0},
1730         {ath_disable_intr_tgt,        WMI_DISABLE_INTR_CMDID,       0},
1731         {ath_enable_intr_tgt,         WMI_ENABLE_INTR_CMDID,        0},
1732         {ath_init_tgt,                WMI_ATH_INIT_CMDID,           0},
1733         {ath_aborttxq_tgt,            WMI_ABORT_TXQ_CMDID,          0},
1734         {ath_stop_tx_dma_tgt,         WMI_STOP_TX_DMA_CMDID,        0},
1735         {ath_aborttx_dma_tgt,         WMI_ABORT_TX_DMA_CMDID,       0},
1736         {ath_tx_draintxq_tgt,         WMI_DRAIN_TXQ_CMDID,          0},
1737         {ath_draintxq_tgt,            WMI_DRAIN_TXQ_ALL_CMDID,      0},
1738         {ath_startrecv_tgt,           WMI_START_RECV_CMDID,         0},
1739         {ath_stoprecv_tgt,            WMI_STOP_RECV_CMDID,          0},
1740         {ath_flushrecv_tgt,           WMI_FLUSH_RECV_CMDID,         0},
1741         {ath_setcurmode_tgt,          WMI_SET_MODE_CMDID,           0},
1742         {ath_node_create_tgt,         WMI_NODE_CREATE_CMDID,        0},
1743         {ath_node_cleanup_tgt,        WMI_NODE_REMOVE_CMDID,        0},
1744         {ath_vap_delete_tgt,          WMI_VAP_REMOVE_CMDID,         0},
1745         {ath_vap_create_tgt,          WMI_VAP_CREATE_CMDID,         0},
1746         {ath_hal_reg_read_tgt,        WMI_REG_READ_CMDID,           0},
1747         {ath_hal_reg_write_tgt,       WMI_REG_WRITE_CMDID,          0},
1748         {handle_rc_state_change_cmd,  WMI_RC_STATE_CHANGE_CMDID,    0},
1749         {handle_rc_rate_update_cmd,   WMI_RC_RATE_UPDATE_CMDID,     0},
1750         {ath_ic_update_tgt,           WMI_TARGET_IC_UPDATE_CMDID,   0},
1751         {ath_enable_aggr_tgt,         WMI_TX_AGGR_ENABLE_CMDID,     0},
1752         {ath_detach_tgt,              WMI_TGT_DETACH_CMDID,         0},
1753         {ath_node_update_tgt,         WMI_NODE_UPDATE_CMDID,        0},
1754         {ath_int_stats_tgt,           WMI_INT_STATS_CMDID,          0},
1755         {ath_tx_stats_tgt,            WMI_TX_STATS_CMDID,           0},
1756         {ath_rx_stats_tgt,            WMI_RX_STATS_CMDID,           0},
1757         {ath_rc_mask_tgt,             WMI_BITRATE_MASK_CMDID,       0},
1758 };
1759
1760 /*****************/
1761 /* Init / Deinit */
1762 /*****************/
1763
1764 static void htc_setup_comp(void)
1765 {
1766 }
1767
1768 static A_UINT8 tgt_ServiceConnect(HTC_SERVICE *pService,
1769                                   HTC_ENDPOINT_ID eid,
1770                                   A_UINT8 *pDataIn,
1771                                   a_int32_t LengthIn,
1772                                   A_UINT8 *pDataOut,
1773                                   a_int32_t *pLengthOut)
1774 {
1775         struct ath_softc_tgt *sc = (struct ath_softc_tgt *)pService->ServiceCtx;
1776
1777         switch(pService->ServiceID) {
1778         case WMI_CONTROL_SVC:
1779                 sc->wmi_command_ep= eid;
1780                 break;
1781         case WMI_BEACON_SVC:
1782                 sc->beacon_ep= eid;
1783                 break;
1784         case WMI_CAB_SVC:
1785                 sc->cab_ep= eid;
1786                 break;
1787         case WMI_UAPSD_SVC:
1788                 sc->uapsd_ep= eid;
1789                 break;
1790         case WMI_MGMT_SVC:
1791                 sc->mgmt_ep= eid;
1792                 break;
1793         case WMI_DATA_VO_SVC:
1794                 sc->data_VO_ep = eid;
1795                 break;
1796         case WMI_DATA_VI_SVC:
1797                 sc->data_VI_ep = eid;
1798                 break;
1799         case WMI_DATA_BE_SVC:
1800                 sc->data_BE_ep = eid;
1801                 break;
1802         case WMI_DATA_BK_SVC:
1803                 sc->data_BK_ep = eid;
1804                 break;
1805         default:
1806                 adf_os_assert(0);
1807         }
1808
1809         return HTC_SERVICE_SUCCESS;
1810 }
1811
1812 static void tgt_reg_service(struct ath_softc_tgt *sc, HTC_SERVICE *svc,
1813                             int svcId, HTC_SERVICE_ProcessRecvMsg recvMsg)
1814 {
1815         svc->ProcessRecvMsg = recvMsg;
1816         svc->ProcessSendBufferComplete = tgt_HTCSendCompleteHandler;
1817         svc->ProcessConnect = tgt_ServiceConnect;
1818         svc->MaxSvcMsgSize = 1600;
1819         svc->TrailerSpcCheckLimit = 0;
1820         svc->ServiceID = svcId;
1821         svc->ServiceCtx = sc;
1822         HTC_RegisterService(sc->tgt_htc_handle, svc);
1823 }
1824
1825 static void tgt_hif_htc_wmi_init(struct ath_softc_tgt *sc)
1826 {
1827         HTC_CONFIG htc_conf;
1828         WMI_SVC_CONFIG wmiConfig;
1829         WMI_DISPATCH_TABLE *Magpie_Sys_Commands_Tbl;
1830
1831         /* Init dynamic buf pool */
1832         sc->pool_handle = BUF_Pool_init(sc->sc_hdl);
1833
1834         /* Init target-side HIF */
1835         sc->tgt_hif_handle = HIF_init(0);
1836
1837         /* Init target-side HTC */
1838         htc_conf.HIFHandle = sc->tgt_hif_handle;
1839         htc_conf.CreditSize = 320;
1840         htc_conf.CreditNumber = ATH_TXBUF;
1841         htc_conf.OSHandle = sc->sc_hdl;
1842         htc_conf.PoolHandle = sc->pool_handle;
1843         sc->tgt_htc_handle = HTC_init(htc_setup_comp, &htc_conf);
1844 #if defined(PROJECT_MAGPIE)
1845         init_htc_handle = sc->tgt_htc_handle;
1846 #endif
1847
1848         tgt_reg_service(sc, &sc->htc_beacon_service, WMI_BEACON_SVC, tgt_HTCRecv_beaconhandler);
1849         tgt_reg_service(sc, &sc->htc_cab_service, WMI_CAB_SVC, tgt_HTCRecv_cabhandler);
1850         tgt_reg_service(sc, &sc->htc_uapsd_service, WMI_UAPSD_SVC, tgt_HTCRecv_uapsdhandler);
1851         tgt_reg_service(sc, &sc->htc_mgmt_service, WMI_MGMT_SVC, tgt_HTCRecv_mgmthandler);
1852         tgt_reg_service(sc, &sc->htc_data_BE_service, WMI_DATA_BE_SVC, tgt_HTCRecvMessageHandler);
1853         tgt_reg_service(sc, &sc->htc_data_BK_service, WMI_DATA_BK_SVC, tgt_HTCRecvMessageHandler);
1854         tgt_reg_service(sc, &sc->htc_data_VI_service, WMI_DATA_VI_SVC, tgt_HTCRecvMessageHandler);
1855         tgt_reg_service(sc, &sc->htc_data_VO_service, WMI_DATA_VO_SVC, tgt_HTCRecvMessageHandler);
1856
1857         /* Init target-side WMI */
1858         Magpie_Sys_Commands_Tbl = (WMI_DISPATCH_TABLE *)adf_os_mem_alloc(sizeof(WMI_DISPATCH_TABLE));
1859         adf_os_mem_zero(Magpie_Sys_Commands_Tbl, sizeof(WMI_DISPATCH_TABLE));
1860         Magpie_Sys_Commands_Tbl->NumberOfEntries = WMI_DISPATCH_ENTRY_COUNT(Magpie_Sys_DispatchEntries);
1861         Magpie_Sys_Commands_Tbl->pTable = Magpie_Sys_DispatchEntries;
1862
1863         adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG));
1864         wmiConfig.HtcHandle = sc->tgt_htc_handle;
1865         wmiConfig.PoolHandle = sc->pool_handle;
1866         wmiConfig.MaxCmdReplyEvts = ATH_WMI_MAX_CMD_REPLY;
1867         wmiConfig.MaxEventEvts = ATH_WMI_MAX_EVENTS;
1868
1869         sc->tgt_wmi_handle = WMI_Init(&wmiConfig);
1870         Magpie_Sys_Commands_Tbl->pContext = sc;
1871         WMI_RegisterDispatchTable(sc->tgt_wmi_handle, Magpie_Sys_Commands_Tbl);
1872
1873         HTC_NotifyTargetInserted(sc->tgt_htc_handle);
1874
1875         /* Start HTC messages exchange */
1876         HTC_Ready(sc->tgt_htc_handle);
1877 }
1878
1879 a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_device_t osdev)
1880 {
1881         struct ath_hal *ah;
1882         HAL_STATUS status;
1883         a_int32_t error = 0, i, flags = 0;
1884         a_uint8_t csz;
1885
1886         adf_os_pci_config_read8(osdev, ATH_PCI_CACHE_LINE_SIZE, &csz);
1887
1888         if (csz == 0)
1889                 csz = 16;
1890         sc->sc_cachelsz = csz << 2;
1891
1892         sc->sc_dev = osdev;
1893         sc->sc_hdl = osdev;
1894
1895         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_rxtq, ath_tgt_rx_tasklet, sc);
1896         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_txtq, owl_tgt_tx_tasklet, sc);
1897         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_bmisstq, ath_bmiss_tasklet, sc);
1898         ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_fataltq, ath_fatal_tasklet, sc);
1899
1900         flags |= AH_USE_EEPROM;
1901         ah = _ath_hal_attach_tgt(devid, sc, sc->sc_dev, flags, &status);
1902         if (ah == NULL) {
1903                 error = ENXIO;
1904                 goto bad;
1905         }
1906         sc->sc_ah = ah;
1907
1908         tgt_hif_htc_wmi_init(sc);
1909
1910         sc->sc_bhalq = HAL_NUM_TX_QUEUES - 1;
1911
1912         ath_rate_setup(sc, IEEE80211_MODE_11NA);
1913         ath_rate_setup(sc, IEEE80211_MODE_11NG);
1914
1915         sc->sc_rc = ath_rate_attach(sc);
1916         if (sc->sc_rc == NULL) {
1917                 error = EIO;
1918                 goto bad2;
1919         }
1920
1921         for (i=0; i < TARGET_NODE_MAX; i++) {
1922                 sc->sc_sta[i].an_rcnode = adf_os_mem_alloc(sc->sc_rc->arc_space);
1923         }
1924
1925         error = ath_desc_alloc(sc);
1926         if (error != 0) {
1927                 goto bad;
1928         }
1929
1930         BUF_Pool_create_pool(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ath_numrxdescs, 1664);
1931
1932         ath_tgt_txq_setup(sc);
1933         sc->sc_imask =0;
1934         ath_hal_intrset(ah,0);
1935
1936         return 0;
1937 bad:
1938 bad2:
1939         ath_desc_free(sc);
1940         if (ah)
1941                 ah->ah_detach(ah);
1942 }
1943
1944 static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)
1945 {
1946         HTC_NotifyTargetDetached(sc->tgt_htc_handle);
1947
1948         WMI_Shutdown(sc->tgt_wmi_handle);
1949         HTC_Shutdown(sc->tgt_htc_handle);
1950         HIF_shutdown(sc->tgt_hif_handle);
1951         BUF_Pool_shutdown(sc->pool_handle);
1952 }
1953
1954 a_int32_t ath_detach(struct ath_softc_tgt *sc)
1955 {
1956         tgt_hif_htc_wmi_shutdown(sc);
1957 }