2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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37 #include "ah_internal.h"
39 #include "ar5416reg.h"
40 #include "ar5416desc.h"
42 #define N(a) (sizeof(a)/sizeof(a[0]))
43 #define AR_INTR_SPURIOUS 0xffffffff
44 #define ar5416_desc ar5416_desc_20
45 #define AR5416_ABORT_LOOPS 1000
46 #define AR5416_ABORT_WAIT 5
47 #define AR5416DESC AR5416DESC_20
48 #define AR5416DESC_CONST AR5416DESC_CONST_20
54 static const struct ath_hal_private ar5416hal_10 = {{
55 .ah_getRateTable = ar5416GetRateTable,
56 .ah_detach = ar5416Detach,
58 /* Transmit functions */
59 .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
60 .ah_setTxDP = ar5416SetTxDP,
61 .ah_numTxPending = ar5416NumTxPending,
62 .ah_startTxDma = ar5416StartTxDma,
63 .ah_stopTxDma = ar5416StopTxDma,
65 .ah_abortTxDma = ar5416AbortTxDma,
68 .ah_getTsf64 = ar5416GetTsf64,
69 .ah_setRxFilter = ar5416SetRxFilter,
72 .ah_setRxDP = ar5416SetRxDP,
73 .ah_stopDmaReceive = ar5416StopDmaReceive,
74 .ah_enableReceive = ar5416EnableReceive,
75 .ah_stopPcuReceive = ar5416StopPcuReceive,
77 /* Interrupt Functions */
78 .ah_isInterruptPending = ar5416IsInterruptPending,
79 .ah_getPendingInterrupts = ar5416GetPendingInterrupts,
80 .ah_setInterrupts = ar5416SetInterrupts,
84 void ar5416Detach(struct ath_hal *ah)
86 HALASSERT(ah != AH_NULL);
91 ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev,
92 a_uint32_t flags, HAL_STATUS *status)
94 struct ath_hal_5416 *ahp;
97 ahp = ath_hal_malloc(sizeof (struct ath_hal_5416));
102 ah = &ahp->ah_priv.h;
104 OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private));
109 /* If its a Owl 2.0 chip then change the hal structure to
110 point to the Owl 2.0 ar5416_hal_20 structure */
112 ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
113 ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
114 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
115 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
116 ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
117 ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
118 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
119 ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
120 ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
121 ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
122 ah->ah_fillTxDesc = ar5416FillTxDesc_20;
123 ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
124 ah->ah_procTxDesc = ar5416ProcTxDesc_20;
125 ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
131 /**********************/
132 /* Interrupt Handling */
133 /**********************/
135 HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
137 a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
139 * Some platforms trigger our ISR before applying power to
140 * the card, so make sure.
142 return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ));
145 HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
149 HAL_BOOL fatal_int = AH_FALSE;
150 a_uint32_t sync_cause;
152 if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
153 if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
162 isr = OS_REG_READ(ah, AR_ISR_RAC);
163 if (isr == 0xffffffff) {
168 *masked = isr & HAL_INT_COMMON;
170 #ifdef AR5416_INT_MITIGATION
171 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) {
172 *masked |= HAL_INT_RX;
174 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) {
175 *masked |= HAL_INT_TX;
179 if (isr & AR_ISR_BCNMISC) {
182 s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
184 if (s2_s & AR_ISR_S2_GTT) {
185 *masked |= HAL_INT_GTT;
188 if (s2_s & AR_ISR_S2_CST) {
189 *masked |= HAL_INT_CST;
193 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
194 *masked |= HAL_INT_RX;
195 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
196 struct ath_hal_5416 *ahp = AH5416(ah);
197 a_uint32_t s0_s, s1_s;
199 *masked |= HAL_INT_TX;
200 s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
201 s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
202 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
203 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
204 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
205 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
209 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
210 fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
211 (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
214 if (AH_TRUE == fatal_int) {
215 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
216 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
223 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
225 struct ath_hal_5416 *ahp = AH5416(ah);
226 a_uint32_t omask = ahp->ah_maskReg;
229 if (omask & HAL_INT_GLOBAL) {
230 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
231 (void) OS_REG_READ(ah, AR_IER);
234 mask = ints & HAL_INT_COMMON;
235 if (ints & HAL_INT_TX) {
236 #ifdef AR5416_INT_MITIGATION
237 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
240 mask |= AR_IMR_TXDESC;
242 mask |= AR_IMR_TXERR;
243 mask |= AR_IMR_TXEOL;
245 if (ints & HAL_INT_RX) {
246 mask |= AR_IMR_RXERR;
247 #ifdef AR5416_INT_MITIGATION
248 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
250 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
254 if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
255 mask |= AR_IMR_BCNMISC;
258 OS_REG_WRITE(ah, AR_IMR, mask);
259 (void) OS_REG_READ(ah, AR_IMR);
260 ahp->ah_maskReg = ints;
262 /* Re-enable interrupts if they were enabled before. */
263 if (ints & HAL_INT_GLOBAL) {
264 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
265 /* See explanation above... */
266 (void) OS_REG_READ(ah, AR_IER);
269 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
270 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
271 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
280 u_int64_t ar5416GetTsf64(struct ath_hal *ah)
284 tsf = OS_REG_READ(ah, AR_TSF_U32);
285 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
293 void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
295 OS_REG_WRITE(ah, AR_RXDP, rxdp);
296 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
299 void ar5416SetMulticastFilter(struct ath_hal *ah, a_uint32_t filter0, a_uint32_t filter1)
301 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
302 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
305 HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
312 val = OS_REG_READ(ah, AR_MCAST_FIL1);
313 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
315 val = OS_REG_READ(ah, AR_MCAST_FIL0);
316 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
321 HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
323 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
324 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
331 HAL_BOOL ar5416SetMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
338 val = OS_REG_READ(ah, AR_MCAST_FIL1);
339 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
341 val = OS_REG_READ(ah, AR_MCAST_FIL0);
342 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
347 void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
351 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
353 if (bits & HAL_RX_FILTER_PHYRADAR)
354 phybits |= AR_PHY_ERR_RADAR;
355 if (bits & HAL_RX_FILTER_PHYERR)
356 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
357 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
359 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
361 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
365 void ar5416EnableReceive(struct ath_hal *ah)
367 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
370 void ar5416StopPcuReceive(struct ath_hal *ah)
372 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
375 HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *ah, struct ath_rx_desc *ds,
376 a_uint32_t size, a_uint32_t flags)
378 struct ar5416_desc *ads = AR5416DESC(ds);
380 HALASSERT((size &~ AR_BufLen) == 0);
382 ads->ds_ctl1 = size & AR_BufLen;
383 if (flags & HAL_RXDESC_INTREQ)
384 ads->ds_ctl1 |= AR_RxIntrReq;
386 /* this should be enough */
387 ads->ds_rxstatus8 &= ~AR_RxDone;
392 HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds,
393 a_uint32_t pa, struct ath_desc *nds,
394 struct ath_rx_status *rx_stats)
396 struct ar5416_desc ads;
397 struct ar5416_desc *adsp = AR5416DESC(ds);
398 struct ar5416_desc *ands = AR5416DESC(nds);
400 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
401 return HAL_EINPROGRESS;
403 * Given the use of a self-linked tail be very sure that the hw is
404 * done with this descriptor; the hw may have done this descriptor
405 * once and picked it up again...make sure the hw has moved on.
407 if ((ands->ds_rxstatus8 & AR_RxDone) == 0
408 && OS_REG_READ(ah, AR_RXDP) == pa)
409 return HAL_EINPROGRESS;
412 * Now we need to get the stats from the descriptor. Since desc are
413 * uncached, lets make a copy of the stats first. Note that, since we
414 * touch most of the rx stats, a memcpy would always be more efficient
416 * Next we fill in all values in a caller passed stack variable.
417 * This reduces the number of uncached accesses.
418 * Do this copy here, after the check so that when the checks fail, we
419 * dont end up copying the entire stats uselessly.
421 ads.u.rx = adsp->u.rx;
423 rx_stats->rs_status = 0;
424 rx_stats->rs_flags = 0;
426 rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
427 rx_stats->rs_tstamp = ads.AR_RcvTimestamp;
429 /* XXX what about KeyCacheMiss? */
430 rx_stats->rs_rssi_combined =
431 MS(ads.ds_rxstatus4, AR_RxRSSICombined);
432 rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
433 rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
434 rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
435 rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
436 rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
437 rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
438 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
439 rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
441 rx_stats->rs_keyix = HAL_RXKEYIX_INVALID;
442 /* NB: caller expected to do rate table mapping */
443 rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads));
444 rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
446 rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
447 rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
448 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
449 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
451 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
452 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE;
453 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
454 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST;
455 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
456 rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY;
458 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
460 * These four bits should not be set together. The
461 * 5416 spec states a Michael error can only occur if
462 * DecryptCRCErr not set (and TKIP is used). Experience
463 * indicates however that you can also get Michael errors
464 * when a CRC error is detected, but these are specious.
465 * Consequently we filter them out here so we don't
466 * confuse and/or complicate drivers.
468 if (ads.ds_rxstatus8 & AR_CRCErr)
469 rx_stats->rs_status |= HAL_RXERR_CRC;
470 else if (ads.ds_rxstatus8 & AR_PHYErr) {
473 rx_stats->rs_status |= HAL_RXERR_PHY;
474 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
475 rx_stats->rs_phyerr = phyerr;
476 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
477 rx_stats->rs_status |= HAL_RXERR_DECRYPT;
478 else if (ads.ds_rxstatus8 & AR_MichaelErr)
479 rx_stats->rs_status |= HAL_RXERR_MIC;
481 rx_stats->evm0=ads.AR_RxEVM0;
482 rx_stats->evm1=ads.AR_RxEVM1;
483 rx_stats->evm2=ads.AR_RxEVM2;
492 HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
494 struct ath_hal_5416 *ahp = AH5416(ah);
495 a_uint32_t txcfg, curLevel, newLevel;
499 * Disable interrupts while futzing with the fifo level.
501 omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
503 txcfg = OS_REG_READ(ah, AR_TXCFG);
504 curLevel = MS(txcfg, AR_FTRIG);
508 if (curLevel < MAX_TX_FIFO_THRESHOLD)
510 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
512 if (newLevel != curLevel)
513 OS_REG_WRITE(ah, AR_TXCFG,
514 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
516 /* re-enable chip interrupts */
517 ar5416SetInterrupts(ah, omask);
519 return (newLevel != curLevel);
522 HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
524 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
525 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
528 * Make sure that TXE is deasserted before setting the TXDP. If TXE
529 * is still asserted, setting TXDP will have no effect.
531 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
533 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
538 HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q)
540 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
541 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
543 /* Check to be sure we're not enabling a q that has its TXD bit set. */
544 HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
546 OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
551 a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
555 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
556 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
558 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
561 * Pending frame count (PFC) can momentarily go to zero
562 * while TXE remains asserted. In other words a PFC of
563 * zero is not sufficient to say that the queue has stopped.
565 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
569 if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
570 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
571 isrPrintf("RTSD on CAB queue\n");
572 /* Clear the ReadyTime shutdown status bits */
573 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
580 HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah)
585 * set txd on all queues
587 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
592 OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
593 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
594 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
597 * wait on all tx queues
599 for (q = 0; q < AR_NUM_QCU; q++) {
600 for (i = 0; i < AR5416_ABORT_LOOPS; i++) {
601 if (!ar5416NumTxPending(ah, q))
604 OS_DELAY(AR5416_ABORT_WAIT);
606 if (i == AR5416_ABORT_LOOPS) {
612 * clear tx abort bits
614 OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
615 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
616 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
621 OS_REG_WRITE(ah, AR_Q_TXD, 0);
626 HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q)
630 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
632 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
634 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
635 for (i = 1000; i != 0; i--) {
636 if (ar5416NumTxPending(ah, q) == 0)
638 OS_DELAY(100); /* XXX get actual value */
641 OS_REG_WRITE(ah, AR_Q_TXD, 0);
645 HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
650 a_uint32_t txRate0, a_uint32_t txTries0,
654 a_uint32_t rtsctsRate,
655 a_uint32_t rtsctsDuration,
656 a_uint32_t compicvLen,
657 a_uint32_t compivLen,
660 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
662 struct ar5416_desc *ads = AR5416DESC(ds);
666 ads->ds_txstatus9 &= ~AR_TxDone;
668 HALASSERT(txTries0 != 0);
669 HALASSERT(isValidPktType(type));
670 HALASSERT(isValidTxRate(txRate0));
671 HALASSERT((flags & RTSCTS) != RTSCTS);
676 ads->ds_ctl0 = (pktLen & AR_FrameLen)
677 | (txPower << AR_XmitPower_S)
678 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
679 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
680 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
682 ads->ds_ctl1 = (type << AR_FrameType_S)
683 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
684 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
685 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
687 ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
688 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
689 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
690 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
692 if (keyIx != HAL_TXKEYIX_INVALID) {
693 /* XXX validate key index */
694 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
695 ads->ds_ctl0 |= AR_DestIdxValid;
698 if (flags & RTSCTS) {
699 if (!isValidTxRate(rtsctsRate)) {
702 /* XXX validate rtsctsDuration */
703 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
704 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
705 ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
706 ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
713 HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
714 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
715 const struct ath_tx_desc *ds0)
717 struct ar5416_desc *ads = AR5416DESC(ds);
719 HALASSERT((segLen &~ AR_BufLen) == 0);
723 * First descriptor, don't clobber xmit control data
724 * setup by ar5416SetupTxDesc.
726 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
727 } else if (lastSeg) {
729 * Last descriptor in a multi-descriptor frame,
730 * copy the multi-rate transmit parameters from
731 * the first frame for processing on completion.
734 ads->ds_ctl1 = segLen;
735 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
736 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
739 * Intermediate descriptor in a multi-descriptor frame.
742 ads->ds_ctl1 = segLen | AR_TxMore;
746 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
751 HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
752 HAL_KEY_TYPE keyType)
754 struct ar5416_desc *ads = AR5416DESC(ds);
756 ads->ds_ctl6 = SM(keyType, AR_EncrType);
760 HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds)
762 struct ar5416_desc *ads = AR5416DESC(gds);
763 struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
765 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
766 return HAL_EINPROGRESS;
768 ads->ds_txstatus9 &= ~AR_TxDone;
770 /* Update software copies of the HW status */
771 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
772 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
773 ds->ds_txstat.ts_status = 0;
774 ds->ds_txstat.ts_flags = 0;
776 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
777 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
778 if (ads->ds_txstatus1 & AR_Filtered)
779 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
780 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
781 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
782 if (ads->ds_txstatus9 & AR_TxOpExceeded)
783 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
784 if (ads->ds_txstatus1 & AR_TxTimerExpired)
785 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
787 if (ads->ds_txstatus1 & AR_DescCfgErr)
788 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
789 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
790 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
791 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
793 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
794 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
795 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
797 if (ads->ds_txstatus0 & AR_TxBaStatus) {
798 ds->ds_txstat.ts_flags |= HAL_TX_BA;
799 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
800 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
804 * Extract the transmit rate used and mark the rate as
805 * ``alternate'' if it wasn't the series 0 rate.
807 ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
808 ds->ds_txstat.ts_rssi_combined =
809 MS(ads->ds_txstatus5, AR_TxRSSICombined);
810 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
811 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
812 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
813 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
814 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
815 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
816 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
817 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
818 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
819 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
820 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
821 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
822 ds->ds_txstat.ts_antenna = 0; /* ignored for owl */
827 void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
828 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
829 a_uint32_t keyIx, HAL_KEY_TYPE keyType,
832 struct ar5416_desc *ads = AR5416DESC(ds);
834 HALASSERT(isValidPktType(type));
835 HALASSERT(isValidKeyType(keyType));
840 ads->ds_ctl0 = (pktLen & AR_FrameLen)
841 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
842 | SM(txPower, AR_XmitPower)
843 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
844 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
845 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
846 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
847 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
848 | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0);
850 ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
851 | SM(type, AR_FrameType)
852 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
853 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
854 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
856 ads->ds_ctl6 = SM(keyType, AR_EncrType);
861 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
862 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
863 a_uint32_t rtsctsDuration,
864 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
867 struct ar5416_desc *ads = AR5416DESC(ds);
870 HALASSERT(nseries == 4);
874 * Rate control settings override
876 ds_ctl0 = ads->ds_ctl0;
878 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
879 if (flags & HAL_TXDESC_RTSENA) {
880 ds_ctl0 &= ~AR_CTSEnable;
881 ds_ctl0 |= AR_RTSEnable;
883 ds_ctl0 &= ~AR_RTSEnable;
884 ds_ctl0 |= AR_CTSEnable;
887 ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
890 ads->ds_ctl0 = ds_ctl0;
892 ads->ds_ctl2 = set11nTries(series, 0)
893 | set11nTries(series, 1)
894 | set11nTries(series, 2)
895 | set11nTries(series, 3)
896 | (durUpdateEn ? AR_DurUpdateEn : 0);
898 ads->ds_ctl3 = set11nRate(series, 0)
899 | set11nRate(series, 1)
900 | set11nRate(series, 2)
901 | set11nRate(series, 3);
903 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
904 | set11nPktDurRTSCTS(series, 1);
906 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
907 | set11nPktDurRTSCTS(series, 3);
909 ads->ds_ctl7 = set11nRateFlags(series, 0)
910 | set11nRateFlags(series, 1)
911 | set11nRateFlags(series, 2)
912 | set11nRateFlags(series, 3)
913 | SM(rtsctsRate, AR_RTSCTSRate);
918 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
919 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
920 a_uint32_t rtsctsDuration,
921 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
924 struct ar5416_desc *ads = AR5416DESC(ds);
927 HALASSERT(nseries == 4);
931 * Rate control settings override
933 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
934 ds_ctl0 = ads->ds_ctl0;
936 if (flags & HAL_TXDESC_RTSENA) {
937 ds_ctl0 &= ~AR_CTSEnable;
938 ds_ctl0 |= AR_RTSEnable;
940 ds_ctl0 &= ~AR_RTSEnable;
941 ds_ctl0 |= AR_CTSEnable;
944 ads->ds_ctl0 = ds_ctl0;
947 ads->ds_ctl2 = set11nTries(series, 0)
948 | set11nTries(series, 1)
949 | set11nTries(series, 2)
950 | set11nTries(series, 3)
951 | (durUpdateEn ? AR_DurUpdateEn : 0);
953 ads->ds_ctl3 = set11nRate(series, 0)
954 | set11nRate(series, 1)
955 | set11nRate(series, 2)
956 | set11nRate(series, 3);
958 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
959 | set11nPktDurRTSCTS(series, 1);
961 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
962 | set11nPktDurRTSCTS(series, 3);
964 ads->ds_ctl7 = set11nRateFlags(series, 0)
965 | set11nRateFlags(series, 1)
966 | set11nRateFlags(series, 2)
967 | set11nRateFlags(series, 3)
968 | SM(rtsctsRate, AR_RTSCTSRate);
973 void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t aggrLen,
974 a_uint32_t numDelims)
976 struct ar5416_desc *ads = AR5416DESC(ds);
978 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
980 ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
981 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
982 SM(numDelims, AR_PadDelim);
985 void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t numDelims)
987 struct ar5416_desc *ads = AR5416DESC(ds);
990 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
993 * We use a stack variable to manipulate ctl6 to reduce uncached
994 * read modify, modfiy, write.
997 ctl6 &= ~AR_PadDelim;
998 ctl6 |= SM(numDelims, AR_PadDelim);
1002 void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1004 struct ar5416_desc *ads = AR5416DESC(ds);
1006 ads->ds_ctl1 |= AR_IsAggr;
1007 ads->ds_ctl1 &= ~AR_MoreAggr;
1008 ads->ds_ctl6 &= ~AR_PadDelim;
1011 void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1013 struct ar5416_desc *ads = AR5416DESC(ds);
1015 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
1018 void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1019 a_uint32_t burstDuration)
1021 struct ar5416_desc *ads = AR5416DESC(ds);
1023 ads->ds_ctl2 &= ~AR_BurstDur;
1024 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
1027 void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1030 struct ar5416_desc *ads = AR5416DESC(ds);
1033 ads->ds_ctl0 |= AR_VirtMoreFrag;
1035 ads->ds_ctl0 &= ~AR_VirtMoreFrag;