target_firmware/wlan/ah.h

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #ifndef _ATH_AH_H_
  37 #define _ATH_AH_H_
  38
  39 #include <ah_osdep.h>
  40 #include <ah_desc.h>
  41
  42 #ifndef __ahdecl
  43 #define __ahdecl
  44 #endif
  45
  46 #define AR5416_DEVID_PCIE   0x0024  /* AR5416 PCI-E (XB) (Owl) */
  47 #define HAL_RATE_TABLE_SIZE 33
  48
  49 typedef enum {
  50         HAL_OK           = 0,    /* No error */
  51         HAL_ENXIO        = 1,    /* No hardware present */
  52         HAL_ENOMEM       = 2,    /* Memory allocation failed */
  53         HAL_EIO          = 3,    /* Hardware didn't respond as expected */
  54         HAL_EEMAGIC      = 4,    /* EEPROM magic number invalid */
  55         HAL_EEVERSION    = 5,    /* EEPROM version invalid */
  56         HAL_EELOCKED     = 6,    /* EEPROM unreadable */
  57         HAL_EEBADSUM     = 7,    /* EEPROM checksum invalid */
  58         HAL_EEREAD       = 8,    /* EEPROM read problem */
  59         HAL_EEBADMAC     = 9,    /* EEPROM mac address invalid */
  60         HAL_EESIZE       = 10,   /* EEPROM size not supported */
  61         HAL_EEWRITE      = 11,   /* Attempt to change write-locked EEPROM */
  62         HAL_EINVAL       = 12,   /* Invalid parameter to function */
  63         HAL_ENOTSUPP     = 13,   /* Hardware revision not supported */
  64         HAL_ESELFTEST    = 14,   /* Hardware self-test failed */
  65         HAL_EINPROGRESS  = 15,   /* Operation incomplete */
  66         HAL_FULL_RESET   = 16,   /* Full reset done */
  67 } HAL_STATUS;
  68
  69 typedef enum {
  70         AH_FALSE = 0,
  71         AH_TRUE  = 1,
  72 } HAL_BOOL;
  73
  74 typedef enum {
  75         HAL_CAP_VEOL        = 0,
  76         HAL_CAP_BSSIDMASK   = 1,
  77         HAL_CAP_TSF_ADJUST  = 2,
  78         HAL_CAP_HT          = 5,
  79         HAL_CAP_RTS_AGGR_LIMIT = 6,
  80 } HAL_CAPABILITY_TYPE;
  81
  82 typedef enum {
  83         HAL_M_STA       = 1,
  84         HAL_M_IBSS      = 0,
  85         HAL_M_HOSTAP    = 6,
  86         HAL_M_MONITOR   = 8,
  87 } HAL_OPMODE;
  88
  89 typedef enum {
  90         HAL_TX_QUEUE_INACTIVE   = 0,
  91         HAL_TX_QUEUE_DATA   = 1,
  92         HAL_TX_QUEUE_BEACON = 2,
  93         HAL_TX_QUEUE_CAB    = 3,
  94         HAL_TX_QUEUE_PSPOLL = 4,
  95         HAL_TX_QUEUE_UAPSD  = 5,
  96 } HAL_TX_QUEUE;
  97
  98 typedef enum {
  99         HAL_WME_AC_BK   = 0,
 100         HAL_WME_AC_BE   = 1,
 101         HAL_WME_AC_VI   = 2,
 102         HAL_WME_AC_VO   = 3,
 103         HAL_WME_UPSD    = 4,
 104         HAL_XR_DATA     = 5,
 105 } HAL_TX_QUEUE_SUBTYPE;
 106
 107 #define HAL_NUM_TX_QUEUES  10
 108
 109 typedef enum {
 110         HAL_PKT_TYPE_NORMAL = 0,
 111         HAL_PKT_TYPE_ATIM   = 1,
 112         HAL_PKT_TYPE_PSPOLL = 2,
 113         HAL_PKT_TYPE_BEACON = 3,
 114         HAL_PKT_TYPE_PROBE_RESP = 4,
 115         HAL_PKT_TYPE_CHIRP  = 5,
 116         HAL_PKT_TYPE_GRP_POLL = 6,
 117 } HAL_PKT_TYPE;
 118
 119 typedef enum {
 120         HAL_RX_CLEAR_CTL_LOW    = 0x1,    /* force control channel to appear busy */
 121         HAL_RX_CLEAR_EXT_LOW    = 0x2,    /* force extension channel to appear busy */
 122 } HAL_HT_RXCLEAR;
 123
 124 typedef enum {
 125         HAL_RX_FILTER_UCAST     = 0x00000001,   /* Allow unicast frames */
 126         HAL_RX_FILTER_MCAST     = 0x00000002,   /* Allow multicast frames */
 127         HAL_RX_FILTER_BCAST     = 0x00000004,   /* Allow broadcast frames */
 128         HAL_RX_FILTER_CONTROL   = 0x00000008,   /* Allow control frames */
 129         HAL_RX_FILTER_BEACON    = 0x00000010,   /* Allow beacon frames */
 130         HAL_RX_FILTER_PROM      = 0x00000020,   /* Promiscuous mode */
 131         HAL_RX_FILTER_XRPOLL    = 0x00000040,   /* Allow XR poll frmae */
 132         HAL_RX_FILTER_PROBEREQ  = 0x00000080,   /* Allow probe request frames */
 133         HAL_RX_FILTER_PHYERR    = 0x00000100,   /* Allow phy errors */
 134 #ifdef MAGPIE_MERLIN
 135         HAL_RX_FILTER_PHYRADAR  =  0x00002000, /* Allow phy radar errors*/
 136         HAL_RX_FILTER_PSPOLL    = 0x00004000,   /* Allow PSPOLL frames */
 137         /*
 138         ** PHY "Pseudo bits" should be in the upper 16 bits since the lower
 139         ** 16 bits actually correspond to register 0x803c bits
 140         */
 141 #else
 142         HAL_RX_FILTER_PHYRADAR  = 0x00000200,   /* Allow phy radar errors*/
 143 #endif
 144 } HAL_RX_FILTER;
 145
 146 #define CHANNEL_QUARTER 0x8000  /* Quarter rate channel */
 147 #define CHANNEL_HALF    0x4000  /* Half rate channel */
 148
 149 typedef enum {
 150         HAL_INT_RX      = 0x00000001,   /* Non-common mapping */
 151         HAL_INT_RXDESC  = 0x00000002,
 152         HAL_INT_RXNOFRM = 0x00000008,
 153         HAL_INT_RXEOL   = 0x00000010,
 154         HAL_INT_RXORN   = 0x00000020,
 155         HAL_INT_TX      = 0x00000040,   /* Non-common mapping */
 156         HAL_INT_TXDESC  = 0x00000080,
 157         HAL_INT_TXURN   = 0x00000800,
 158         HAL_INT_MIB     = 0x00001000,
 159         HAL_INT_RXPHY   = 0x00004000,
 160         HAL_INT_RXKCM   = 0x00008000,
 161         HAL_INT_SWBA    = 0x00010000,
 162         HAL_INT_BMISS   = 0x00040000,
 163         HAL_INT_BNR     = 0x00100000,   /* Non-common mapping */
 164         HAL_INT_GPIO    = 0x01000000,
 165         HAL_INT_CST     = 0x02000000,   /* Non-common mapping */
 166         HAL_INT_GTT     = 0x20000000,   /* Non-common mapping */
 167         HAL_INT_FATAL   = 0x40000000,   /* Non-common mapping */
 168         HAL_INT_GLOBAL  = 0x80000000,   /* Set/clear IER */
 169         HAL_INT_GENTIMER =0x08000000,   /* Non-common mapping */
 170
 171         /* Interrupt bits that map directly to ISR/IMR bits */
 172         HAL_INT_COMMON  = HAL_INT_RXNOFRM
 173         | HAL_INT_RXDESC
 174         | HAL_INT_RXEOL
 175         | HAL_INT_RXORN
 176         | HAL_INT_TXURN
 177         | HAL_INT_TXDESC
 178         | HAL_INT_MIB
 179         | HAL_INT_RXPHY
 180         | HAL_INT_RXKCM
 181         | HAL_INT_SWBA
 182         | HAL_INT_BMISS
 183         | HAL_INT_GPIO,
 184         HAL_INT_NOCARD  = 0xffffffff    /* To signal the card was removed */
 185 } HAL_INT;
 186
 187 #ifdef MAGPIE_MERLIN
 188
 189 #define HAL_RATESERIES_RTS_CTS    0x0001  /* use rts/cts w/this series */
 190 #define HAL_RATESERIES_2040       0x0002  /* use ext channel for series */
 191 #define HAL_RATESERIES_HALFGI     0x0004  /* use half-gi for series */
 192 #define HAL_RATESERIES_STBC       0x0008  /* use STBC for series */
 193
 194 /* 11n */
 195 typedef enum {
 196         HAL_HT_MACMODE_20   = 0,        /* 20 MHz operation */
 197         HAL_HT_MACMODE_2040 = 1,        /* 20/40 MHz operation */
 198 } HAL_HT_MACMODE;
 199
 200 typedef enum {
 201         HAL_HT_PHYMODE_20   = 0,        /* 20 MHz operation */
 202         HAL_HT_PHYMODE_2040 = 1,        /* 20/40 MHz operation */
 203 } HAL_HT_PHYMODE;
 204
 205 typedef enum {
 206         HAL_HT_EXTPROTSPACING_20 = 0,       /* 20 MHz spacing */
 207         HAL_HT_EXTPROTSPACING_25 = 1,       /* 25 MHz spacing */
 208 } HAL_HT_EXTPROTSPACING;
 209
 210 typedef struct {
 211         HAL_HT_MACMODE          ht_macmode;     /* MAC - 20/40 mode */
 212         HAL_HT_PHYMODE          ht_phymode;     /* PHY - 20/40 mode */
 213         a_int8_t                ht_extoff;      /* ext channel offset */
 214         HAL_HT_EXTPROTSPACING   ht_extprotspacing;  /* ext channel protection spacing */
 215 } HAL_HT_CWM;
 216
 217 typedef struct {
 218         a_uint8_t ht_txchainmask; /* tx chain mask    */
 219         a_uint8_t ht_rxchainmask; /* rx chain mask    */
 220 } HAL_HT_MISC;
 221
 222 typedef struct {
 223         HAL_HT_CWM  cwm;
 224         HAL_HT_MISC misc;
 225 } HAL_HT;
 226
 227 /* channelFlags */
 228 #define CHANNEL_CW_INT  0x0002  /* CW interference detected on channel */
 229 #define CHANNEL_TURBO   0x0010  /* Turbo Channel */
 230 #define CHANNEL_CCK     0x0020  /* CCK channel */
 231 #define CHANNEL_OFDM    0x0040  /* OFDM channel */
 232 #define CHANNEL_2GHZ    0x0080  /* 2 GHz spectrum channel. */
 233 #define CHANNEL_5GHZ    0x0100  /* 5 GHz spectrum channel */
 234 #define CHANNEL_PASSIVE 0x0200  /* Only passive scan allowed in the channel */
 235 #define CHANNEL_DYN     0x0400  /* dynamic CCK-OFDM channel */
 236 #define CHANNEL_XR      0x0800  /* XR channel */
 237 #define CHANNEL_STURBO  0x2000  /* Static turbo, no 11a-only usage */
 238 #define CHANNEL_HALF    0x4000  /* Half rate channel */
 239 #define CHANNEL_QUARTER 0x8000  /* Quarter rate channel */
 240 #define CHANNEL_HT20    0x10000 /* HT20 channel */
 241 #define CHANNEL_HT40    0x20000 /* HT40 channel */
 242 #define CHANNEL_HT40U   0x40000 /* control channel can be upper channel */
 243 #define CHANNEL_HT40L   0x80000 /* control channel can be lower channel */
 244
 245 /* privFlags */
 246 #define CHANNEL_INTERFERENCE    0x01
 247 #define CHANNEL_DFS             0x02 /* DFS required on channel */
 248 #define CHANNEL_4MS_LIMIT       0x04 /* 4msec packet limit on this channel */
 249 #define CHANNEL_DFS_CLEAR       0x08 /* if channel has been checked for DFS */
 250
 251 #define CHANNEL_A       (CHANNEL_5GHZ|CHANNEL_OFDM)
 252 #define CHANNEL_B       (CHANNEL_2GHZ|CHANNEL_CCK)
 253 #define CHANNEL_PUREG   (CHANNEL_2GHZ|CHANNEL_OFDM)
 254 #define CHANNEL_G       (CHANNEL_2GHZ|CHANNEL_OFDM)
 255 #define CHANNEL_T       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
 256 #define CHANNEL_ST      (CHANNEL_T|CHANNEL_STURBO)
 257 #define CHANNEL_108G    (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
 258 #define CHANNEL_108A    CHANNEL_T
 259 #define CHANNEL_X       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
 260
 261 #define CHANNEL_G_HT20  (CHANNEL_2GHZ|CHANNEL_HT20)
 262 #define CHANNEL_A_HT20  (CHANNEL_5GHZ|CHANNEL_HT20)
 263 #define CHANNEL_G_HT40  (CHANNEL_2GHZ|CHANNEL_HT20|CHANNEL_HT40)
 264 #define CHANNEL_A_HT40  (CHANNEL_5GHZ|CHANNEL_HT20|CHANNEL_HT40)
 265 #define CHANNEL_ALL                             \
 266         (CHANNEL_OFDM |                         \
 267          CHANNEL_CCK |                          \
 268          CHANNEL_2GHZ |                         \
 269          CHANNEL_5GHZ |                         \
 270          CHANNEL_TURBO |                        \
 271          CHANNEL_HT20 |                         \
 272          CHANNEL_HT40)
 273 #define CHANNEL_ALL_NOTURBO     (CHANNEL_ALL &~ CHANNEL_TURBO)
 274
 275 typedef struct {
 276         a_int32_t    rateCount;
 277         a_uint8_t    rateCodeToIndex[HAL_RATE_TABLE_SIZE];
 278         struct {
 279                 a_uint8_t    valid;
 280                 a_uint8_t    phy;
 281                 a_int16_t    txPower;
 282                 a_int16_t    txPower2Chains;
 283                 a_int16_t    txPower3Chains;
 284                 a_uint32_t   rateKbps;
 285                 a_uint8_t    rateCode;
 286                 a_uint8_t    shortPreamble;
 287                 a_uint8_t    dot11Rate;
 288                 a_uint8_t    controlRate;
 289                 a_uint16_t   lpAckDuration;
 290                 a_uint16_t   spAckDuration;
 291         } info[HAL_RATE_TABLE_SIZE];
 292 } HAL_RATE_TABLE;
 293
 294 typedef struct {
 295         a_uint32_t   Tries;
 296         a_uint32_t   Rate;
 297         a_uint32_t   PktDuration;
 298         a_uint32_t   ChSel;
 299         a_uint32_t   RateFlags;
 300         a_uint32_t   RateIndex;
 301         a_uint32_t   TxPowerCap;     /* in 1/2 dBm units */
 302 } HAL_11N_RATE_SERIES;
 303
 304 #else
 305
 306 typedef struct {
 307         a_int32_t    rateCount;
 308         a_uint8_t    rateCodeToIndex[HAL_RATE_TABLE_SIZE];
 309         struct {
 310                 a_uint8_t    valid;
 311                 a_uint8_t    phy;
 312                 a_uint32_t   rateKbps;
 313                 a_uint8_t    rateCode;
 314                 a_uint8_t    shortPreamble;
 315                 a_uint8_t    dot11Rate;
 316                 a_uint8_t    controlRate;
 317                 a_uint16_t   lpAckDuration;
 318                 a_uint16_t   spAckDuration;
 319         } info[HAL_RATE_TABLE_SIZE];
 320 } HAL_RATE_TABLE;
 321
 322 #define HAL_RATESERIES_RTS_CTS    0x0001  /* use rts/cts w/this series */
 323 #define HAL_RATESERIES_2040       0x0002  /* use ext channel for series */
 324 #define HAL_RATESERIES_HALFGI     0x0004  /* use half-gi for series */
 325 #define HAL_RATESERIES_STBC       0x0008  /* use STBC for series */
 326
 327 typedef struct {
 328         a_uint32_t   Tries;
 329         a_uint32_t   Rate;
 330         a_uint32_t   PktDuration;
 331         a_uint32_t   ChSel;
 332         a_uint32_t   RateFlags;
 333 } HAL_11N_RATE_SERIES;
 334
 335 #endif
 336
 337 enum {
 338         HAL_MODE_11A    = 0x001,        /* 11a channels */
 339         HAL_MODE_TURBO  = 0x002,        /* 11a turbo-only channels */
 340         HAL_MODE_11B    = 0x004,        /* 11b channels */
 341         HAL_MODE_PUREG  = 0x008,        /* 11g channels (OFDM only) */
 342         HAL_MODE_11G    = 0x008,        /* XXX historical */
 343         HAL_MODE_108G   = 0x020,        /* 11a+Turbo channels */
 344         HAL_MODE_108A   = 0x040,        /* 11g+Turbo channels */
 345         HAL_MODE_XR     = 0x100,        /* XR channels */
 346         HAL_MODE_11A_HALF_RATE = 0x200,     /* 11A half rate channels */
 347         HAL_MODE_11A_QUARTER_RATE = 0x400,  /* 11A quarter rate channels */
 348         HAL_MODE_11NG   = 0x4000,           /* 11ng channels */
 349         HAL_MODE_11NA   = 0x8000,           /* 11na channels */
 350         HAL_MODE_ALL    = 0xffff
 351 };
 352
 353 typedef enum {
 354         HAL_KEY_TYPE_CLEAR,
 355         HAL_KEY_TYPE_WEP,
 356         HAL_KEY_TYPE_AES,
 357         HAL_KEY_TYPE_TKIP,
 358         HAL_KEY_TYPE_WAPI,
 359 } HAL_KEY_TYPE;
 360
 361 struct ath_desc;
 362 struct ath_rx_status;
 363
 364 struct ath_hal
 365 {
 366         a_uint32_t ah_magic;
 367         HAL_SOFTC ah_sc;
 368         adf_os_device_t ah_dev;
 369
 370         a_uint32_t ah_macVersion;
 371         a_uint16_t ah_macRev;
 372         a_uint16_t ah_phyRev;
 373         const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
 374                                                          a_uint32_t mode);
 375         void      __ahdecl(*ah_detach)(struct ath_hal*);
 376         HAL_BOOL  __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
 377                                                   HAL_BOOL incTrigLevel);
 378
 379         /* Misc Functions */
 380         void      __ahdecl(*ah_setDefAntenna)(struct ath_hal*, a_uint32_t);
 381         void      __ahdecl(*ah_setRxFilter)(struct ath_hal*, a_uint32_t);
 382
 383
 384         /* Target Transmit Functions */
 385         HAL_BOOL  __ahdecl(*ah_setTxDP)(struct ath_hal*, a_uint32_t, a_uint32_t txdp);
 386         a_uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, a_uint32_t q);
 387         HAL_BOOL  __ahdecl(*ah_startTxDma)(struct ath_hal*, a_uint32_t);
 388         HAL_BOOL  __ahdecl(*ah_stopTxDma)(struct ath_hal*, a_uint32_t);
 389
 390         HAL_BOOL  __ahdecl(*ah_abortTxDma)(struct ath_hal *);
 391
 392         void      __ahdecl(*ah_set11nTxDesc)(struct ath_tx_desc *ds,
 393                                              a_uint32_t pktLen, HAL_PKT_TYPE type,
 394                                              a_uint32_t txPower, a_uint32_t keyIx,
 395                                              HAL_KEY_TYPE keyType,
 396                                              a_uint32_t flags);
 397         void      __ahdecl(*ah_set11nRateScenario)(struct ath_hal *ah,
 398                                                    struct ath_tx_desc *ds,
 399                                                    a_uint32_t durUpdateEn,
 400                                                    a_uint32_t rtsctsRate,
 401                                                    a_uint32_t rtsctsDuration,
 402                                                    HAL_11N_RATE_SERIES series[],
 403                                                    a_uint32_t nseries, a_uint32_t flags);
 404         void      __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *ah,
 405                                                 struct ath_tx_desc *ds, a_uint32_t aggrLen,
 406                                                 a_uint32_t numDelims);
 407         void      __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *ah,
 408                                                  struct ath_tx_desc *ds, a_uint32_t numDelims);
 409         void      __ahdecl(*ah_set11nAggrLast)(struct ath_hal *ah,
 410                                                struct ath_tx_desc *ds);
 411         void      __ahdecl(*ah_clr11nAggr)(struct ath_hal *ah,
 412                                            struct ath_tx_desc *ds);
 413         void      __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *ah,
 414                                                     struct ath_tx_desc *ds,
 415                                                     a_uint32_t burstDuration);
 416         void      __ahdecl(*ah_set11nVirtualMoreFrag)(struct ath_hal *ah,
 417                                                       struct ath_tx_desc *ds, a_uint32_t vmf);
 418
 419         HAL_BOOL  __ahdecl(*ah_setupTxDesc)(struct ath_tx_desc *,
 420                                             a_uint32_t pktLen, a_uint32_t hdrLen,
 421                                             HAL_PKT_TYPE type, a_uint32_t txPower,
 422                                             a_uint32_t txRate0, a_uint32_t txTries0,
 423                                             a_uint32_t keyIx, a_uint32_t flags,
 424                                             a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration);
 425         HAL_BOOL  __ahdecl(*ah_fillTxDesc)(struct ath_tx_desc *,
 426                                            a_uint32_t segLen, HAL_BOOL firstSeg,
 427                                            HAL_BOOL lastSeg, const struct ath_tx_desc *);
 428         HAL_BOOL  __ahdecl (*ah_fillKeyTxDesc) (struct ath_tx_desc *, HAL_KEY_TYPE);
 429         HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_tx_desc *);
 430         HAL_BOOL  __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const a_uint8_t*);
 431         void      __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
 432         void      __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
 433                                                    a_uint32_t filter0, a_uint32_t filter1);
 434
 435         u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
 436
 437         /* Target receive Functions */
 438         void       __ahdecl(*ah_setRxDP)(struct ath_hal*, a_uint32_t rxdp);
 439         HAL_BOOL  __ahdecl(*ah_setupRxDesc)(struct ath_rx_desc *,
 440                                             a_uint32_t size, a_uint32_t flags);
 441         HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *,
 442                                             a_uint32_t phyAddr, struct ath_desc *next, u_int64_t tsf);
 443         HAL_STATUS __ahdecl(*ah_procRxDescFast)(struct ath_hal *ah,
 444                                                 struct ath_rx_desc *ds, a_uint32_t pa,
 445                                                 struct ath_desc *nds,
 446                                                 struct ath_rx_status *rx_stats);
 447         HAL_BOOL  __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
 448         void      __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
 449         void      __ahdecl(*ah_enableReceive)(struct ath_hal*);
 450
 451         /* Interrupt functions */
 452         HAL_BOOL  __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
 453         HAL_BOOL  __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
 454         HAL_INT   __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
 455 };
 456
 457
 458 extern struct ath_hal * __ahdecl ath_hal_attach_tgt(a_uint32_t devid, HAL_SOFTC,
 459                                                     adf_os_device_t dev,
 460                                                     a_uint32_t flags, HAL_STATUS* status);
 461
 462 extern a_uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
 463                                                  const HAL_RATE_TABLE *rates,
 464                                                  a_uint32_t frameLen,
 465                                                  a_uint16_t rateix,
 466                                                  HAL_BOOL shortPreamble);
 467 #endif /* _ATH_AH_H_ */