target_firmware/magpie_fw_dev/target/rompatch/usb_api_patch.c

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35 #include "usb_defs.h"
  36 #include "usb_type.h"
  37 #include "usb_pre.h"
  38 #include "usb_extr.h"
  39 #include "usb_std.h"
  40 #include "reg_defs.h"
  41 #include "athos_api.h"
  42 #include "usbfifo_api.h"
  43
  44 #include "sys_cfg.h"
  45
  46 #define measure_time 0
  47 #define measure_time_pll 10000000
  48
  49 typedef void (* USBFIFO_recv_command)(VBUF *cmd);
  50
  51 extern Action eUsbCxFinishAction;
  52 extern CommandType eUsbCxCommand;
  53 extern BOOLEAN UsbChirpFinish;
  54 extern USB_FIFO_CONFIG usbFifoConf;
  55 extern uint16_t *pu8DescriptorEX;
  56 extern uint16_t u16TxRxCounter;
  57
  58 USBFIFO_recv_command m_origUsbfifoRecvCmd = NULL;
  59
  60 void zfTurnOffPower_patch(void);
  61
  62 static void _fw_reset_dma_fifo();
  63 static void _fw_restore_dma_fifo();
  64 static void _fw_power_on();
  65 static void _fw_power_off();
  66
  67 BOOLEAN bEepromExist = TRUE;
  68 BOOLEAN bJumptoFlash = FALSE;
  69
  70 void _fw_usbfifo_recv_command(VBUF *buf)
  71 {
  72         A_UINT8 *cmd_data;
  73         A_UINT32 tmp;
  74
  75         cmd_data = (A_UINT8 *)(buf->desc_list->buf_addr + buf->desc_list->data_offset);
  76         tmp = *((A_UINT32 *)cmd_data);
  77         if ( tmp == 0xFFFFFFFF ) {
  78                 // reset usb/wlan dma
  79                 _fw_reset_dma_fifo();
  80
  81                 // restore gpio setting and usb/wlan dma state
  82                 _fw_restore_dma_fifo();
  83
  84                 // set clock to bypass mode - 40Mhz from XTAL
  85                 HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4));
  86
  87                 A_DELAY_USECS(100); // wait for stable
  88
  89                 HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));
  90
  91                 A_DELAY_USECS(100); // wait for stable
  92                 A_UART_HWINIT((40*1000*1000), 19200);
  93
  94                 A_CLOCK_INIT(40);
  95
  96                 if (!bEepromExist) { //jump to flash boot (eeprom data in flash)
  97                         bJumptoFlash = TRUE;
  98                         A_PRINTF("Jump to Flash BOOT\n");
  99                         app_start();
 100                 }else{
 101                         A_PRINTF("receive the suspend command...\n");
 102                         // reboot.....
 103                         A_USB_JUMP_BOOT();
 104                 }
 105
 106         } else {
 107                 m_origUsbfifoRecvCmd(buf);
 108         }
 109 }
 110
 111 void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig)
 112 {
 113         m_origUsbfifoRecvCmd = pConfig->recv_command;
 114
 115         usbFifoConf.get_command_buf = pConfig->get_command_buf;
 116         usbFifoConf.recv_command    = _fw_usbfifo_recv_command;
 117         usbFifoConf.get_event_buf   = pConfig->get_event_buf;
 118         usbFifoConf.send_event_done = pConfig->send_event_done;
 119 }
 120
 121 #define PCI_RC_RESET_BIT                            BIT6
 122 #define PCI_RC_PHY_RESET_BIT                        BIT7
 123 #define PCI_RC_PLL_RESET_BIT                        BIT8
 124 #define PCI_RC_PHY_SHIFT_RESET_BIT                  BIT10
 125
 126
 127 /*
 128  * -- urn_off_merlin --
 129  * . values suggested from Lalit
 130  *
 131  */
 132 static void turn_off_merlin()
 133 {
 134         volatile uint32_t default_data[9];
 135         uint32_t i=0;
 136
 137         if(1)
 138         {
 139                 A_PRINTF("turn_off_merlin_ep_start ......\n");
 140                 A_DELAY_USECS(measure_time);
 141                 default_data[0] = 0x9248fd00;
 142                 default_data[1] = 0x24924924;
 143                 default_data[2] = 0xa8000019;
 144                 default_data[3] = 0x17160820;
 145                 default_data[4] = 0x25980560;
 146                 default_data[5] = 0xc1c00000;
 147                 default_data[6] = 0x1aaabe40;
 148                 default_data[7] = 0xbe105554;
 149                 default_data[8] = 0x00043007;
 150
 151                 for(i=0; i<9; i++)
 152                 {
 153                         A_DELAY_USECS(10);
 154
 155                         HAL_WORD_REG_WRITE( 0x10ff4040, default_data[i]);
 156                 }
 157                 A_DELAY_USECS(10);
 158                 HAL_WORD_REG_WRITE(0x10ff4044, BIT0);
 159                 A_PRINTF("turn_off_merlin_ep_end ......\n");
 160         }
 161 }
 162
 163 /*
 164  * -- turn_off_phy --
 165  *
 166  * . write shift register to both pcie ep and rc
 167  * .
 168  */
 169
 170 static void turn_off_phy()
 171 {
 172
 173         volatile uint32_t default_data[9];
 174         volatile uint32_t read_data = 0;
 175         uint32_t i=0;
 176
 177         default_data[0] = 0x9248fd00;
 178         default_data[1] = 0x24924924;
 179         default_data[2] = 0xa8000019;
 180         default_data[3] = 0x17160820;
 181         default_data[4] = 0x25980560;
 182         default_data[5] = 0xc1c00000;
 183         default_data[6] = 0x1aaabe40;
 184         default_data[7] = 0xbe105554;
 185         default_data[8] = 0x00043007;
 186
 187         for(i=0; i<9; i++)
 188         {
 189                 // check for the done bit to be set
 190
 191                 while (1)
 192                 {
 193                         read_data=HAL_WORD_REG_READ(0x40028);
 194                         if( read_data & BIT31 )
 195                                 break;
 196                 }
 197
 198                 A_DELAY_USECS(1);
 199
 200                 HAL_WORD_REG_WRITE( 0x40024, default_data[i]);
 201         }
 202         HAL_WORD_REG_WRITE(0x40028, BIT0);
 203 }
 204
 205 static void turn_off_phy_rc()
 206 {
 207
 208         volatile uint32_t default_data[9];
 209         volatile uint32_t read_data = 0;
 210         uint32_t i=0;
 211
 212         A_PRINTF("turn_off_phy_rc\n");
 213
 214         default_data[0] = 0x9248fd00;
 215         default_data[1] = 0x24924924;
 216         default_data[2] = 0xa8000019;
 217         default_data[3] = 0x13160820;//PwdClk1MHz=0
 218         default_data[4] = 0x25980560;
 219         default_data[5] = 0xc1c00000;
 220         default_data[6] = 0x1aaabe40;
 221         default_data[7] = 0xbe105554;
 222         default_data[8] = 0x00043007;
 223
 224         for(i=0; i<9; i++)
 225         {
 226                 // check for the done bit to be set
 227
 228                 while (1)
 229                 {
 230                         read_data=HAL_WORD_REG_READ(0x40028);
 231                         if( read_data & BIT31 )
 232                                 break;
 233                 }
 234
 235                 A_DELAY_USECS(1);
 236
 237                 HAL_WORD_REG_WRITE( 0x40024, default_data[i]);
 238         }
 239         HAL_WORD_REG_WRITE(0x40028, BIT0);
 240 }
 241
 242 volatile uint32_t gpio_func = 0x0;
 243 volatile uint32_t gpio = 0x0;
 244
 245 /*
 246  * -- patch zfTurnOffPower --
 247  *
 248  * . set suspend counter to non-zero value
 249  * .
 250  */
 251 void zfTurnOffPower_patch(void)
 252 {
 253         A_PRINTF("+++ goto suspend ......\n");
 254
 255         // setting the go suspend here, power down right away...
 256         HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8));
 257
 258         A_DELAY_USECS(100);
 259
 260         // TURN OFF ETH PLL
 261         _fw_power_off();
 262
 263         //32clk wait for External ETH PLL stable
 264         A_DELAY_USECS(100);
 265
 266         HAL_WORD_REG_WRITE(0x52000, 0x70303);//read back 0x703f7
 267         HAL_WORD_REG_WRITE(0x52008, 0x0e91c);//read back 0x1e948
 268
 269         HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
 270                            (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(BIT0))); //0x56030
 271         // wake up, and turn on cpu, eth, pcie and usb pll
 272         _fw_power_on();
 273         // restore gpio and other settings
 274         _fw_restore_dma_fifo();
 275
 276         // clear suspend..................
 277         HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
 278                            (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)&(~BIT0)));
 279         HAL_WORD_REG_WRITE(0x52028, HAL_WORD_REG_READ(0x52028)&(~(BIT8|BIT12|BIT16)));
 280 }
 281
 282 /*
 283  * -- patch zfResetUSBFIFO_patch --
 284  *
 285  * . clear ep3/ep4 fifo
 286  * . set suspend magic pattern
 287  * . reset pcie ep phy
 288  * . reset pcie rc phy
 289  * . turn off pcie pll
 290  * . reset all pcie/gmac related registers
 291  * . reset usb dma
 292  */
 293 void zfResetUSBFIFO_patch(void)
 294 {
 295         A_PRINTF("0x9808  0x%x ......\n", HAL_WORD_REG_READ(0x10ff9808));
 296         A_PRINTF("0x7890  0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890));
 297         A_PRINTF("0x7890  0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890));
 298         A_PRINTF("0x4088  0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
 299         _fw_reset_dma_fifo();
 300 }
 301
 302 static void _fw_reset_dma_fifo()
 303 {
 304         HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
 305         HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10));
 306         A_PRINTF("_fw_reset_dma_fifo\n");
 307
 308         // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!!
 309         mUSB_STATUS_IN_INT_DISABLE();
 310
 311         // update magic pattern to indicate this is a suspend
 312         HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, SUS_MAGIC_PATTERN);
 313
 314         A_PRINTF("org 0x4048  0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048));
 315         A_PRINTF("org 0x404C  0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C));
 316         A_PRINTF("org 0x4088  0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
 317
 318         HAL_WORD_REG_WRITE(0x10ff4088,0xaaa6a);//1010.1010.1010.0110.1010 for UB94
 319         HAL_WORD_REG_WRITE(0x10ff404C,0x0);
 320
 321         A_DELAY_USECS(1000);
 322         A_PRINTF("0x4048  0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048));
 323         A_PRINTF("0x404C  0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C));
 324         A_PRINTF("0x4088  0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
 325
 326         // turn off merlin
 327         turn_off_merlin();
 328         // pcie ep
 329         A_PRINTF("turn_off_magpie_ep_start ......\n");
 330         A_DELAY_USECS(measure_time);
 331         HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)|BIT0|(1<<1)));
 332         turn_off_phy();
 333         HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&~(BIT0|(1<<1))));
 334         A_PRINTF("turn_off_magpie_ep_end ......\n");
 335
 336         // pcie rc
 337         A_PRINTF("turn_off_magpie_rc_start ......\n");
 338         A_DELAY_USECS(measure_time);
 339         HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&(~BIT0)));
 340         turn_off_phy_rc();
 341         A_PRINTF("turn_off_magpie_rc_end ......down\n");
 342         A_DELAY_USECS(measure_time);
 343
 344         A_PRINTF("0x4001C  %p ......\n", HAL_WORD_REG_READ(0x4001c));
 345         A_PRINTF("0x40040  %p ......\n", HAL_WORD_REG_READ(0x40040));
 346
 347         // turn off pcie_pll - power down (bit16)
 348         A_PRINTF(" before pwd PCIE PLL CFG:0x5601C  %p ......\n", HAL_WORD_REG_READ(0x5601C));
 349         HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)|(BIT18)));
 350         A_PRINTF(" after pwd PCIE PLL CFG:0x5601C  %p ......\n", HAL_WORD_REG_READ(0x5601C));
 351
 352         /* set everything to reset state?, requested by Oligo */
 353         HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)|(BIT13|BIT12|BIT11|BIT9|BIT7|BIT6));
 354
 355         HAL_WORD_REG_WRITE(0x5C000, 0);
 356
 357         A_DELAY_USECS(10);
 358
 359         // reset usb DMA controller
 360         HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x0);
 361
 362         HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT4)));
 363         A_DELAY_USECS(5);
 364         HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~BIT4)));
 365
 366
 367         HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x1);
 368 }
 369
 370 static void _fw_power_off()
 371 {
 372         /*
 373          *  1. set CPU bypass
 374          *  2. turn off CPU PLL
 375          *  3. turn off ETH PLL
 376          *  4. disable ETH PLL bypass and update
 377          *  4.1 set suspend timeout
 378          *  5. set SUSPEND_ENABLE
 379          */
 380
 381         HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4)); //0x56004
 382
 383         A_DELAY_USECS(100); // wait for stable
 384
 385         HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));//0x56000
 386
 387         A_DELAY_USECS(100); // wait for stable
 388
 389         A_UART_HWINIT((40*1000*1000), 19200);
 390         A_CLOCK_INIT(40);
 391
 392         HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR,
 393                            (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)|(BIT16)));   //0x5600c
 394
 395         HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,
 396                            (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)|(BIT4|BIT0))); //0x56010
 397
 398         HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
 399                            (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(0x10<<8))); //0x56030
 400 }
 401
 402 static void _fw_power_on()
 403 {
 404     /*
 405      *  1. turn on CPU PLL
 406      *  2. disable CPU bypass
 407      *  3. turn on ETH PLL
 408      *  4. disable ETH PLL bypass and update
 409      *  5. turn on pcie pll
 410      */
 411
 412         HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR,
 413                            (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)&(~BIT16)));
 414
 415         // deassert eth_pll bypass mode and trigger update bit
 416         HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,
 417                            (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)&(~(BIT4|BIT0))));
 418 }
 419
 420 #define CMD_PCI_RC_RESET_ON() HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \
 421                          (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)| \
 422                           (PCI_RC_PHY_SHIFT_RESET_BIT|PCI_RC_PLL_RESET_BIT|PCI_RC_PHY_RESET_BIT|PCI_RC_RESET_BIT)))
 423
 424 static void _fw_restore_dma_fifo(void)
 425 {
 426         HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)&(~(BIT18))));
 427
 428         // reset pcie_rc shift
 429         HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~(BIT10|BIT8|BIT7))));
 430         A_DELAY_USECS(1);
 431         HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT10|BIT8|BIT7)));
 432
 433         // reset pci_rc phy
 434         CMD_PCI_RC_RESET_ON();
 435         A_DELAY_USECS(20);
 436
 437         // enable dma swap function
 438         MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
 439         MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
 440         MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
 441         MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
 442 }
 443
 444 extern uint16_t *u8ConfigDescriptorEX;
 445 extern uint16_t *pu8DescriptorEX;
 446 extern uint16_t u16TxRxCounter;
 447 extern SetupPacket    ControlCmd;
 448
 449 extern uint16_t *u8UsbDeviceDescriptor;
 450
 451 extern BOOLEAN bGet_descriptor(void);
 452
 453 uint16_t ConfigDescriptorPatch[30];
 454
 455 uint16_t UsbDeviceDescriptorPatch[9];
 456 #define BCD_DEVICE_OFFSET               6
 457 #define BCD_DEVICE_FW_SIGNATURE         0xffff
 458 #define VENDOR_ID_OFFSET                4
 459 #define PRODUCT_ID_OFFSET               5
 460
 461 #define EP3_TRANSFER_TYPE_OFFSET    17
 462 #define EP3_INT_INTERVAL            19
 463 #define EP4_TRANSFER_TYPE_OFFSET    21
 464 #define EP4_INT_INTERVAL            22
 465
 466
 467
 468  #define A_SFLASH_READ_4B(u32Data, start_addr) u32Data = *(uint32_t *)(0xf000000+start_addr);
 469  #define FLASH_SIZE 0x800000 //8M
 470  #define FLASH_USB_VENDOR_ID_OFFSET     0x86
 471  #define FLASH_USB_PRODUCT_ID_OFFSET    0x87
 472
 473  // flash reserved size for saving eeprom data is 4K.
 474  #define EE_DATA_RESERVED_LEN 0x1000 //4K
 475
 476 #define mLOW_MASK(u16)          ((uint8_t) ((u16) & mMASK(8)))
 477 #define mHIGH_MASK(u16)         ((uint8_t) ((u16) & ~mMASK(8)))
 478
 479 /* (1234) -> 0034 */
 480 //#define mLOW_BYTE(u16)          ((U_8)(u16))
 481 #define mLOW_BYTE(u16)          mLOW_MASK(u16)
 482 /* (1234) -> 0012 */
 483 #define mHIGH_BYTE(u16)         ((uint8_t) (((uint16_t) (u16)) >> 8))
 484
 485 #define mLOW_WORD0(u32)         ((uint16_t) ((u32) & 0xFFFF))
 486 #define mHIGH_WORD0(u32)        ((uint16_t) ((u32) >> 16))
 487
 488 /* (1234) -> 3412 */
 489 #define mSWAP_BYTE(u16)         ((mLOW_MASK(u16) << 8) | mHIGH_BYTE(u16))
 490
 491 BOOLEAN bGet_descriptor_patch(void)
 492 {
 493         if (mDEV_REQ_VALUE_HIGH() == 1)
 494         {
 495                 uint8_t *p = (uint8_t *)u8UsbDeviceDescriptor;
 496                 uint32_t u32Tmp=0;
 497                 /* Copy Usb Device Descriptor */
 498                 ath_hal_memcpy(UsbDeviceDescriptorPatch, p, sizeof(UsbDeviceDescriptorPatch));
 499
 500                 UsbDeviceDescriptorPatch[BCD_DEVICE_OFFSET] =
 501                         BCD_DEVICE_FW_SIGNATURE;
 502
 503                 /* Patch for custom id from flash */
 504                 if (bEepromExist == FALSE) {
 505                         A_SFLASH_READ_4B(u32Tmp, FLASH_SIZE -
 506                                 EE_DATA_RESERVED_LEN + FLASH_USB_VENDOR_ID_OFFSET*2);
 507                         UsbDeviceDescriptorPatch[VENDOR_ID_OFFSET] =
 508                                 mSWAP_BYTE(mLOW_WORD0(u32Tmp));
 509                         UsbDeviceDescriptorPatch[PRODUCT_ID_OFFSET] =
 510                                 mSWAP_BYTE(mHIGH_WORD0(u32Tmp));
 511                 }
 512
 513                 pu8DescriptorEX = UsbDeviceDescriptorPatch;
 514                 u16TxRxCounter = mTABLE_LEN(u8UsbDeviceDescriptor[0]);
 515
 516                 if (u16TxRxCounter > mDEV_REQ_LENGTH())
 517                         u16TxRxCounter = mDEV_REQ_LENGTH();
 518
 519                 A_USB_EP0_TX_DATA();
 520
 521                 //u16TxRxCounter = 18;
 522                 return TRUE;
 523         }
 524         if (mDEV_REQ_VALUE_HIGH() == 2) {
 525                 uint8_t *p = (uint8_t *)u8ConfigDescriptorEX;
 526
 527                 /* Copy ConfigDescriptor */
 528                 ath_hal_memcpy(ConfigDescriptorPatch, p, sizeof(ConfigDescriptorPatch));
 529
 530                  /* place holder for EPx patches */
 531
 532                 switch (mDEV_REQ_VALUE_LOW())
 533                 {
 534                 case 0x00:      // configuration no: 0
 535                         pu8DescriptorEX = ConfigDescriptorPatch;
 536                         u16TxRxCounter = ConfigDescriptorPatch[1];
 537                         //u16TxRxCounter = 46;
 538                         break;
 539                 default:
 540                         return FALSE;
 541                 }
 542
 543                 if (u16TxRxCounter > mDEV_REQ_LENGTH())
 544                         u16TxRxCounter = mDEV_REQ_LENGTH();
 545
 546                 A_USB_EP0_TX_DATA();
 547                 return TRUE;
 548         }
 549         else {
 550                 return bGet_descriptor();
 551         }
 552 }
 553