target_firmware/magpie_fw_dev/target/rompatch/usb_api_patch.c

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35 #include "usb_defs.h"
  36 #include "usb_type.h"
  37 #include "usb_pre.h"
  38 #include "usb_extr.h"
  39 #include "usb_std.h"
  40 #include "reg_defs.h"
  41 #include "athos_api.h"
  42 #include "usbfifo_api.h"
  43
  44 #include "sys_cfg.h"
  45
  46 #define measure_time 0
  47 #define measure_time_pll 10000000
  48
  49 extern Action eUsbCxFinishAction;
  50 extern CommandType eUsbCxCommand;
  51 extern BOOLEAN UsbChirpFinish;
  52 extern USB_FIFO_CONFIG usbFifoConf;
  53 extern uint16_t *pu8DescriptorEX;
  54 extern uint16_t u16TxRxCounter;
  55
  56 void zfTurnOffPower_patch(void);
  57
  58 static void _fw_reset_dma_fifo();
  59 static void _fw_restore_dma_fifo();
  60 static void _fw_power_on();
  61 static void _fw_power_off();
  62
  63 BOOLEAN bEepromExist = TRUE;
  64 BOOLEAN bJumptoFlash = FALSE;
  65
  66 void _fw_usb_suspend_reboot()
  67 {
  68         /* reset usb/wlan dma */
  69         _fw_reset_dma_fifo();
  70
  71         /* restore gpio setting and usb/wlan dma state */
  72         _fw_restore_dma_fifo();
  73
  74         /* set clock to bypass mode - 40Mhz from XTAL */
  75         HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4));
  76
  77         A_DELAY_USECS(100); /* wait for stable */
  78
  79         HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));
  80
  81         A_DELAY_USECS(100); /* wait for stable */
  82         A_UART_HWINIT((40*1000*1000), 19200);
  83
  84         A_CLOCK_INIT(40);
  85
  86         if (!bEepromExist) { /* jump to flash boot (eeprom data in flash) */
  87                 bJumptoFlash = TRUE;
  88                 A_PRINTF("Jump to Flash BOOT\n");
  89                 app_start();
  90         } else {
  91                 A_PRINTF("receive the suspend command...\n");
  92                 /* reboot..... */
  93                 A_USB_JUMP_BOOT();
  94         }
  95
  96 }
  97
  98 #define PCI_RC_RESET_BIT                            BIT6
  99 #define PCI_RC_PHY_RESET_BIT                        BIT7
 100 #define PCI_RC_PLL_RESET_BIT                        BIT8
 101 #define PCI_RC_PHY_SHIFT_RESET_BIT                  BIT10
 102
 103 /*
 104  * -- urn_off_merlin --
 105  * . values suggested from Lalit
 106  *
 107  */
 108 static void turn_off_merlin()
 109 {
 110         volatile uint32_t default_data[9];
 111         uint32_t i=0;
 112
 113         if(1)
 114         {
 115                 A_PRINTF("turn_off_merlin_ep_start ......\n");
 116                 A_DELAY_USECS(measure_time);
 117                 default_data[0] = 0x9248fd00;
 118                 default_data[1] = 0x24924924;
 119                 default_data[2] = 0xa8000019;
 120                 default_data[3] = 0x17160820;
 121                 default_data[4] = 0x25980560;
 122                 default_data[5] = 0xc1c00000;
 123                 default_data[6] = 0x1aaabe40;
 124                 default_data[7] = 0xbe105554;
 125                 default_data[8] = 0x00043007;
 126
 127                 for(i=0; i<9; i++)
 128                 {
 129                         A_DELAY_USECS(10);
 130
 131                         HAL_WORD_REG_WRITE( 0x10ff4040, default_data[i]);
 132                 }
 133                 A_DELAY_USECS(10);
 134                 HAL_WORD_REG_WRITE(0x10ff4044, BIT0);
 135                 A_PRINTF("turn_off_merlin_ep_end ......\n");
 136         }
 137 }
 138
 139 /*
 140  * -- turn_off_phy --
 141  *
 142  * . write shift register to both pcie ep and rc
 143  * .
 144  */
 145
 146 static void turn_off_phy()
 147 {
 148
 149         volatile uint32_t default_data[9];
 150         volatile uint32_t read_data = 0;
 151         uint32_t i=0;
 152
 153         default_data[0] = 0x9248fd00;
 154         default_data[1] = 0x24924924;
 155         default_data[2] = 0xa8000019;
 156         default_data[3] = 0x17160820;
 157         default_data[4] = 0x25980560;
 158         default_data[5] = 0xc1c00000;
 159         default_data[6] = 0x1aaabe40;
 160         default_data[7] = 0xbe105554;
 161         default_data[8] = 0x00043007;
 162
 163         for(i=0; i<9; i++)
 164         {
 165                 // check for the done bit to be set
 166
 167                 while (1)
 168                 {
 169                         read_data=HAL_WORD_REG_READ(0x40028);
 170                         if( read_data & BIT31 )
 171                                 break;
 172                 }
 173
 174                 A_DELAY_USECS(1);
 175
 176                 HAL_WORD_REG_WRITE( 0x40024, default_data[i]);
 177         }
 178         HAL_WORD_REG_WRITE(0x40028, BIT0);
 179 }
 180
 181 static void turn_off_phy_rc()
 182 {
 183
 184         volatile uint32_t default_data[9];
 185         volatile uint32_t read_data = 0;
 186         uint32_t i=0;
 187
 188         A_PRINTF("turn_off_phy_rc\n");
 189
 190         default_data[0] = 0x9248fd00;
 191         default_data[1] = 0x24924924;
 192         default_data[2] = 0xa8000019;
 193         default_data[3] = 0x13160820;//PwdClk1MHz=0
 194         default_data[4] = 0x25980560;
 195         default_data[5] = 0xc1c00000;
 196         default_data[6] = 0x1aaabe40;
 197         default_data[7] = 0xbe105554;
 198         default_data[8] = 0x00043007;
 199
 200         for(i=0; i<9; i++)
 201         {
 202                 // check for the done bit to be set
 203
 204                 while (1)
 205                 {
 206                         read_data=HAL_WORD_REG_READ(0x40028);
 207                         if( read_data & BIT31 )
 208                                 break;
 209                 }
 210
 211                 A_DELAY_USECS(1);
 212
 213                 HAL_WORD_REG_WRITE( 0x40024, default_data[i]);
 214         }
 215         HAL_WORD_REG_WRITE(0x40028, BIT0);
 216 }
 217
 218 volatile uint32_t gpio_func = 0x0;
 219 volatile uint32_t gpio = 0x0;
 220
 221 /*
 222  * -- patch zfTurnOffPower --
 223  *
 224  * . set suspend counter to non-zero value
 225  * .
 226  */
 227 void zfTurnOffPower_patch(void)
 228 {
 229         A_PRINTF("+++ goto suspend ......\n");
 230
 231         // setting the go suspend here, power down right away...
 232         HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8));
 233
 234         A_DELAY_USECS(100);
 235
 236         // TURN OFF ETH PLL
 237         _fw_power_off();
 238
 239         //32clk wait for External ETH PLL stable
 240         A_DELAY_USECS(100);
 241
 242         HAL_WORD_REG_WRITE(0x52000, 0x70303);//read back 0x703f7
 243         HAL_WORD_REG_WRITE(0x52008, 0x0e91c);//read back 0x1e948
 244
 245         HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
 246                            (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(BIT0))); //0x56030
 247         // wake up, and turn on cpu, eth, pcie and usb pll
 248         _fw_power_on();
 249         // restore gpio and other settings
 250         _fw_restore_dma_fifo();
 251
 252         // clear suspend..................
 253         HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
 254                            (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)&(~BIT0)));
 255         HAL_WORD_REG_WRITE(0x52028, HAL_WORD_REG_READ(0x52028)&(~(BIT8|BIT12|BIT16)));
 256 }
 257
 258 /*
 259  * -- patch zfResetUSBFIFO_patch --
 260  *
 261  * . clear ep3/ep4 fifo
 262  * . set suspend magic pattern
 263  * . reset pcie ep phy
 264  * . reset pcie rc phy
 265  * . turn off pcie pll
 266  * . reset all pcie/gmac related registers
 267  * . reset usb dma
 268  */
 269 void zfResetUSBFIFO_patch(void)
 270 {
 271         A_PRINTF("0x9808  0x%x ......\n", HAL_WORD_REG_READ(0x10ff9808));
 272         A_PRINTF("0x7890  0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890));
 273         A_PRINTF("0x7890  0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890));
 274         A_PRINTF("0x4088  0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
 275         _fw_reset_dma_fifo();
 276 }
 277
 278 static void _fw_reset_dma_fifo()
 279 {
 280         HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
 281         HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10));
 282         A_PRINTF("_fw_reset_dma_fifo\n");
 283
 284         // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!!
 285         mUSB_STATUS_IN_INT_DISABLE();
 286
 287         // update magic pattern to indicate this is a suspend
 288         HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, SUS_MAGIC_PATTERN);
 289
 290         A_PRINTF("org 0x4048  0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048));
 291         A_PRINTF("org 0x404C  0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C));
 292         A_PRINTF("org 0x4088  0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
 293
 294         HAL_WORD_REG_WRITE(0x10ff4088,0xaaa6a);//1010.1010.1010.0110.1010 for UB94
 295         HAL_WORD_REG_WRITE(0x10ff404C,0x0);
 296
 297         A_DELAY_USECS(1000);
 298         A_PRINTF("0x4048  0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048));
 299         A_PRINTF("0x404C  0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C));
 300         A_PRINTF("0x4088  0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088));
 301
 302         // turn off merlin
 303         turn_off_merlin();
 304         // pcie ep
 305         A_PRINTF("turn_off_magpie_ep_start ......\n");
 306         A_DELAY_USECS(measure_time);
 307         HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)|BIT0|(1<<1)));
 308         turn_off_phy();
 309         HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&~(BIT0|(1<<1))));
 310         A_PRINTF("turn_off_magpie_ep_end ......\n");
 311
 312         // pcie rc
 313         A_PRINTF("turn_off_magpie_rc_start ......\n");
 314         A_DELAY_USECS(measure_time);
 315         HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&(~BIT0)));
 316         turn_off_phy_rc();
 317         A_PRINTF("turn_off_magpie_rc_end ......down\n");
 318         A_DELAY_USECS(measure_time);
 319
 320         A_PRINTF("0x4001C  %p ......\n", HAL_WORD_REG_READ(0x4001c));
 321         A_PRINTF("0x40040  %p ......\n", HAL_WORD_REG_READ(0x40040));
 322
 323         // turn off pcie_pll - power down (bit16)
 324         A_PRINTF(" before pwd PCIE PLL CFG:0x5601C  %p ......\n", HAL_WORD_REG_READ(0x5601C));
 325         HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)|(BIT18)));
 326         A_PRINTF(" after pwd PCIE PLL CFG:0x5601C  %p ......\n", HAL_WORD_REG_READ(0x5601C));
 327
 328         /* set everything to reset state?, requested by Oligo */
 329         HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)|(BIT13|BIT12|BIT11|BIT9|BIT7|BIT6));
 330
 331         HAL_WORD_REG_WRITE(0x5C000, 0);
 332
 333         A_DELAY_USECS(10);
 334
 335         // reset usb DMA controller
 336         HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x0);
 337
 338         HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT4)));
 339         A_DELAY_USECS(5);
 340         HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~BIT4)));
 341
 342
 343         HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x1);
 344 }
 345
 346 static void _fw_power_off()
 347 {
 348         /*
 349          *  1. set CPU bypass
 350          *  2. turn off CPU PLL
 351          *  3. turn off ETH PLL
 352          *  4. disable ETH PLL bypass and update
 353          *  4.1 set suspend timeout
 354          *  5. set SUSPEND_ENABLE
 355          */
 356
 357         HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4)); //0x56004
 358
 359         A_DELAY_USECS(100); // wait for stable
 360
 361         HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));//0x56000
 362
 363         A_DELAY_USECS(100); // wait for stable
 364
 365         A_UART_HWINIT((40*1000*1000), 19200);
 366         A_CLOCK_INIT(40);
 367
 368         HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR,
 369                            (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)|(BIT16)));   //0x5600c
 370
 371         HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,
 372                            (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)|(BIT4|BIT0))); //0x56010
 373
 374         HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
 375                            (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(0x10<<8))); //0x56030
 376 }
 377
 378 static void _fw_power_on()
 379 {
 380     /*
 381      *  1. turn on CPU PLL
 382      *  2. disable CPU bypass
 383      *  3. turn on ETH PLL
 384      *  4. disable ETH PLL bypass and update
 385      *  5. turn on pcie pll
 386      */
 387
 388         HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR,
 389                            (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)&(~BIT16)));
 390
 391         // deassert eth_pll bypass mode and trigger update bit
 392         HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,
 393                            (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)&(~(BIT4|BIT0))));
 394 }
 395
 396 #define CMD_PCI_RC_RESET_ON() HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \
 397                          (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)| \
 398                           (PCI_RC_PHY_SHIFT_RESET_BIT|PCI_RC_PLL_RESET_BIT|PCI_RC_PHY_RESET_BIT|PCI_RC_RESET_BIT)))
 399
 400 static void _fw_restore_dma_fifo(void)
 401 {
 402         HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)&(~(BIT18))));
 403
 404         // reset pcie_rc shift
 405         HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~(BIT10|BIT8|BIT7))));
 406         A_DELAY_USECS(1);
 407         HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT10|BIT8|BIT7)));
 408
 409         // reset pci_rc phy
 410         CMD_PCI_RC_RESET_ON();
 411         A_DELAY_USECS(20);
 412
 413         // enable dma swap function
 414         MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
 415         MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
 416         MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
 417         MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
 418 }