8 // @TODO: Should define the memory region later~
9 #define ALLOCRAM_START ( ((unsigned int)&_fw_image_end) + 4)
10 #define ALLOCRAM_SIZE ( SYS_RAM_SZIE - ( ALLOCRAM_START - SYS_D_RAM_REGION_0_BASE) - SYS_D_RAM_STACK_SIZE)
12 // support for more than 64 bytes on command pipe
13 extern void vUsb_Reg_Out_patch(void);
14 extern int _HIFusb_get_max_msg_len_patch(hif_handle_t handle, int pipe);
15 extern void _HIFusb_isr_handler_patch(hif_handle_t h);
16 extern BOOLEAN bSet_configuration_patch(void);
17 extern void vUSBFIFO_EP6Cfg_FS_patch(void);
18 extern void vUsb_Status_In_patch(void);
19 extern void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig);
20 extern void zfTurnOffPower_patch(void);
21 extern void zfResetUSBFIFO_patch(void);
22 extern void _HIFusb_start_patch(hif_handle_t handle);
23 extern void hif_pci_patch_install(struct hif_api *apis);
24 extern BOOLEAN bGet_descriptor_patch(void);
25 extern BOOLEAN bStandardCommand_patch(void);
28 extern void cmnos_clock_init_patch(a_uint32_t refclk);
29 extern a_uint32_t cmnos_refclk_speed_get_patch(void);
30 extern void cmnos_delay_us_patch(int us);
31 extern void cmnos_tick_patch(void);
32 extern a_uint32_t cmnos_milliseconds_patch(void);
34 extern BOOLEAN bJumptoFlash;
35 extern BOOLEAN bEepromExist;
40 #if defined(PROJECT_MAGPIE)
44 /* Zero BSS segment & dynamic memory section. */
47 #if defined(PROJECT_MAGPIE)
48 fatal_exception_func();
51 if( IS_FLASHBOOT() ) {
52 athos_indirection_table_install();
54 A_CLOCK_INIT(SYSTEM_CLK);
60 _indir_tbl.cmnos.timer._timer_init();
62 #if defined(PROJECT_K2)
64 * WAR: these variable is not initialized when boot from flash
65 * either re-enumeration or config them to default value = 0 would fix the issue
67 u8UsbInterfaceAlternateSetting = u8UsbConfigValue = u8UsbInterfaceValue = 0;
72 A_EEP_INIT(); /*Required for 1_1*/
75 #if defined(PROJECT_MAGPIE)
76 retEEP = A_EEP_IS_EXIST();
78 if ( RET_SUCCESS == retEEP ) {
85 hostif = A_IS_HOST_PRESENT();
87 #if defined(PROJECT_MAGPIE)
88 rst_status = *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR);
89 #elif defined(PROJECT_K2)
90 rst_status = HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR);
91 #endif /* #if defined(PROJECT_MAGPIE) */
94 A_PRINTF(" A_WDT_INIT()\n\r");
96 #if defined(PROJECT_K2)
97 save_cmnos_printf = (uint32_t) fw_cmnos_printf;
100 if( hostif == HIF_USB ) {
101 #if defined(PROJECT_K2)
102 #if MOVE_PRINT_TO_RAM
103 save_cmnos_printf = (uint32_t) _indir_tbl.cmnos.printf._printf;
104 _indir_tbl.cmnos.printf._printf = fw_cmnos_printf;
106 _indir_tbl.cmnos.usb._usb_fw_task = _fw_usb_fw_task;
107 _indir_tbl.cmnos.usb._usb_reset_fifo = _fw_usb_reset_fifo;
111 if( rst_status == WDT_MAGIC_PATTERN ) {
112 A_PRINTF(" ==>WDT reset<==\n");
113 #if defined(PROJECT_MAGPIE)
116 *((volatile uint32_t*)WATCH_DOG_RESET_COUNTER_ADDR)+=1;
117 } else if (rst_status == SUS_MAGIC_PATTERN) {
118 A_PRINTF(" ==>warm start<==\n");
120 A_PRINTF(" ==>cold start<==\n");
122 #if defined(PROJECT_MAGPIE)
123 *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR)=WDT_MAGIC_PATTERN;
124 #elif defined(PROJECT_K2)
125 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, WDT_MAGIC_PATTERN);
126 #endif /* #if defined(PROJECT_MAGPIE) */
128 /* intr enable would left for firmware */
129 /* athos_interrupt_init(); */
131 DBG_MODULE_INSTALL();
132 #if defined(PROJECT_K2)
136 #if defined(PROJECT_K2)
137 #if SYSTEM_MODULE_SFLASH
138 SFLASH_MODULE_INSTALL();
143 HIF_MODULE_INSTALL();
144 HTC_MODULE_INSTALL();
145 WMI_SERVICE_MODULE_INSTALL();
146 BUF_POOL_MODULE_INSTALL();
147 VBUF_MODULE_INSTALL();
148 VDESC_MODULE_INSTALL();
150 //init each module, should be put together..
151 A_PRINTF("ALLOCRAM start 0x%x size %d\n", ALLOCRAM_START, ALLOCRAM_SIZE);
152 A_ALLOCRAM_INIT(ALLOCRAM_START, ALLOCRAM_SIZE);
154 if( hostif == HIF_USB ) {
155 _indir_tbl.hif._get_max_msg_len = _HIFusb_get_max_msg_len_patch;
156 _indir_tbl.cmnos.usb._usb_reg_out = vUsb_Reg_Out_patch;
157 _indir_tbl.hif._isr_handler = _HIFusb_isr_handler_patch;
158 _indir_tbl.cmnos.usb._usb_set_configuration = bSet_configuration_patch;
159 _indir_tbl.cmnos.usb._usb_status_in = vUsb_Status_In_patch;
160 _indir_tbl.cmnos.usb._usb_get_descriptor = bGet_descriptor_patch;
161 _indir_tbl.cmnos.usb._usb_standard_cmd = bStandardCommand_patch;
162 _indir_tbl.usbfifo_api._init = _fw_usbfifo_init;
164 #if defined(PROJECT_MAGPIE)
165 _indir_tbl.cmnos.usb._usb_power_off = zfTurnOffPower_patch;
166 _indir_tbl.cmnos.usb._usb_reset_fifo = zfResetUSBFIFO_patch;
167 _indir_tbl.hif._start = _HIFusb_start_patch;
168 _indir_tbl.htc._HTC_MsgRecvHandler = HTCMsgRecvHandler_patch;
169 _indir_tbl.htc._HTC_ControlSvcProcessMsg = HTCControlSvcProcessMsg_patch;
172 if (!(USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT6)) {
173 vUSBFIFO_EP6Cfg_FS_patch();
176 #ifdef FUSION_USB_ENABLE_TX_STREAM
177 // For K2, enable tx stream mode
178 A_PRINTF("Enable Tx Stream mode\r\n");
180 // Patch for K2 USB STREAM mode
181 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
182 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))); // disable down stream DMA mode
184 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
185 ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6)));
187 #if SYSTEM_MODULE_HP_EP5
188 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
189 ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)));
192 #if SYSTEM_MODULE_HP_EP6
193 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
194 ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)));
196 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
197 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT0))); // enable down stream DMA mode
200 #ifdef FUSION_USB_ENABLE_RX_STREAM
201 // Patch for K2 USB STREAM mode
202 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
203 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))); // disable upstream DMA mode
204 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
205 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))); // enable upstream stream mode
207 // K2, Set maximum IN transfer to 8K
208 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
209 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(0xcf)));
210 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
211 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(0x20)));
213 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
214 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT1))); // enable upstream DMA mode
216 USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, 0xa0); // set stream mode timeout critirea
217 #if defined(PROJECT_K2)
218 /*0x10004020 is vaild in k2 but could be invaild in other chip*/
219 if ((HAL_WORD_REG_READ(0x10004020) & 0x2000) != 0) {
220 /* disable stream mode for AR9270 */
221 USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 0);
223 /* enable stream mode for AR9271 */
224 USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 9);
227 USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 9);
231 #if defined(PROJECT_MAGPIE) && !defined(ROM_VER_1_1)
232 else if (hostif == HIF_PCI )
233 hif_pci_patch_install(&_indir_tbl.hif);
236 // patch the clock function
238 _indir_tbl.cmnos.clock._clock_init = cmnos_clock_init_patch;
239 _indir_tbl.cmnos.clock._refclk_speed_get = cmnos_refclk_speed_get_patch;
240 _indir_tbl.cmnos.clock._delay_us = cmnos_delay_us_patch;
241 _indir_tbl.cmnos.clock._clock_tick = cmnos_tick_patch;
242 _indir_tbl.cmnos.clock._milliseconds = cmnos_milliseconds_patch;
244 //default clock, setup initial variable, SYSTEM_FREQ=40
245 A_CLOCK_INIT(SYSTEM_FREQ);
250 #if MAGPIE_ENABLE_WLAN == 1
252 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR,
253 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT10|BIT8|BIT7|BIT6))));
254 #if defined(PROJECT_MAGPIE)
255 HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR,
256 (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT1));
259 wlan_pci_module_init();
264 A_PRINTF("Tgt running\n\r");
266 #if defined(PROJECT_MAGPIE)
268 A_PRINTF("======= Apply MISC Assert patch\n\r");
269 _assfail_ori = _indir_tbl.cmnos.misc._assfail;
270 _indir_tbl.cmnos.misc._assfail = exception_reset;
275 wlan_task(); //never return