target_firmware/magpie_fw_dev/target/inc/k2/k2/reg_defs.h

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted (subject to the limitations in the
   7  * disclaimer below) provided that the following conditions are met:
   8  *
   9  *  * Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  *  * Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the
  15  *    distribution.
  16  *
  17  *  * Neither the name of Qualcomm Atheros nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35 /*************************************************************************/
  36 /*  Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */
  37 /*                                                                       */
  38 /*  Module Name : reg_defs.h                                             */
  39 /*                                                                       */
  40 /*  Abstract                                                             */
  41 /*      This file contains the register addr and marco definition.       */
  42 /*                                                                       */
  43 /*  NOTES                                                                */
  44 /*      None                                                             */
  45 /*                                                                       */
  46 /*************************************************************************/
  47 #ifndef _REG_DEFS_H_
  48 #define _REG_DEFS_H_
  49
  50 #include "dt_defs.h"
  51
  52 #define BIT_SET(bit)    (1<<bit)
  53 #define BIT_CLR(bit)    (0<<bit)
  54
  55 #define HAL_WORD_REG_WRITE(addr, val)                                   \
  56         do {                                                            \
  57                 (*((volatile uint32_t *)(addr&0xfffffffc))) = (uint32_t)(val); \
  58         } while (0)
  59
  60 #define HAL_WORD_REG_READ(addr) (*((volatile uint32_t *)(addr&0xfffffffc)))
  61
  62
  63 #define HAL_HALF_WORD_REG_WRITE(addr, val)                              \
  64         do {                                                            \
  65                 (*((volatile uint16_t *)(addr&0xfffffffe))) = (uint16_t)(val); \
  66         } while (0)
  67
  68 #define HAL_HALF_WORD_REG_READ(addr) (*((volatile uint16_t *)(addr&0xfffffffe)))
  69
  70
  71 #define HAL_BYTE_REG_WRITE(addr, val)                                   \
  72         do {                                                            \
  73                 (*((volatile uint8_t *)(addr))) = (uint8_t)(val);       \
  74         } while (0)
  75
  76 #define HAL_BYTE_REG_READ(addr) (*((volatile uint8_t *)(addr)))
  77
  78 /***** REGISTER BASE ADDRESS DEFINITION *****/
  79 #define RESET_VECTOR_ADDRESS        0x8e0000
  80 /********************************************/
  81
  82 /***** REGISTER BASE ADDRESS DEFINITION *****/
  83 #define USB_CTRL_BASE_ADDRESS           0x00010000
  84 #define RST_BASE_ADDRESS                0x00050000
  85 #define UART_BASE_ADDRESS               0x00051000
  86 #define HOST_DMA_BASE_ADDRESS           0x00053000
  87 #define USB_DMA_BASE_ADDRESS            0x00055000
  88 #define SPI_REG_BASE_ADDRESS            0x0005B000
  89 #define WLAN_BASE_ADDRESS           0x10000000
  90 #define MAC_REG_BASE_ADDRESS        WLAN_BASE_ADDRESS
  91 /*******************************************************************************/
  92 /* Reset Register*/
  93 #define MAGPEI_REG_RST_BASE_ADDR                    RST_BASE_ADDRESS
  94
  95 #define REG_GENERAL_TIMER_OFFSET                    0x0
  96 #define REG_GENERAL_TIMER_RELOAD_OFFSET             0x4
  97 #define REG_WATCHDOG_TIMER_CONTROL_OFFSET           0x8
  98 #define REG_WATCHDOG_TIMER_OFFSET                   0xC
  99 #define REG_RESET_OFFSET                            0x10
 100 #define REG_BOOTSTRAP                               0x14
 101 #define REG_AHB_ARB                                 0x18
 102 #define REG_WATCHDOG_INTR_OFFSET                    0x1C
 103 #define REG_GENERAL_TIMER_INTR_OFFSET               0x20
 104 #define REG_REVISION_ID                             0x90
 105 #define REG_CLOCK_CONTROL_OFFSET                    0x40
 106 #define REG_RST_PWDN_CONTROL_OFFSET                 0x44
 107 #define REG_USB_PLL_OFFSET                          0x48
 108 #define REG_RST_STATUS_OFFSET                       0x4C
 109
 110
 111 #define MAGPEI_REG_RST_GENERAL_TIMER_ADDR       (RST_BASE_ADDRESS+REG_GENERAL_TIMER_OFFSET)
 112 #define MAGPIE_REG_RST_GENERAL_TIMER_RLD_ADDR   (RST_BASE_ADDRESS+REG_GENERAL_TIMER_RELOAD_OFFSET)
 113 #define MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR      (RST_BASE_ADDRESS+REG_WATCHDOG_TIMER_CONTROL_OFFSET)
 114 #define MAGPIE_REG_RST_WDT_TIMER_ADDR           (RST_BASE_ADDRESS+REG_WATCHDOG_TIMER_OFFSET)
 115 #define MAGPIE_REG_RST_RESET_ADDR               (RST_BASE_ADDRESS+REG_RESET_OFFSET)
 116 #define MAGPIE_REG_RST_BOOTSTRAP_ADDR           (RST_BASE_ADDRESS+REG_BOOTSTRAP)
 117 #define MAGPIE_REG_AHB_ARB_ADDR                 (RST_BASE_ADDRESS+REG_AHB_ARB)
 118 #define MAGPIE_REG_RST_WDT_INTR_ADDR            (RST_BASE_ADDRESS+REG_WATCHDOG_INTR_OFFSET)
 119 #define MAGPIE_REG_RST_GENERAL_TIMER_INTR_ADDR  (RST_BASE_ADDRESS+REG_GENERAL_TIMER_INTR_OFFSET)
 120 #define MAGPIE_REG_REVISION_ID_ADDR             (RST_BASE_ADDRESS+REG_REVISION_ID)
 121 #define MAGPIE_REG_CLOCK_CTRL_ADDR              (RST_BASE_ADDRESS+REG_CLOCK_CONTROL_OFFSET)
 122 #define MAGPIE_REG_RST_PWDN_CTRL_ADDR           (RST_BASE_ADDRESS+REG_RST_PWDN_CONTROL_OFFSET)
 123 #define MAGPIE_REG_USB_PLL_ADDR                 (RST_BASE_ADDRESS+REG_USB_PLL_OFFSET)
 124 #define MAGPIE_REG_RST_STATUS_ADDR              (RST_BASE_ADDRESS+REG_RST_STATUS_OFFSET)
 125
 126 #define MAGPEI_REG_RST_GENERAL_TIMER            (*((volatile u32_t*)(MAGPEI_REG_RST_GENERAL_TIMER_ADDR)))
 127 #define MAGPIE_REG_RST_GENERAL_TIMER_RLD        (*((volatile u32_t*)(MAGPIE_REG_RST_GENERAL_TIMER_RLD_ADDR)))
 128 #define MAGPIE_REG_RST_WDT_TIMER_CTRL           (*((volatile u32_t*)(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR)))
 129 #define MAGPIE_REG_RST_WDT_TIMER                (*((volatile u32_t*)(MAGPIE_REG_RST_WDT_TIMER_ADDR)))
 130 #define MAGPIE_REG_RST_RESET                    (*((volatile u32_t*)(MAGPIE_REG_RST_RESET_ADDR)))
 131 #define MAGPIE_REG_RST_BOOTSTRAP                (*((volatile u32_t*)(MAGPIE_REG_RST_BOOTSTRAP_ADDR)))
 132 #define MAGPIE_REG_AHB_ARB                      (*((volatile u32_t*)(MAGPIE_REG_AHB_ARB_ADDR)))
 133 #define MAGPIE_REG_REVISION_ID                  (*((volatile u32_t*)(MAGPIE_REG_REVISION_ID_ADDR)))
 134 #define MAGPIE_REG_CLOCK_CTRL                   (*((volatile u32_t*)(MAGPIE_REG_CLOCK_CTRL_ADDR)))
 135 #define MAGPIE_REG_RST_PWDN_CTRL                (*((volatile u32_t*)(MAGPIE_REG_RST_PWDN_CTRL_ADDR)))
 136 #define MAGPIE_REG_USB_PLL                      (*((volatile u32_t*)(MAGPIE_REG_USB_PLL_ADDR)))
 137 #define MAGPIE_REG_RST_STATUS                   (*((volatile u32_t*)(MAGPIE_REG_RST_STATUS_ADDR)))
 138
 139
 140 /*******************************************************************************/
 141 /* USB DMA Register*/
 142
 143 #define MAGPIE_REG_USB_INTERRUPT_ADDR           USB_DMA_BASE_ADDRESS
 144 #define MAGPIE_REG_USB_INTERRUPT_MASK_ADDR      (USB_DMA_BASE_ADDRESS + 0x4)
 145
 146 #define MAGPIE_REG_USB_RX0_DESC_START_ADDR      (USB_DMA_BASE_ADDRESS + 0x800)
 147 #define MAGPIE_REG_USB_RX0_DMA_START_ADDR       (USB_DMA_BASE_ADDRESS + 0x804)
 148 #define MAGPIE_REG_USB_RX0_BURST_SIZE_ADDR      (USB_DMA_BASE_ADDRESS + 0x808)
 149 #define MAGPIE_REG_USB_RX0_STATE_ADDR           (USB_DMA_BASE_ADDRESS + 0x814)
 150 #define MAGPIE_REG_USB_RX0_CUR_TRACE_ADDR       (USB_DMA_BASE_ADDRESS + 0x818)
 151 #define MAGPIE_REG_USB_RX0_SWAP_DATA_ADDR       (USB_DMA_BASE_ADDRESS + 0x81C)
 152
 153 #define MAGPIE_REG_USB_RX1_DESC_START_ADDR      (USB_DMA_BASE_ADDRESS + 0x900)
 154 #define MAGPIE_REG_USB_RX1_DMA_START_ADDR       (USB_DMA_BASE_ADDRESS + 0x904)
 155 #define MAGPIE_REG_USB_RX1_BURST_SIZE_ADDR      (USB_DMA_BASE_ADDRESS + 0x908)
 156 #define MAGPIE_REG_USB_RX1_STATE_ADDR           (USB_DMA_BASE_ADDRESS + 0x914)
 157 #define MAGPIE_REG_USB_RX1_CUR_TRACE_ADDR       (USB_DMA_BASE_ADDRESS + 0x918)
 158 #define MAGPIE_REG_USB_RX1_SWAP_DATA_ADDR       (USB_DMA_BASE_ADDRESS + 0x91C)
 159
 160 #define MAGPIE_REG_USB_RX2_DESC_START_ADDR      (USB_DMA_BASE_ADDRESS + 0xa00)
 161 #define MAGPIE_REG_USB_RX2_DMA_START_ADDR       (USB_DMA_BASE_ADDRESS + 0xa04)
 162 #define MAGPIE_REG_USB_RX2_BURST_SIZE_ADDR      (USB_DMA_BASE_ADDRESS + 0xa08)
 163 #define MAGPIE_REG_USB_RX2_STATE_ADDR           (USB_DMA_BASE_ADDRESS + 0xa14)
 164 #define MAGPIE_REG_USB_RX2_CUR_TRACE_ADDR       (USB_DMA_BASE_ADDRESS + 0xa18)
 165 #define MAGPIE_REG_USB_RX2_SWAP_DATA_ADDR       (USB_DMA_BASE_ADDRESS + 0xa1C)
 166
 167 #define MAGPIE_REG_USB_TX0_DESC_START_ADDR      (USB_DMA_BASE_ADDRESS + 0xC00)
 168 #define MAGPIE_REG_USB_TX0_DMA_START_ADDR       (USB_DMA_BASE_ADDRESS + 0xC04)
 169 #define MAGPIE_REG_USB_TX0_BURST_SIZE_ADDR      (USB_DMA_BASE_ADDRESS + 0xC08)
 170 #define MAGPIE_REG_USB_TX0_STATE_ADDR           (USB_DMA_BASE_ADDRESS + 0xC10)
 171 #define MAGPIE_REG_USB_TX0_CUR_TRACE_ADDR       (USB_DMA_BASE_ADDRESS + 0xC14)
 172 #define MAGPIE_REG_USB_TX0_SWAP_DATA_ADDR       (USB_DMA_BASE_ADDRESS + 0xC18)
 173
 174 #define MAGPIE_REG_USB_INTERRUPT_TX0_END         (1<<24) //0x1000000
 175 #define MAGPIE_REG_USB_INTERRUPT_TX0_COMPL       (1<<16) //0x10000
 176 #define MAGPIE_REG_USB_INTERRUPT_RX2_END         (1<<10) //0x00400
 177 #define MAGPIE_REG_USB_INTERRUPT_RX1_END         (1<<9) //0x00200
 178 #define MAGPIE_REG_USB_INTERRUPT_RX0_END         (1<<8)  //0x0100
 179 #define MAGPIE_REG_USB_INTERRUPT_RX2_COMPL       (1<<2) //0x00004
 180
 181 #define MAGPIE_REG_USB_INTERRUPT_RX1_COMPL       (1<<1) //0x00002
 182 #define MAGPIE_REG_USB_INTERRUPT_RX0_COMPL       (1<<0)  //0x00001
 183
 184
 185 #define MAGPIE_REG_USB_INTERRUPT                (*((volatile u32_t*)(MAGPIE_REG_USB_INTERRUPT_ADDR)))
 186 #define MAGPIE_REG_USB_INTERRUPT_MASK           (*((volatile u32_t*)(MAGPIE_REG_USB_INTERRUPT_MASK_ADDR)))
 187
 188 #define MAGPIE_REG_USB_RX0_DESC_START           (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_DESC_START_ADDR)))
 189 #define MAGPIE_REG_USB_RX0_DMA_START            (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_DMA_START_ADDR)))
 190 #define MAGPIE_REG_USB_RX0_BURST_SIZE           (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_BURST_SIZE_ADDR)))
 191 #define MAGPIE_REG_USB_RX0_STATE                    (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_STATE_ADDR)))
 192 #define MAGPIE_REG_USB_RX0_CUR_TRACE            (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_CUR_TRACE_ADDR)))
 193 #define MAGPIE_REG_USB_RX0_SWAP_DATA            (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_SWAP_DATA_ADDR)))
 194
 195
 196 #define MAGPIE_REG_USB_RX1_DESC_START           (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_DESC_START_ADDR)))
 197 #define MAGPIE_REG_USB_RX1_DMA_START            (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_DMA_START_ADDR)))
 198 #define MAGPIE_REG_USB_RX1_BURST_SIZE           (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_BURST_SIZE_ADDR)))
 199 #define MAGPIE_REG_USB_RX1_STATE                    (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_STATE_ADDR)))
 200 #define MAGPIE_REG_USB_RX1_CUR_TRACE            (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_CUR_TRACE_ADDR)))
 201 #define MAGPIE_REG_USB_RX1_SWAP_DATA            (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_SWAP_DATA_ADDR)))
 202
 203 #define MAGPIE_REG_USB_RX2_DESC_START           (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_DESC_START_ADDR)))
 204 #define MAGPIE_REG_USB_RX2_DMA_START            (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_DMA_START_ADDR)))
 205 #define MAGPIE_REG_USB_RX2_BURST_SIZE           (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_BURST_SIZE_ADDR)))
 206 #define MAGPIE_REG_USB_RX2_STATE                    (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_STATE_ADDR)))
 207 #define MAGPIE_REG_USB_RX2_CUR_TRACE            (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_CUR_TRACE_ADDR)))
 208 #define MAGPIE_REG_USB_RX2_SWAP_DATA            (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_SWAP_DATA_ADDR)))
 209
 210
 211 #define MAGPIE_REG_USB_TX0_DESC_START           (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_DESC_START_ADDR)))
 212 #define MAGPIE_REG_USB_TX0_DMA_START            (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_DMA_START_ADDR)))
 213 #define MAGPIE_REG_USB_TX0_BURST_SIZE           (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_BURST_SIZE_ADDR)))
 214 #define MAGPIE_REG_USB_TX0_STATE                    (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_STATE_ADDR)))
 215 #define MAGPIE_REG_USB_TX0_CUR_TRACE            (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_CUR_TRACE_ADDR)))
 216 #define MAGPIE_REG_USB_TX0_SWAP_DATA            (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_SWAP_DATA_ADDR)))
 217
 218 /*******************************************************************************/
 219 /***************************/
 220 #define MAGPIE_REG_SPI_BASE_ADDR        SPI_REG_BASE_ADDRESS
 221
 222 #define REG_SPI_CS_OFFSET               0x0
 223 #define REG_SPI_AO_OFFSET                           0x4
 224 #define REG_SPI_D_OFFSET                            0x8
 225 #define REG_SPI_CLKDIV_OFFSET                       0x1C
 226
 227
 228 #define MAGPIE_REG_SPI_CS_ADDR                      (SPI_REG_BASE_ADDRESS + REG_SPI_CS_OFFSET)
 229 #define MAGPIE_REG_SPI_AO_ADDR                      (SPI_REG_BASE_ADDRESS + REG_SPI_AO_OFFSET)
 230 #define MAGPIE_REG_SPI_D_ADDR                       (SPI_REG_BASE_ADDRESS + REG_SPI_D_OFFSET)
 231 #define MAGPIE_REG_SPI_CLKDIV_ADDR                  (SPI_REG_BASE_ADDRESS + REG_SPI_CLKDIV_OFFSET)
 232
 233 /*******************************************************************************/
 234 #define K2_REG_MAC_BASE_ADDR                        MAC_REG_BASE_ADDRESS
 235
 236 #define REG_PLL_CONTROL_OFFSET                      0x7014
 237 #define REG_RTC_FORCE_OFFSET                        0x7040
 238 #define REG_RTC_STATUS_OFFSET                       0x7044
 239
 240 #define K2_REG_PLL_CONTROL_ADDR                     (MAC_REG_BASE_ADDRESS + REG_PLL_CONTROL_OFFSET)
 241 #define K2_REG_RTC_FORCE_ADDR                       (MAC_REG_BASE_ADDRESS + REG_RTC_FORCE_OFFSET)
 242 #define K2_REG_RTC_STATUS_ADDR                      (MAC_REG_BASE_ADDRESS + REG_RTC_STATUS_OFFSET)
 243 #endif