1 #ifndef __AR6K_MISC_H__
2 #define __AR6K_MISC_H__
5 * AR6001: CIS Tuple 0x82, "Board Hardware Configuration Information",
6 * is set at chip reset according to board configuration. Bits in this
7 * register indicate what type of Host connection is in use. We don't
8 * have proper header files to describe tuples, so the offset and layout
9 * for the one tuple that firmwware needs is defined here.
11 * AR6002: The RESET_TUPLE_STATUS register in the GPIO block holds
12 * Board Hardware Configuration Information.
14 * If the interface is SDIO, then the "INFO_MASK" must be "SDIO_NORMAL".
15 * For debug purposes, a Target with the KeepAlive jumper may be booted
16 * before the Host. In this case, INFO_MASK is 0.
18 * For NON-SDIO Host interfaces, the INFO_MASK may hold board information.
20 * By convention, hostless boards set INTERFACE to SDIO, and INFO to
21 * something OTHER than SDIO_NORMAL or 0.
23 * Layout of Board HW Cfg Info is below. These values are captured at
24 * reset and made available to software.
26 * These 3 bits are available on AR6002 via RESET_TUPLE_STATUS_ADDRESS;
27 * they are NOT available on AR6001.
29 * bit 9: cmode[1] Bits 9..8 indicate modes as follows:
30 * bit 8: cmode[0] 0-->normal
32 * 2-->functional test (ATE)
35 * These 8 bits are available on AR6002 through RESET_TUPLE_STATUS_ADDRESS
36 * and on both AR6001 and AR6002 through CIS Tuple 0x82.
37 * bit 7: gpio9 (aka hmode0) Bits 7..6 are the "Interface Config bits"
38 * bit 6: tdo (aka hmode1)
47 #if defined(RESET_TUPLE_STATUS_ADDRESS)
48 #define AR6K_BOARD_HWCFG_CMODE_MASK 0x300
49 #define AR6K_BOARD_HWCFG_CMODE_ATE 0x200
52 * CIS Tuple 0x82 happens to be located at offset 0x13c into CIS registers.
53 * This may change across tapeouts, if CIS tuple information changes.
55 #define AR6K_BOARD_HWCFG_TUPLE_OFFSET 0x13c
58 #define AR6K_BOARD_HWCFG_INTERFACE_MASK 0xc0
59 #define AR6K_BOARD_HWCFG_KEEP_ALIVE_MASK 0x20
60 #define AR6K_BOARD_HWCFG_INFO_MASK 0x1f
62 /* Values for INTERFACE_MASK indicate type of interface */
63 #define AR6K_BOARD_HWCFG_SPI 0x00
64 #define AR6K_BOARD_HWCFG_SDIO 0x40
65 #define AR6K_BOARD_HWCFG_LBCF 0x80
66 #define AR6K_BOARD_HWCFG_MSIO 0xc0
68 #define AR6K_BOARD_HWCFG_SDIO_NORMAL 0x1f
70 #endif /* __AR6K_MISC_H__ */