2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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6 * modification, are permitted (subject to the limitations in the
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19 * from this software without specific prior written permission.
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22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #include "athos_api.h"
42 #include "usbfifo_api.h"
47 typedef void (* USBFIFO_recv_command)(VBUF *cmd);
48 void _fw_usb_suspend_reboot();
50 extern Action eUsbCxFinishAction;
51 extern CommandType eUsbCxCommand;
52 extern BOOLEAN UsbChirpFinish;
53 extern USB_FIFO_CONFIG usbFifoConf;
55 USBFIFO_recv_command m_origUsbfifoRecvCmd = NULL;
58 #define vUsb_ep0end(void) \
60 eUsbCxCommand = CMD_VOID; \
61 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); \
64 #define vUsb_ep0fail(void) USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04)
68 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
69 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT1)); \
70 UsbChirpFinish = FALSE; \
73 #define vUsb_suspend() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
74 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT2))
76 #define vUsb_resm() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
77 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT3))
79 void _fw_usbfifo_recv_command(VBUF *buf)
84 cmd_data = (A_UINT8 *)(buf->desc_list->buf_addr + buf->desc_list->data_offset);
85 tmp = *((A_UINT32 *)cmd_data);
86 if ( tmp == 0xFFFFFFFF ) {
87 _fw_usb_suspend_reboot();
89 m_origUsbfifoRecvCmd(buf);
93 void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig)
95 m_origUsbfifoRecvCmd = pConfig->recv_command;
97 usbFifoConf.get_command_buf = pConfig->get_command_buf;
98 usbFifoConf.recv_command = _fw_usbfifo_recv_command;
99 usbFifoConf.get_event_buf = pConfig->get_event_buf;
100 usbFifoConf.send_event_done = pConfig->send_event_done;
103 #define CHECK_SOF_LOOP_CNT 50
105 void _fw_usb_suspend_reboot()
107 volatile uint32_t gpio_in = 0;
108 volatile uint32_t pupd = 0;
109 volatile uint32_t t = 0;
110 volatile uint32_t sof_no=0,sof_no_new=0;
111 /* Set GO_TO_SUSPEND bit to USB main control register */
113 A_PRINTF("!USB suspend\n\r");
115 // keep the record of suspend
116 #if defined(PROJECT_MAGPIE)
117 *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = SUS_MAGIC_PATTERN;
118 #elif defined(PROJECT_K2)
119 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
120 #endif /* #if defined(PROJECT_MAGPIE) */
128 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1000;
130 // reset ep3/ep4 fifo in case there is data which might affect resuming
131 // HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
132 // HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10));
135 // config gpio to input before goto suspend
138 //jtag = HAL_WORD_REG_READ(0x10004054);
139 //HAL_WORD_REG_WRITE(0x10004054, (jtag|BIT17));
142 //spi = HAL_WORD_REG_READ(0x50040);
143 //HAL_WORD_REG_WRITE(0x50040, (spi&~(BIT8)));
145 //set all GPIO to input
146 gpio_in = HAL_WORD_REG_READ(0x1000404c);
147 HAL_WORD_REG_WRITE(0x1000404c, 0x0);
149 //set PU/PD for all GPIO except two UART pins
150 pupd = HAL_WORD_REG_READ(0x10004088);
151 HAL_WORD_REG_WRITE(0x10004088, 0xA982AA6A);
154 sof_no= HAL_WORD_REG_READ(0x10004);
155 for (t = 0; t < CHECK_SOF_LOOP_CNT; t++)
157 A_DELAY_USECS(1000); //delay 1ms
158 sof_no_new = HAL_WORD_REG_READ(0x10004);
160 if(sof_no_new == sof_no)
167 * Reset "printf" module patch point(RAM to ROM) when K2 warm start or suspend,
168 * which fixed the error issue cause by redownload another different firmware.
170 _indir_tbl.cmnos.printf._printf = save_cmnos_printf;
172 ///////////////////////////////////////////////////////////////
173 // setting the go suspend here, power down right away...
174 if (t != CHECK_SOF_LOOP_CNT) // not time out
175 HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8));
176 ///////////////////////////////////////////////////////////////
178 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1100;
180 #if 0 // pll unstable, h/w bug?
181 HAL_WORD_REG_WRITE(0x50040, (0x300|6|(1>>1)<<12));
182 A_UART_HWINIT((40*1000*1000)/1, 19200);
185 // restore gpio setting
186 //HAL_WORD_REG_WRITE(0x10004054, jtag);
187 //HAL_WORD_REG_WRITE(0x50040, spi);
188 HAL_WORD_REG_WRITE(0x1000404c, gpio_in);
189 HAL_WORD_REG_WRITE(0x10004088, pupd);
191 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1200;
194 // since we still need to touch mac_base address after resuming back, so that
195 // reset mac can't be done in ResetFifo function, move to here...
196 // whole mac control reset.... (bit1)
197 HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT1) );
198 HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0));
199 HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 );
203 //A_PRINTF("reg(0x10020)=(%x)\n", HAL_WORD_REG_READ(0x10020));
204 // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!!
205 mUSB_STATUS_IN_INT_DISABLE();
207 MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
208 MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
209 MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
210 MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
212 if (((DEBUG_SYSTEM_STATE&~(0x0000ffff))>>16 == 0x5342)) {
213 /* UART_SEL and SPI_SEL */
214 HAL_WORD_REG_WRITE(0x50040, (0x300|0|(1>>1)<<12));
217 /* Jump to boot code */
223 * -- patch usb_fw_task --
224 * . usb zero length interrupt should not clear by s/w, h/w will handle that
225 * . complete suspend handle, configure gpio, turn off related function,
226 * slow down the pll for stable issue
228 void _fw_usb_fw_task(void)
230 register uint8_t usb_interrupt_level1;
231 register uint8_t usb_interrupt_level2;
233 usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET);
234 #if 0 // these endpoints are handled by DMA
235 if (usb_interrupt_level1 & BIT5) //Group Byte 5
240 if (usb_interrupt_level1 & BIT4)
242 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_4_OFFSET);
243 if( usb_interrupt_level2 & BIT6)
244 A_USB_REG_OUT();//vUsb_Reg_Out();
247 if (usb_interrupt_level1 & BIT6)
249 //zfGenWatchDogEvent();
250 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_6_OFFSET);
251 if( usb_interrupt_level2 & BIT6)
252 A_USB_STATUS_IN();//vUsb_Status_In();
255 if (usb_interrupt_level1 & BIT0) //Group Byte 0
257 //usb_interrupt_level2 = ZM_INTR_SOURCE_0_REG;
258 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET);
260 // refer to FUSB200, p 48, offset:21H, bit7 description, should clear the command abort interrupt first!?
261 if (usb_interrupt_level2 & BIT7)
263 //ZM_INTR_SOURCE_0_REG &= 0x7f; // Handle command abort
264 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)& ~BIT7));
265 A_PRINTF("![SOURCE_0] bit7 on\n\r");
268 if (usb_interrupt_level2 & BIT1)
270 //A_PRINTF("![USB] ep0 IN in \n\r");
271 A_USB_EP0_TX(); // USB EP0 tx interrupt
273 if (usb_interrupt_level2 & BIT2)
275 //A_PRINTF("![USB] ep0 OUT in\n\r");
276 A_USB_EP0_RX(); // USB EP0 rx interrupt
278 if (usb_interrupt_level2 & BIT0)
280 //A_PRINTF("![USB] ep0 SETUP in\n\r");
282 //vWriteUSBFakeData();
284 // else if (usb_interrupt_level2 & BIT3)
285 if (usb_interrupt_level2 & BIT3)
288 // A_PRINTF("![SOURCE_0] ep0 CMD_END\n\r");
290 if (usb_interrupt_level2 & BIT4)
293 // A_PRINTF("![SOURCE_0] ep0 CMD_FAIL\n\r");
295 if (eUsbCxFinishAction == ACT_STALL)
297 // set CX_STL to stall Endpoint0 & will also clear FIFO0
298 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
299 // A_PRINTF("![USB] ZM_CX_CONFIG_STATUS_REG = 0x04\n\r");
301 else if (eUsbCxFinishAction == ACT_DONE)
303 // set CX_DONE to indicate the transmistion of control frame
304 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
306 eUsbCxFinishAction = ACT_IDLE;
309 if (usb_interrupt_level1 & BIT7) //Group Byte 7
311 //usb_interrupt_level2 = ZM_INTR_SOURCE_7_REG;
312 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET);
315 if (usb_interrupt_level2 & BIT7)
317 vUsb_Data_Out0Byte();
318 // A_PRINTF("![SOURCE_7] bit7 on, clear it\n\r");
320 if (usb_interrupt_level2 & BIT6)
323 // A_PRINTF("![SOURCE_7] bit6 on, clear it\n\r");
327 if (usb_interrupt_level2 & BIT1)
330 //USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~0x2));
331 A_PRINTF("!USB reset\n\r");
332 // A_PRINTF("![0x1012c]: %\n\r", USB_WORD_REG_READ(0x12c));
334 if (usb_interrupt_level2 & BIT2)
336 // TBD: the suspend resume code should put here, Ryan, 07/18
338 // issue, jump back to rom code and what peripherals should we reset here?
340 _fw_usb_suspend_reboot();
342 if (usb_interrupt_level2 & BIT3)
345 A_PRINTF("!USB resume\n\r");
352 void _fw_usb_reset_fifo(void)
354 volatile uint32_t *reg_data;
356 HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10));
357 HAL_BYTE_REG_WRITE(0x100af, (HAL_BYTE_REG_READ(0x100af)|0x10));
359 // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!!
360 mUSB_STATUS_IN_INT_DISABLE();
362 // update magic pattern to indicate this is a suspend
363 // k2: MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR
364 // magpie: MAGPIE_REG_RST_STATUS_ADDR
365 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
368 * Before USB suspend, USB DMA must be reset(refer to Otus)
369 * Otus runs the following statements only
370 * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0|BIT2 );
371 * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 );
372 * K2 must run the following statements additionally
373 * reg_data = (A_UINT32 *)(USB_CTRL_BASE_ADDRESS + 0x118);
374 * *reg_data = 0x00000000;
375 * *reg_data = 0x00000001;
376 * because of Hardware bug in K2
378 reg_data = (uint32_t *)(USB_CTRL_BASE_ADDRESS + 0x118);
379 *reg_data = 0x00000000;
381 // reset both usb(bit2)/wlan(bit1) dma
382 HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT2) );
383 HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0));
384 HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 );
386 *reg_data = 0x00000001;
388 /* MAC warem reset */
389 //reg_data = (uint32_t *)(K2_REG_MAC_BASE_ADDR + 0x7000);
390 //*reg_data = 0x00000001;
394 //*reg_data = 0x00000000;
396 //while (*reg_data) ;
398 A_PRINTF("\n change clock to 22 and go to suspend now!");
401 HAL_WORD_REG_WRITE(0x50040, (0x200|0|(1>>1)<<12));
402 A_UART_HWINIT((22*1000*1000), 19200);
406 * -- support more than 64 bytes command on ep4 --
408 void vUsb_Reg_Out_patch(void)
413 static volatile uint32_t *regaddr; // = (volatile uint32_t *) ZM_CMD_BUFFER;
414 static uint16_t cmdLen;
416 BOOLEAN cmd_is_last = FALSE;
417 static BOOLEAN cmd_is_new = TRUE;
419 // get the size of this transcation
420 usbfifolen = USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_LOW_OFFSET);
421 if (usbfifolen > 0x40) {
422 A_PRINTF("EP4 FIFO Bug? Buffer is too big: %x\n", usbfifolen);
426 // check is command is new
429 buf = usbFifoConf.get_command_buf();
435 // copy free, assignment buffer of the address
436 regaddr = (uint32_t *)buf->desc_list->buf_addr;
441 // just in case, suppose should not happen
445 // if size is smaller, this is the last command!
447 // zero-length supposed should be set through 0x27/bit7->0x19/bit4, not here
449 if( usbfifolen<bUSB_EP_MAX_PKT_SIZE_64 ) {
453 // accumulate the size
454 cmdLen += usbfifolen;
456 // round it to alignment
458 usbfifolen = (usbfifolen >> 2) + 1;
460 usbfifolen = usbfifolen >> 2;
462 // A_PRINTF("copy data out from fifo to - %p\n\r", regaddr);
463 // retrieve the data from fifo
464 for(ii = 0; ii < usbfifolen; ii++)
466 ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out
471 // if this is the last command, callback to HTC
474 buf->desc_list->next_desc = NULL;
475 buf->desc_list->data_offset = 0;
476 buf->desc_list->data_size = cmdLen;
477 buf->desc_list->control = 0;
478 buf->next_buf = NULL;
479 buf->buf_length = cmdLen;
481 usbFifoConf.recv_command(buf);
488 // we might get no command buffer here?
489 // but if we return here, the ep4 fifo will be lock out,
490 // so that we still read them out but just drop it ?
491 for(ii = 0; ii < usbfifolen; ii++)
493 ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out
497 //mUSB_STATUS_IN_INT_ENABLE();
504 * -- usb1.1 ep6 fix --
506 extern uint16_t u8UsbConfigValue;
507 extern uint16_t u8UsbInterfaceValue;
508 extern uint16_t u8UsbInterfaceAlternateSetting;
509 extern SetupPacket ControlCmd;
510 extern void vUsbClrEPx(void);
512 void vUSBFIFO_EP6Cfg_FS_patch(void)
514 #if (FS_C1_I0_A0_EP_NUMBER >= 6)
518 mUsbEPMap(EP6, FS_C1_I0_A0_EP6_MAP);
519 mUsbFIFOMap(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_MAP);
520 mUsbFIFOConfig(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_CONFIG);
522 for(i = FS_C1_I0_A0_EP6_FIFO_START + 1 ;
523 i < FS_C1_I0_A0_EP6_FIFO_START + FS_C1_I0_A0_EP6_FIFO_NO ; i ++)
525 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP6_FIFO_CONFIG & (~BIT7)) );
528 mUsbEPMxPtSzHigh(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff));
529 mUsbEPMxPtSzLow(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff));
530 mUsbEPinHighBandSet(EP6 , FS_C1_I0_A0_EP6_DIRECTION, FS_C1_I0_A0_EP6_MAX_PACKET);
534 void vUsbFIFO_EPxCfg_FS_patch(void)
536 switch (u8UsbConfigValue)
538 #if (FS_CONFIGURATION_NUMBER >= 1)
539 // Configuration 0X01
541 switch (u8UsbInterfaceValue)
543 #if (FS_C1_INTERFACE_NUMBER >= 1)
546 switch (u8UsbInterfaceAlternateSetting)
549 #if (FS_C1_I0_ALT_NUMBER >= 1)
550 // AlternateSetting 0
555 // patch up this ep6_fs config
556 vUSBFIFO_EP6Cfg_FS_patch();
578 BOOLEAN bSet_configuration_patch(void)
580 //A_PRINTF("bSet_configuration...\n\r");
582 bSet_configuration();
584 if (mLOW_BYTE(mDEV_REQ_VALUE()) == 0)
591 if (mUsbHighSpeedST()) // First judge HS or FS??
599 vUsbFIFO_EPxCfg_FS_patch();
605 eUsbCxFinishAction = ACT_DONE;
611 * -- support more than 64 bytes command on ep3 --
613 void vUsb_Status_In_patch(void)
618 BOOLEAN cmdEnd = FALSE;
620 static u16_t mBufLen;
621 static VBUF *evntbuf = NULL;
622 static volatile u32_t *regaddr;
623 static BOOLEAN cmd_is_new = TRUE;
627 evntbuf = usbFifoConf.get_event_buf();
628 if ( evntbuf != NULL )
630 regaddr = (u32_t *)VBUF_GET_DATA_ADDR(evntbuf);
631 mBufLen = evntbuf->buf_length;
635 mUSB_STATUS_IN_INT_DISABLE();
641 // if( mBufLen>bUSB_EP_MAX_PKT_SIZE_64 )
642 // A_PRINTF("EP3 send %d bytes to host \n", mBufLen);
646 if( mBufLen > bUSB_EP_MAX_PKT_SIZE_64 ) {
647 RegBufLen = bUSB_EP_MAX_PKT_SIZE_64;
648 mBufLen -= bUSB_EP_MAX_PKT_SIZE_64;
650 // TODO: 64 byes... controller supposed will take care of zero-length?
657 for(count = 0; count < (RegBufLen / 4); count++)
659 USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
663 remainder = RegBufLen % 4;
670 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
673 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
676 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
680 USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
682 // Restore CBus FIFO size to word size
683 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
686 mUSB_EP3_XFER_DONE();
688 // if( mBufLen<=bUSB_EP_MAX_PKT_SIZE_64 )
692 if ( evntbuf != NULL && cmdEnd )
694 usbFifoConf.send_event_done(evntbuf);
702 extern uint16_t *u8ConfigDescriptorEX;
703 extern uint16_t *pu8DescriptorEX;
704 extern uint16_t u16TxRxCounter;
705 extern BOOLEAN bGet_descriptor(void);
707 uint16_t ConfigDescriptorPatch[30];
709 #define EP3_TRANSFER_TYPE_OFFSET 17
710 #define EP3_INT_INTERVAL 19
711 #define EP4_TRANSFER_TYPE_OFFSET 21
712 #define EP4_INT_INTERVAL 22
714 BOOLEAN bGet_descriptor_patch(void)
716 if (mDEV_REQ_VALUE_HIGH() == 2) {
717 uint8_t *p = (uint8_t *)u8ConfigDescriptorEX;
719 /* Copy ConfigDescriptor */
720 ath_hal_memcpy(ConfigDescriptorPatch, p, sizeof(ConfigDescriptorPatch));
722 p = (uint8_t *)ConfigDescriptorPatch;
724 /* Patch the transfer type of EP3 and EP4 */
725 ConfigDescriptorPatch[EP3_TRANSFER_TYPE_OFFSET] = 0x0283;
726 ConfigDescriptorPatch[EP3_INT_INTERVAL] = 0x0700;
727 ConfigDescriptorPatch[EP4_TRANSFER_TYPE_OFFSET] = 0x4002;
728 ConfigDescriptorPatch[EP4_INT_INTERVAL] = 0x00;
730 switch (mDEV_REQ_VALUE_LOW())
732 case 0x00: // configuration no: 0
733 pu8DescriptorEX = ConfigDescriptorPatch;
734 u16TxRxCounter = ConfigDescriptorPatch[1];
735 //u16TxRxCounter = 46;
741 if (u16TxRxCounter > mDEV_REQ_LENGTH())
742 u16TxRxCounter = mDEV_REQ_LENGTH();
748 return bGet_descriptor();
752 extern BOOLEAN bStandardCommand(void);
754 BOOLEAN bStandardCommand_patch(void)
756 if (mDEV_REQ_REQ() == USB_SET_CONFIGURATION) {
759 #if ENABLE_SWAP_DATA_MODE
760 // SWAP FUNCTION should be enabled while DMA engine is not working,
761 // the best place to enable it is before we trigger the DMA
762 MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
763 MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
765 #if SYSTEM_MODULE_HP_EP5
766 MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
769 #if SYSTEM_MODULE_HP_EP6
770 MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
773 #endif //ENABLE_SWAP_DATA_MODE
777 return bStandardCommand();