target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_fifo.c

   1 #include "usb_defs.h"
   2 #include "usb_type.h"
   3 #include "usb_pre.h"
   4 #include "usb_extr.h"
   5 #include "usb_std.h"
   6 #include "dt_defs.h"
   7 #include "sys_cfg.h"
   8
   9 #include "athos_api.h"
  10
  11 #if SYSTEM_MODULE_USB
  12
  13 extern uint16_t       u8UsbConfigValue;
  14 extern uint16_t       u8UsbInterfaceValue;
  15 extern uint16_t       u8UsbInterfaceAlternateSetting;
  16
  17 #if 1
  18
  19 void mUsbEPMap(uint8_t EPn, uint8_t MAP)
  20 {
  21     //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x30+(EPn-1));
  22     //*reg = MAP;
  23     uint8_t reg = (0x30+(EPn-1));
  24
  25 //    A_PRINTF("=>mUsbEPMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg));
  26     USB_BYTE_REG_WRITE(reg, MAP );
  27
  28 //    A_PRINTF("<=mUsbEPMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg));
  29
  30     //zfUartSendStr("mUsbEPMap\r\n");
  31     //zfUartSendStrAndHex("EPn=", EPn);
  32     //zfUartSendStrAndHex("MAP=", MAP);
  33 }
  34
  35 void mUsbFIFOMap(uint8_t FIFOn, uint8_t MAP)
  36 {
  37     //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x80+FIFOn);
  38     //*reg = MAP;
  39
  40     uint8_t reg = (0x80+FIFOn);
  41
  42     reg = reg;
  43
  44 //    A_PRINTF("=>mUsbFIFOMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg));
  45     USB_BYTE_REG_WRITE( reg, MAP );
  46
  47 //    A_PRINTF("<=mUsbFIFOMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg));
  48     //zfUartSendStr("mUsbFIFOMap\r\n");
  49     //zfUartSendStrAndHex("FIFOn=", FIFOn);
  50     //zfUartSendStrAndHex("MAP=", MAP);
  51 }
  52
  53 void mUsbFIFOConfig(uint8_t FIFOn, uint8_t cfg)
  54 {
  55     //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x90+FIFOn);
  56     //*reg = cfg;
  57     uint8_t reg = (0x90+FIFOn);
  58
  59 //    A_PRINTF("=>mUsbFIFOConfig: write: %02x to %02x (0x%08x)\n\r", cfg , reg, USB_WORD_REG_READ(reg));
  60     USB_BYTE_REG_WRITE( reg, cfg );
  61
  62 //    A_PRINTF("<=mUsbFIFOConfig: write: %02x to %02x (0x%08x)\n\r", cfg , reg, USB_WORD_REG_READ(reg));
  63     //zfUartSendStr((uint8_t *)"mUsbFIFOConfig\r\n");
  64     //zfUartSendStrAndHex((uint8_t *)"FIFOn=", FIFOn);
  65     //zfUartSendStrAndHex((uint8_t *)"cfg=", cfg);
  66 }
  67
  68 void mUsbEPMxPtSzHigh(uint8_t EPn, uint8_t dir, uint16_t size)
  69 {
  70     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+EPn << 1));
  71     //*reg = (size >> 8) & 0xf;
  72     uint8_t reg = (ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+(EPn << 1)));
  73
  74 //    A_PRINTF("=>mUsbEPMxPtSzHigh: write: %02x to %02x (0x%08x)\n\r", ((size >> 8) & 0xff), reg, USB_WORD_REG_READ(reg));
  75     USB_BYTE_REG_WRITE(reg, ((size >> 8) & 0xff));
  76
  77 //    A_PRINTF("<=mUsbEPMxPtSzHigh: write: %02x to %02x (0x%08x)\n\r", ((size >> 8) & 0xff), reg, USB_WORD_REG_READ(reg));
  78     //USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+EPn << 1)), ((size >> 8) & 0xf));
  79 }
  80
  81 void mUsbEPMxPtSzLow(uint8_t EPn, uint8_t dir, uint16_t size)
  82 {
  83     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_LOW_OFFSET+(((dir) * 0x20)+EPn << 1));
  84     //*reg = (size & 0xff);
  85
  86     uint8_t reg = (ZM_EP_IN_MAX_SIZE_LOW_OFFSET+(((dir) * 0x20)+(EPn << 1)));
  87 //    A_PRINTF("=>mUsbEPMxPtSzLow: write: %02x to %02x (0x%08x)\n\r", (size & 0xff), reg, USB_WORD_REG_READ(reg));
  88     USB_BYTE_REG_WRITE(reg, (size & 0xff));
  89
  90 //    A_PRINTF("<=mUsbEPMxPtSzLow: write: %02x to %02x (0x%08x)\n\r", (size & 0xff), reg, USB_WORD_REG_READ(reg));
  91 }
  92
  93 void mUsbEPinHighBandSet(uint8_t EPn, uint8_t dir, uint16_t size)
  94 {
  95 #if 1
  96     //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1));
  97
  98     //*reg &= ~(BIT6 | BIT5);
  99     //*reg |= (((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir));
 100
 101     uint8_t reg = (ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1));
 102 //    uint8_t reg2 = (((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir));
 103     uint8_t reg2 = (((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir));
 104
 105 //    A_PRINTF("=>mUsbEPinHighBandSet(%d)(size:%d)(dir:%d): write: %02x to %02x (0x%08x)\n\r", EPn, size, dir, (USB_BYTE_REG_READ(reg)|reg2), reg, USB_WORD_REG_READ(reg));
 106     USB_BYTE_REG_WRITE(reg, (USB_BYTE_REG_READ(reg)&~(BIT6 | BIT5)));
 107     USB_BYTE_REG_WRITE(reg,  (USB_BYTE_REG_READ(reg)|reg2));
 108
 109 //    A_PRINTF("=>mUsbEPinHighBandSet(%d)(size:%d)(dir:%d): write: %02x to %02x (0x%08x)\n\r", EPn, size, dir, (USB_BYTE_REG_READ(reg)|reg2), reg, USB_WORD_REG_READ(reg));
 110 #endif
 111 }
 112
 113 #else
 114
 115 #define mUsbEPMap( EPn, MAP)    USB_BYTE_REG_WRITE( (0x30+(EPn-1)), MAP )
 116
 117 #define mUsbFIFOMap( FIFOn, MAP)    USB_BYTE_REG_WRITE( (0x80+FIFOn), MAP )
 118
 119 #define mUsbFIFOConfig(FIFOn, cfg)    USB_BYTE_REG_WRITE( (0x90+FIFOn), cfg )
 120
 121 #define mUsbEPMxPtSzHigh(EPn, dir, size)  USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+EPn << 1)), ((size >> 8) & 0xf))
 122
 123 #define mUsbEPMxPtSzLow(EPn, dir, size)   USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_LOW_OFFSET+(((dir) * 0x20)+EPn << 1)), (size & 0xff))
 124
 125 #define mUsbEPinHighBandSet( EPn, dir, size)                                                \
 126 {                                                                                                                       \
 127     USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)),  \
 128                     (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1))&(~(BIT6 | BIT5)))));       \
 129     USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)),  \
 130                     (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)|((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir)))));   \
 131 }
 132
 133 #endif
 134
 135 /////////////////////////////////////////////////////
 136 //      vUsbFIFO_EPxCfg_HS(void)
 137 //      Description:
 138 //          1. Configure the FIFO and EPx map
 139 //      input: none
 140 //      output: none
 141 /////////////////////////////////////////////////////
 142 void vUsbFIFO_EPxCfg_HS(void)
 143 {
 144
 145     int i;
 146
 147     switch (u8UsbConfigValue)
 148     {
 149         #if (HS_CONFIGURATION_NUMBER >= 1)
 150         // Configuration 0X01
 151         case 0X01:
 152             switch (u8UsbInterfaceValue)
 153             {
 154                 #if (HS_C1_INTERFACE_NUMBER >= 1)
 155                 // Interface 0
 156                 case 0:
 157                     switch (u8UsbInterfaceAlternateSetting)
 158                     {
 159                         #if (HS_C1_I0_ALT_NUMBER >= 1)
 160                         // AlternateSetting 0
 161                         case 0:
 162                             #if (HS_C1_I0_A0_EP_NUMBER >= 1)
 163                             //EP0X01
 164                             mUsbEPMap(EP1, HS_C1_I0_A0_EP1_MAP);
 165                             mUsbFIFOMap(HS_C1_I0_A0_EP1_FIFO_START, HS_C1_I0_A0_EP1_FIFO_MAP);
 166
 167                             mUsbFIFOMap(HS_C1_I0_A0_EP1_FIFO_START+1, HS_C1_I0_A0_EP1_FIFO_MAP);    //ryan
 168
 169                             mUsbFIFOConfig(HS_C1_I0_A0_EP1_FIFO_START, HS_C1_I0_A0_EP1_FIFO_CONFIG);
 170
 171                             for(i = HS_C1_I0_A0_EP1_FIFO_START + 1 ;
 172                                 i < HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO ;
 173                                 i ++)
 174                             {
 175                                 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP1_FIFO_CONFIG & (~BIT7)) );
 176                             }
 177
 178                             mUsbEPMxPtSzHigh(EP1, HS_C1_I0_A0_EP1_DIRECTION, (HS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff) );
 179                             mUsbEPMxPtSzLow(EP1, HS_C1_I0_A0_EP1_DIRECTION, (HS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff) );
 180                             mUsbEPinHighBandSet(EP1 , HS_C1_I0_A0_EP1_DIRECTION , HS_C1_I0_A0_EP1_MAX_PACKET);
 181
 182                             #endif
 183                             #if (HS_C1_I0_A0_EP_NUMBER >= 2)
 184                             //EP0X02
 185                             mUsbEPMap(EP2, HS_C1_I0_A0_EP2_MAP);
 186                             mUsbFIFOMap(HS_C1_I0_A0_EP2_FIFO_START, HS_C1_I0_A0_EP2_FIFO_MAP);
 187
 188                             mUsbFIFOMap(HS_C1_I0_A0_EP2_FIFO_START+1, HS_C1_I0_A0_EP2_FIFO_MAP);//ryan
 189
 190                             mUsbFIFOConfig(HS_C1_I0_A0_EP2_FIFO_START, HS_C1_I0_A0_EP2_FIFO_CONFIG);
 191
 192                             for(i = HS_C1_I0_A0_EP2_FIFO_START + 1 ;
 193                                 i < HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO ;
 194                                 i ++)
 195                             {
 196                                 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP2_FIFO_CONFIG & (~BIT7)) );
 197                             }
 198
 199                             mUsbEPMxPtSzHigh(EP2, HS_C1_I0_A0_EP2_DIRECTION, (HS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff) );
 200                             mUsbEPMxPtSzLow(EP2, HS_C1_I0_A0_EP2_DIRECTION, (HS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff) );
 201                             mUsbEPinHighBandSet(EP2 , HS_C1_I0_A0_EP2_DIRECTION , HS_C1_I0_A0_EP2_MAX_PACKET);
 202
 203                             #endif
 204                             #if (HS_C1_I0_A0_EP_NUMBER >= 3)
 205                             //EP0X03
 206                             mUsbEPMap(EP3, HS_C1_I0_A0_EP3_MAP);
 207                             mUsbFIFOMap(HS_C1_I0_A0_EP3_FIFO_START, HS_C1_I0_A0_EP3_FIFO_MAP);
 208                             mUsbFIFOConfig(HS_C1_I0_A0_EP3_FIFO_START, HS_C1_I0_A0_EP3_FIFO_CONFIG);
 209
 210                             for(i = HS_C1_I0_A0_EP3_FIFO_START + 1 ;
 211                                 i < HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO ;
 212                                 i ++)
 213                             {
 214                                 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP3_FIFO_CONFIG & (~BIT7)) );
 215                             }
 216
 217                             mUsbEPMxPtSzHigh(EP3, HS_C1_I0_A0_EP3_DIRECTION, (HS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff) );
 218                             mUsbEPMxPtSzLow(EP3, HS_C1_I0_A0_EP3_DIRECTION, (HS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff) );
 219                             mUsbEPinHighBandSet(EP3 , HS_C1_I0_A0_EP3_DIRECTION , HS_C1_I0_A0_EP3_MAX_PACKET);
 220
 221                             #endif
 222                             #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
 223                             //EP0X04
 224                             mUsbEPMap(EP4, HS_C1_I0_A0_EP4_MAP);
 225                             mUsbFIFOMap(HS_C1_I0_A0_EP4_FIFO_START, HS_C1_I0_A0_EP4_FIFO_MAP);
 226                             mUsbFIFOConfig(HS_C1_I0_A0_EP4_FIFO_START, HS_C1_I0_A0_EP4_FIFO_CONFIG);
 227
 228                             for(i = HS_C1_I0_A0_EP4_FIFO_START + 1 ;
 229                                 i < HS_C1_I0_A0_EP4_FIFO_START + HS_C1_I0_A0_EP4_FIFO_NO ;
 230                                 i ++)
 231                             {
 232                                 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP4_FIFO_CONFIG & (~BIT7)) );
 233                             }
 234
 235                             mUsbEPMxPtSzHigh(EP4, HS_C1_I0_A0_EP4_DIRECTION, (HS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff) );
 236                             mUsbEPMxPtSzLow(EP4, HS_C1_I0_A0_EP4_DIRECTION, (HS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff) );
 237                             mUsbEPinHighBandSet(EP4 , HS_C1_I0_A0_EP4_DIRECTION , HS_C1_I0_A0_EP4_MAX_PACKET);
 238
 239                             #endif
 240 //////////////////////////////////////////////////////////////
 241 #if SYSTEM_MODULE_HP_EP5
 242                             #if (HS_C1_I0_A0_EP_NUMBER >= 5)
 243                             //EP0X05
 244                             mUsbEPMap(EP5, HS_C1_I0_A0_EP5_MAP);
 245                             mUsbFIFOMap(HS_C1_I0_A0_EP5_FIFO_START, HS_C1_I0_A0_EP5_FIFO_MAP);
 246
 247                             mUsbFIFOMap(HS_C1_I0_A0_EP5_FIFO_START+1, HS_C1_I0_A0_EP5_FIFO_MAP);        //ryan
 248
 249                             mUsbFIFOConfig(HS_C1_I0_A0_EP5_FIFO_START, HS_C1_I0_A0_EP5_FIFO_CONFIG);
 250
 251                             for(i = HS_C1_I0_A0_EP5_FIFO_START + 1 ;
 252                                 i < HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO ;
 253                                 i ++)
 254                             {
 255                                 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP5_FIFO_CONFIG & (~BIT7)) );
 256                             }
 257
 258                             mUsbEPMxPtSzHigh(EP5, HS_C1_I0_A0_EP5_DIRECTION, (HS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff) );
 259                             mUsbEPMxPtSzLow(EP5, HS_C1_I0_A0_EP5_DIRECTION, (HS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff) );
 260                             mUsbEPinHighBandSet(EP5 , HS_C1_I0_A0_EP5_DIRECTION , HS_C1_I0_A0_EP5_MAX_PACKET);
 261                             #endif
 262 #endif //SYSTEM_MODULE_HP_EP5
 263
 264 //////////////////////////////////////////////////////////////
 265 #if SYSTEM_MODULE_HP_EP6
 266                             #if (HS_C1_I0_A0_EP_NUMBER >= 6)
 267                             //EP0X06
 268                             mUsbEPMap(EP6, HS_C1_I0_A0_EP6_MAP);
 269                             mUsbFIFOMap(HS_C1_I0_A0_EP6_FIFO_START, HS_C1_I0_A0_EP6_FIFO_MAP);
 270
 271                             mUsbFIFOMap(HS_C1_I0_A0_EP6_FIFO_START+1, HS_C1_I0_A0_EP6_FIFO_MAP);        //ryan
 272
 273                             mUsbFIFOConfig(HS_C1_I0_A0_EP6_FIFO_START, HS_C1_I0_A0_EP6_FIFO_CONFIG);
 274
 275                             for(i = HS_C1_I0_A0_EP6_FIFO_START + 1 ;
 276                                 i < HS_C1_I0_A0_EP6_FIFO_START + HS_C1_I0_A0_EP6_FIFO_NO ;
 277                                 i ++)
 278                             {
 279                                 mUsbFIFOConfig(i, (HS_C1_I0_A0_EP6_FIFO_CONFIG & (~BIT7)) );
 280                             }
 281
 282                             mUsbEPMxPtSzHigh(EP6, HS_C1_I0_A0_EP6_DIRECTION, (HS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff) );
 283                             mUsbEPMxPtSzLow(EP6, HS_C1_I0_A0_EP6_DIRECTION, (HS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff) );
 284                             mUsbEPinHighBandSet(EP6 , HS_C1_I0_A0_EP6_DIRECTION , HS_C1_I0_A0_EP6_MAX_PACKET);
 285                             #endif
 286                             break;
 287 #endif //SYSTEM_MODULE_HP_EP6
 288
 289                         #endif
 290                         default:
 291                             break;
 292                     }
 293                     break;
 294                 #endif
 295                 default:
 296                     break;
 297             }
 298             break;
 299         #endif
 300         default:
 301             break;
 302     }
 303     //mCHECK_STACK();
 304
 305 }
 306
 307 void vUsbFIFO_EPxCfg_FS(void)
 308 {
 309
 310 int i;
 311
 312     switch (u8UsbConfigValue)
 313     {
 314         #if (FS_CONFIGURATION_NUMBER >= 1)
 315         // Configuration 0X01
 316         case 0X01:
 317             switch (u8UsbInterfaceValue)
 318             {
 319                 #if (FS_C1_INTERFACE_NUMBER >= 1)
 320                 // Interface 0
 321                 case 0:
 322                     switch (u8UsbInterfaceAlternateSetting)
 323                     {
 324                         #if (FS_C1_I0_ALT_NUMBER >= 1)
 325                         // AlternateSetting 0
 326                         case 0:
 327                             #if (FS_C1_I0_A0_EP_NUMBER >= 1)
 328                             //EP0X01
 329                             mUsbEPMap(EP1, FS_C1_I0_A0_EP1_MAP);
 330                             mUsbFIFOMap(FS_C1_I0_A0_EP1_FIFO_START, FS_C1_I0_A0_EP1_FIFO_MAP);
 331                             mUsbFIFOConfig(FS_C1_I0_A0_EP1_FIFO_START, FS_C1_I0_A0_EP1_FIFO_CONFIG);
 332
 333                             for(i = FS_C1_I0_A0_EP1_FIFO_START + 1 ;
 334                                 i < FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO ;
 335                                 i ++)
 336                             {
 337                                 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP1_FIFO_CONFIG & (~BIT7)) );
 338                             }
 339
 340                             mUsbEPMxPtSzHigh(EP1, FS_C1_I0_A0_EP1_DIRECTION, (FS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff));
 341                             mUsbEPMxPtSzLow(EP1, FS_C1_I0_A0_EP1_DIRECTION, (FS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff));
 342                         //``.JWEI 2003/04/29
 343                             mUsbEPinHighBandSet(EP1 , FS_C1_I0_A0_EP1_DIRECTION, FS_C1_I0_A0_EP1_MAX_PACKET);
 344
 345                             #endif
 346                             #if (FS_C1_I0_A0_EP_NUMBER >= 2)
 347                             //EP0X02
 348                             mUsbEPMap(EP2, FS_C1_I0_A0_EP2_MAP);
 349                             mUsbFIFOMap(FS_C1_I0_A0_EP2_FIFO_START, FS_C1_I0_A0_EP2_FIFO_MAP);
 350                             mUsbFIFOConfig(FS_C1_I0_A0_EP2_FIFO_START, FS_C1_I0_A0_EP2_FIFO_CONFIG);
 351
 352                             for(i = FS_C1_I0_A0_EP2_FIFO_START + 1 ;
 353                                 i < FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO ;
 354                                 i ++)
 355                             {
 356                                 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP2_FIFO_CONFIG & (~BIT7)) );
 357                             }
 358
 359                             mUsbEPMxPtSzHigh(EP2, FS_C1_I0_A0_EP2_DIRECTION, (FS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff));
 360                             mUsbEPMxPtSzLow(EP2, FS_C1_I0_A0_EP2_DIRECTION, (FS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff));
 361                             mUsbEPinHighBandSet(EP2 , FS_C1_I0_A0_EP2_DIRECTION, FS_C1_I0_A0_EP2_MAX_PACKET);
 362
 363                             #endif
 364                             #if (FS_C1_I0_A0_EP_NUMBER >= 3)
 365                             //EP0X03
 366                             mUsbEPMap(EP3, FS_C1_I0_A0_EP3_MAP);
 367                             mUsbFIFOMap(FS_C1_I0_A0_EP3_FIFO_START, FS_C1_I0_A0_EP3_FIFO_MAP);
 368                             mUsbFIFOConfig(FS_C1_I0_A0_EP3_FIFO_START, FS_C1_I0_A0_EP3_FIFO_CONFIG);
 369
 370                             for(i = FS_C1_I0_A0_EP3_FIFO_START + 1 ;
 371                                 i < FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO ;
 372                                 i ++)
 373                             {
 374                                 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP3_FIFO_CONFIG & (~BIT7)) );
 375                             }
 376
 377                             mUsbEPMxPtSzHigh(EP3, FS_C1_I0_A0_EP3_DIRECTION, (FS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff));
 378                             mUsbEPMxPtSzLow(EP3, FS_C1_I0_A0_EP3_DIRECTION, (FS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff));
 379                             mUsbEPinHighBandSet(EP3 , FS_C1_I0_A0_EP3_DIRECTION, FS_C1_I0_A0_EP3_MAX_PACKET);
 380
 381                             #endif
 382                             #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
 383                             //EP0X04
 384                             mUsbEPMap(EP4, FS_C1_I0_A0_EP4_MAP);
 385                             mUsbFIFOMap(FS_C1_I0_A0_EP4_FIFO_START, FS_C1_I0_A0_EP4_FIFO_MAP);
 386                             mUsbFIFOConfig(FS_C1_I0_A0_EP4_FIFO_START, FS_C1_I0_A0_EP4_FIFO_CONFIG);
 387
 388                             for(i = FS_C1_I0_A0_EP4_FIFO_START + 1 ;
 389                                 i < FS_C1_I0_A0_EP4_FIFO_START + FS_C1_I0_A0_EP4_FIFO_NO ;
 390                                 i ++)
 391                             {
 392                                 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP4_FIFO_CONFIG & (~BIT7)) );
 393                             }
 394
 395                             mUsbEPMxPtSzHigh(EP4, FS_C1_I0_A0_EP4_DIRECTION, (FS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff));
 396                             mUsbEPMxPtSzLow(EP4, FS_C1_I0_A0_EP4_DIRECTION, (FS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff));
 397                             mUsbEPinHighBandSet(EP4 , FS_C1_I0_A0_EP4_DIRECTION, FS_C1_I0_A0_EP4_MAX_PACKET);
 398
 399                             #endif
 400                             #if (FS_C1_I0_A0_EP_NUMBER >= 5)
 401                             //EP0X05
 402                             mUsbEPMap(EP5, FS_C1_I0_A0_EP5_MAP);
 403                             mUsbFIFOMap(FS_C1_I0_A0_EP5_FIFO_START, FS_C1_I0_A0_EP5_FIFO_MAP);
 404                             mUsbFIFOConfig(FS_C1_I0_A0_EP5_FIFO_START, FS_C1_I0_A0_EP5_FIFO_CONFIG);
 405
 406                             for(i = FS_C1_I0_A0_EP5_FIFO_START + 1 ;
 407                                 i < FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO ;
 408                                 i ++)
 409                             {
 410                                 mUsbFIFOConfig(i, (FS_C1_I0_A0_EP5_FIFO_CONFIG & (~BIT7)) );
 411                             }
 412
 413                             mUsbEPMxPtSzHigh(EP5, FS_C1_I0_A0_EP5_DIRECTION, (FS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff));
 414                             mUsbEPMxPtSzLow(EP5, FS_C1_I0_A0_EP5_DIRECTION, (FS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff));
 415                             mUsbEPinHighBandSet(EP5 , FS_C1_I0_A0_EP5_DIRECTION, FS_C1_I0_A0_EP5_MAX_PACKET);
 416                             #endif
 417                             break;
 418                         #endif
 419                         default:
 420                             break;
 421                     }
 422                     break;
 423                 #endif
 424                 default:
 425                     break;
 426             }
 427             break;
 428         #endif
 429         default:
 430             break;
 431     }
 432     //mCHECK_STACK();
 433 }
 434
 435 #endif