target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/src/desc.h

   1 /************************************************************************/
   2 /*  Copyright (c) 2013 Qualcomm Atheros, All Rights Reserved.           */
   3 /*                                                                      */
   4 /*  Module Name : desc_def.h                                            */
   5 /*                                                                      */
   6 /*  Abstract                                                            */
   7 /*      This module contains DMA descriptor related definitions.        */
   8 /*                                                                      */
   9 /*  NOTES                                                               */
  10 /*      None                                                            */
  11 /*                                                                      */
  12 /************************************************************************/
  13
  14 #ifndef _DESC_DEFS_H
  15 #define _DESC_DEFS_H
  16
  17 #if 0
  18 #define BIG_ENDIAN
  19
  20 struct zsDmaDesc
  21 {
  22 #ifdef BIG_ENDIAN
  23
  24     volatile u16_t      ctrl;       // Descriptor control
  25     volatile u16_t      status;     // Descriptor status
  26
  27     volatile u16_t      totalLen;   // Total length
  28     volatile u16_t      dataSize;   // Data size
  29
  30 #else
  31     volatile u16_t      status;     // Descriptor status
  32     volatile u16_t      ctrl;       // Descriptor control
  33     volatile u16_t      dataSize;   // Data size
  34     volatile u16_t      totalLen;   // Total length
  35 #endif
  36     struct zsDmaDesc*   lastAddr;   // Last address of this chain
  37     volatile u32_t      dataAddr;   // Data buffer address
  38     struct zsDmaDesc*   nextAddr;   // Next TD address
  39 };
  40 #endif
  41
  42 /* Tx5 Dn Rx Up Int */
  43 #if 0
  44 #define ZM_TERMINATOR_NUMBER_B  8
  45
  46 #if ZM_BAR_AUTO_BA == 1
  47 #define ZM_TERMINATOR_NUMBER_BAR        1
  48 #else
  49 #define ZM_TERMINATOR_NUMBER_BAR        0
  50 #endif
  51
  52 #if ZM_INT_USE_EP2 == 1
  53 #define ZM_TERMINATOR_NUMBER_INT        1
  54 #else
  55 #define ZM_TERMINATOR_NUMBER_INT        0
  56 #endif
  57
  58 #define ZM_TX_DELAY_DESC_NUM    16
  59 #define ZM_TERMINATOR_NUMBER (8 + ZM_TERMINATOR_NUMBER_BAR + \
  60                                   ZM_TERMINATOR_NUMBER_INT + \
  61                                                               ZM_TX_DELAY_DESC_NUM)
  62
  63
  64 #define ZM_BLOCK_SIZE           (256+64)
  65 #define ZM_DESCRIPTOR_SIZE      (sizeof(struct zsDmaDesc))
  66 #endif
  67
  68 //#define ZM_FRAME_MEMORY_BASE    0x100000
  69 #if 0
  70 #if 1
  71 /* 64k */
  72 //#define ZM_FRAME_MEMROY_SIZE    0xf000
  73 /* 96k */
  74 //#define ZM_FRAME_MEMROY_SIZE    0x17000
  75
  76 #else
  77 /* fake phy */
  78 /* 128k / 96k */
  79 #define ZM_FRAME_MEMROY_SIZE    (ZM_BLOCK_SIZE+ZM_DESCRIPTOR_SIZE)*(160+60) + \
  80                                 (ZM_DESCRIPTOR_SIZE*ZM_TERMINATOR_NUMBER)+64
  81 #endif
  82
  83 #define ZM_BLOCK_NUMBER         ((ZM_FRAME_MEMROY_SIZE-(ZM_DESCRIPTOR_SIZE* \
  84                                 ZM_TERMINATOR_NUMBER)-64)/(ZM_BLOCK_SIZE \
  85                                 +ZM_DESCRIPTOR_SIZE))
  86 #define ZM_DESC_NUMBER          (ZM_BLOCK_NUMBER + ZM_TERMINATOR_NUMBER)
  87
  88 #define ZM_DESCRIPTOR_BASE              ZM_FRAME_MEMORY_BASE
  89 #define ZM_BLOCK_BUFFER_BASE    (((((ZM_BLOCK_NUMBER+ZM_TERMINATOR_NUMBER) \
  90                                 *ZM_DESCRIPTOR_SIZE) >> 6) << 6) + 0x40 \
  91                                 + ZM_FRAME_MEMORY_BASE)
  92
  93 #define ZM_DOWN_BLOCK_RATIO     2
  94 #define ZM_RX_BLOCK_RATIO       1
  95 /* Tx 16*2 = 32 packets => 32*(5*320) */
  96 #define ZM_TX_BLOCK_NUMBER      ZM_BLOCK_NUMBER * ZM_DOWN_BLOCK_RATIO / \
  97                                 (ZM_RX_BLOCK_RATIO + ZM_DOWN_BLOCK_RATIO)
  98 #define ZM_RX_BLOCK_NUMBER      ZM_BLOCK_NUMBER-ZM_TX_BLOCK_NUMBER
  99                                 //ZM_BLOCK_NUMBER * ZM_RX_BLOCK_RATIO / \
 100                                 //(ZM_RX_BLOCK_RATIO + ZM_DOWN_BLOCK_RATIO)
 101
 102
 103 #define ZM_TX_DELAY_DESC_BASE   ZM_FRAME_MEMORY_BASE + ZM_DESCRIPTOR_SIZE*(ZM_TERMINATOR_NUMBER-ZM_TX_DELAY_DESC_NUM)
 104 #endif
 105
 106 /* Erro code */
 107 #define ZM_ERR_FS_BIT           1
 108 #define ZM_ERR_LS_BIT           2
 109 #define ZM_ERR_OWN_BITS         3
 110 #define ZM_ERR_DATA_SIZE        4
 111 #define ZM_ERR_TOTAL_LEN        5
 112 #define ZM_ERR_DATA             6
 113 #define ZM_ERR_SEQ              7
 114 #define ZM_ERR_LEN              8
 115
 116 /* Status bits definitions */
 117 /* Own bits definitions */
 118 #define ZM_OWN_BITS_MASK        0x3
 119 #define ZM_OWN_BITS_SW          0x0
 120 #define ZM_OWN_BITS_HW          0x1
 121 #define ZM_OWN_BITS_SE          0x2
 122
 123 /* Control bits definitions */
 124 /* First segament bit */
 125 #define ZM_LS_BIT               0x100
 126 /* Last segament bit */
 127 #define ZM_FS_BIT               0x200
 128
 129 #if 0
 130 struct zsDmaQueue
 131 {
 132     struct zsDmaDesc* head;
 133     struct zsDmaDesc* terminator;
 134 };
 135 #endif
 136
 137 struct zsDmaQueue;
 138 struct szDmaDesc;
 139
 140 extern struct zsDmaDesc* zfDmaGetPacket(struct zsDmaQueue* q);
 141 extern void zfDmaReclaimPacket(struct zsDmaQueue* q, struct zsDmaDesc* desc);
 142 extern void zfDmaPutPacket(struct zsDmaQueue* q, struct zsDmaDesc* desc);
 143
 144 #endif /* #ifndef _DESC_DEFS_H */