target_firmware/magpie_fw_dev/build/magpie_1_1/inc/magpie_mem.h

   1 /*************************************************************************/
   2 /*  Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */
   3 /*                                                                       */
   4 /*  Module Name : mem_addrs.h                                            */
   5 /*                                                                       */
   6 /*  Abstract                                                             */
   7 /*      This file contains definition of the memory related information. */
   8 /*                                                                       */
   9 /*  NOTES                                                                */
  10 /*      None                                                             */
  11 /*                                                                       */
  12 /*************************************************************************/
  13
  14 #ifndef _MEM_ADDRS_H_
  15 #define _MEM_ADDRS_H_
  16
  17 #define SYS_ROM_BLOCK_SIZE                  (32*1024)
  18 #if MAGPIE_FPGA_RAM_256K == 1
  19 #define SYS_ROM_BLOCK_NUM               2         //ram 256K version is also rom 64k version
  20 #else
  21 #define SYS_ROM_BLOCK_NUM               3
  22 #endif
  23 #define SYS_ROM_SIZE                    (SYS_ROM_BLOCK_SIZE*SYS_ROM_BLOCK_NUM)
  24
  25 #if MAGPIE_FPGA_RAM_256K == 1
  26 #define SYS_RAM_BLOCK_SIZE              64*1024
  27 #else
  28 #define SYS_RAM_BLOCK_SIZE              40*1024
  29 #endif
  30
  31 #define SYS_RAM_BLOCK_NUM               4
  32 #define SYS_RAM_SZIE                    (SYS_RAM_BLOCK_SIZE*SYS_RAM_BLOCK_NUM)
  33
  34 /* instruction port area */
  35 #define SYS_I_R0M_REGION_0_BASE         0x8e0000
  36
  37 #define SYS_I_RAM_REGION_0_BASE         0x900000
  38 #define SYS_I_RAM_REGION_1_BASE         (SYS_I_RAM_REGION_0_BASE+SYS_RAM_BLOCK_SIZE)
  39 #define SYS_I_RAM_REGION_2_BASE         (SYS_I_RAM_REGION_1_BASE+SYS_RAM_BLOCK_SIZE)
  40 #define SYS_I_RAM_REGION_3_BASE         (SYS_I_RAM_REGION_2_BASE+SYS_RAM_BLOCK_SIZE)
  41
  42 /* data port area */
  43 #define SYS_D_R0M_REGION_0_BASE         0x4e0000
  44
  45 #define SYS_D_RAM_REGION_0_BASE         0x500000
  46 #define SYS_D_RAM_REGION_1_BASE         (SYS_D_RAM_REGION_0_BASE+SYS_RAM_BLOCK_SIZE)
  47 #define SYS_D_RAM_REGION_2_BASE         (SYS_D_RAM_REGION_1_BASE+SYS_RAM_BLOCK_SIZE)
  48 #define SYS_D_RAM_REGION_3_BASE         (SYS_D_RAM_REGION_2_BASE+SYS_RAM_BLOCK_SIZE)
  49
  50 /* data and bss section */
  51
  52 #define SYS_D_RAM_DATA_BSS              SYS_D_RAM_REGION_0_BASE
  53 #define SYS_D_RAM_DATA_BSS_SZ           SYS_RAM_BLOCK_SIZE
  54 #define SYS_D_RAM_STACK_SIZE            (2*1024)
  55
  56 /////////////////////////////////////////////////////////////////////////////////////
  57 #define EEPROM_CTRL_BASE                0x10ff0000
  58 #define EEPROM_ADDR_BASE                (EEPROM_CTRL_BASE+0x2000)
  59
  60 #define EEPROM_SIZE                     0xfff   // 4K addressing space, each has 2 bytes, (a half word)
  61 #define EEPROM_START_OFFSET             0       // THIS SHOULD NOT MODIFY
  62 #define EEPROM_END_OFFSET               (EEPROM_START_OFFSET+EEPROM_SIZE)   // end of the eeprom offset
  63
  64 /////////////////////////////////////////////////////////////////////////////////////
  65 #define EEPROM_USB_DESCRIPTOR_ADDR      ((uint32_t)&_bss_end)  // address at RAM to put descriptor data
  66 #define USB_DESC_START_ADDR             0x80
  67 #define USB_DESCRIPTOR_ADDR             USB_DESC_START_ADDR     // eeprom offset to sotre the descriptor data
  68
  69 #define USB_DESC_IN_EEPROM_SIZE         2                       // indicate eeprom is exist in eeprom
  70 #define USB_DEVICE_DESCRIPTOR_SIZE      16                      // Device Descriptor
  71 #define USB_STRING00_DESCRIPTOR_SIZE    6                       // 16 half word
  72 #define USB_STRING10_DESCRIPTOR_SIZE    12                      // Manufacture data
  73 #define USB_STRING20_DESCRIPTOR_SIZE    16                      // Product/Company data
  74 #define USB_STRING30_DESCRIPTOR_SIZE    8                       // Serial Number
  75
  76 #define USB_DEVICE_PID_SIZE             1                       // PID SIZE, 1 halfword offset
  77 #define USB_DEVICE_VID_SIZE             1                       // VID SIZE, 1 halfword offset
  78
  79 #define USB_DESC_IN_EEPROM_FLAG_OFFSET  USB_DESCRIPTOR_ADDR
  80 #define USB_DEVICE_DESCRIPTOR_OFFSET    (USB_DESC_IN_EEPROM_FLAG_OFFSET+USB_DESC_IN_EEPROM_SIZE)
  81 #define USB_STRING00_DESCRIPTOR_OFFSET  (USB_DEVICE_DESCRIPTOR_OFFSET+USB_DEVICE_DESCRIPTOR_SIZE)
  82 #define USB_STRING10_DESCRIPTOR_OFFSET  (USB_STRING00_DESCRIPTOR_OFFSET+USB_STRING00_DESCRIPTOR_SIZE)
  83 #define USB_STRING20_DESCRIPTOR_OFFSET  (USB_STRING10_DESCRIPTOR_OFFSET+USB_STRING10_DESCRIPTOR_SIZE)
  84 #define USB_STRING30_DESCRIPTOR_OFFSET  (USB_STRING20_DESCRIPTOR_OFFSET+USB_STRING20_DESCRIPTOR_SIZE)
  85
  86 #define USB_DEVICE_VID_OFFSET           (USB_DEVICE_DESCRIPTOR_OFFSET+4)
  87 #define USB_DEVICE_PID_OFFSET           (USB_DEVICE_VID_OFFSET+USB_DEVICE_VID_SIZE)
  88
  89 #define USB_DESC_IN_EEPROM_FLAG_ADDR    EEPROM_USB_DESCRIPTOR_ADDR
  90 #define USB_DEVICE_DESCRIPTOR_ADDR      (USB_DESC_IN_EEPROM_FLAG_ADDR+(USB_DESC_IN_EEPROM_SIZE*2))
  91 #define USB_STRING00_DESCRIPTOR_ADDR    (USB_DEVICE_DESCRIPTOR_ADDR+(USB_DEVICE_DESCRIPTOR_SIZE*2))
  92 #define USB_STRING10_DESCRIPTOR_ADDR    (USB_STRING00_DESCRIPTOR_ADDR+(USB_STRING00_DESCRIPTOR_SIZE*2))
  93 #define USB_STRING20_DESCRIPTOR_ADDR    (USB_STRING10_DESCRIPTOR_ADDR+(USB_STRING10_DESCRIPTOR_SIZE*2))
  94 #define USB_STRING30_DESCRIPTOR_ADDR    (USB_STRING20_DESCRIPTOR_ADDR+(USB_STRING20_DESCRIPTOR_SIZE*2))
  95
  96 #define USB_DEVICE_VID_ADDR             (USB_DEVICE_DESCRIPTOR_ADDR+4)
  97 #define USB_DEVICE_PID_ADDR             (USB_DEVICE_VID_ADDR+USB_DEVICE_VID_SIZE)
  98
  99 #define USB_DESC_IN_EEP_PATTERN         0x41544852  //ATHR
 100
 101 /****************************** patch in eeprom *****************************************/
 102 #define ROM_PATCH_EEPROM_SIZE                   2                       // 4 bytes
 103
 104 #define ROM_PATCH_EEPROM_OFFSET         0xfc
 105
 106 // 16KB-2KB, the last 14KB for patch buffer is enough, since max EEPROM won't never bigger than this
 107 #define ROM_PATCH_BUF_ADDR              (SYS_D_RAM_REGION_3_BASE+SYS_RAM_BLOCK_SIZE-(SYS_RAM_BLOCK_SIZE>>2))
 108
 109 #endif /* _MEM_ADDRS_H_ */