-#define AR9170_PWR_REG_BASE 0x1d4000
-
-#define AR9170_PWR_REG_POWER_STATE (AR9170_PWR_REG_BASE + 0x000)
-
-#define AR9170_PWR_REG_ADDA_BB (AR9170_PWR_REG_BASE + 0x004)
-#define AR9170_PWR_ADDA_BB_USB_FIFO_RESET 0x00000005
-#define AR9170_PWR_ADDA_BB_COLD_RESET 0x00000800
-#define AR9170_PWR_ADDA_BB_WARM_RESET 0x00000400
-
-#define AR9170_PWR_REG_CLOCK_SEL (AR9170_PWR_REG_BASE + 0x008)
-#define AR9170_PWR_CLK_AHB_40MHZ 0
-#define AR9170_PWR_CLK_AHB_20_22MHZ 1
-#define AR9170_PWR_CLK_AHB_40_44MHZ 2
-#define AR9170_PWR_CLK_AHB_80_88MHZ 3
-#define AR9170_PWR_CLK_DAC_160_INV_DLY 0x70
-
-#define AR9170_PWR_REG_CHIP_REVISION (AR9170_PWR_REG_BASE + 0x010)
-#define AR9170_PWR_REG_PLL_ADDAC (AR9170_PWR_REG_BASE + 0x014)
-#define AR9170_PWR_REG_WATCH_DOG_MAGIC (AR9170_PWR_REG_BASE + 0x020)
-