carl9170 firmware: purge duplicated registers

Felix kindly pointed out:
	* SYNTH_CONTROL was introduced in the AR9002+ generation.

	* TXPWRADJ is of little relevance for AR9001.

	* M_SLEEP same as above, only of use on pre-11n chips.

Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>

diff --git a/include/shared/phy.h b/include/shared/phy.h
index e4beeda57371724918419f77c2ae06dd726f5684..6291fb2f059532ddcf6bf0c85d0b541aaf9bcbd5 100644 (file)
--- a/include/shared/phy.h
+++ b/include/shared/phy.h
@@ -159,8 +159,6 @@
 
 #define        AR9170_PHY_REG_SLEEP_CTR_CONTROL        (AR9170_PHY_REG_BASE + 0x0070)
 #define        AR9170_PHY_REG_SLEEP_CTR_LIMIT          (AR9170_PHY_REG_BASE + 0x0074)
-/* ??? same address ??? */
-#define        AR9170_PHY_REG_SYNTH_CONTROL            (AR9170_PHY_REG_BASE + 0x0074)
 #define        AR9170_PHY_REG_SLEEP_SCAL               (AR9170_PHY_REG_BASE + 0x0078)
 
 #define        AR9170_PHY_REG_PLL_CTL                  (AR9170_PHY_REG_BASE + 0x007c)
@@ -208,13 +206,6 @@
 #define                AR9170_PHY_FRAME_CTL_TX_CLIP            0x00000038
 #define                AR9170_PHY_FRAME_CTL_TX_CLIP_S          3
 
-#define        AR9170_PHY_REG_TXPWRADJ                 (AR9170_PHY_REG_BASE + 0x014c)
-#define                AR9170_PHY_TXPWRADJ_CCK_GAIN_DELTA      0x00000fc0
-#define                AR9170_PHY_TXPWRADJ_CCK_GAIN_DELTA_S    6
-#define                AR9170_PHY_TXPWRADJ_CCK_PCDAC_INDEX     0x00fc0000
-#define                AR9170_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S   18
-
-/* ??? same address ??? */
 #define        AR9170_PHY_REG_SPUR_REG                 (AR9170_PHY_REG_BASE + 0x014c)
 #define                AR9170_PHY_SPUR_REG_MASK_RATE_CNTL      (0xff << 18)
 #define                AR9170_PHY_SPUR_REG_MASK_RATE_CNTL_S    18
@@ -379,9 +370,6 @@
 #define                AR9170_PHY_CALMODE_ADC_DC_PER           0x00000002
 #define                AR9170_PHY_CALMODE_ADC_DC_INIT          0x00000003
 
-/* ??? same register ??? */
-#define        AR9170_PHY_REG_M_SLEEP                  (AR9170_PHY_REG_BASE + 0x01f0)
-
 #define        AR9170_PHY_REG_REFCLKDLY                (AR9170_PHY_REG_BASE + 0x01f4)
 #define        AR9170_PHY_REG_REFCLKPD                 (AR9170_PHY_REG_BASE + 0x01f8)