2 * Atheros AR9170 driver
4 * Hardware-specific definitions
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, see
20 * http://www.gnu.org/licenses/.
22 * This file incorporates work covered by the following copyright and
24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
26 * Permission to use, copy, modify, and/or distribute this software for any
27 * purpose with or without fee is hereby granted, provided that the above
28 * copyright notice and this permission notice appear in all copies.
30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
39 #ifndef __CARL9170_SHARED_WLAN_H
40 #define __CARL9170_SHARED_WLAN_H
44 #define AR9170_RX_PHY_RATE_CCK_1M 0x0a
45 #define AR9170_RX_PHY_RATE_CCK_2M 0x14
46 #define AR9170_RX_PHY_RATE_CCK_5M 0x37
47 #define AR9170_RX_PHY_RATE_CCK_11M 0x6e
49 #define AR9170_ENC_ALG_NONE 0x0
50 #define AR9170_ENC_ALG_WEP64 0x1
51 #define AR9170_ENC_ALG_TKIP 0x2
52 #define AR9170_ENC_ALG_AESCCMP 0x4
53 #define AR9170_ENC_ALG_WEP128 0x5
54 #define AR9170_ENC_ALG_WEP256 0x6
55 #define AR9170_ENC_ALG_CENC 0x7
57 #define AR9170_RX_ENC_SOFTWARE 0x8
59 #define AR9170_RX_STATUS_MODULATION_MASK 0x03
60 #define AR9170_RX_STATUS_MODULATION_CCK 0x00
61 #define AR9170_RX_STATUS_MODULATION_OFDM 0x01
62 #define AR9170_RX_STATUS_MODULATION_HT 0x02
63 #define AR9170_RX_STATUS_MODULATION_DUPOFDM 0x03
65 /* depends on modulation */
66 #define AR9170_RX_STATUS_SHORT_PREAMBLE 0x08
67 #define AR9170_RX_STATUS_GREENFIELD 0x08
69 #define AR9170_RX_STATUS_MPDU_MASK 0x30
70 #define AR9170_RX_STATUS_MPDU_SINGLE 0x00
71 #define AR9170_RX_STATUS_MPDU_FIRST 0x20
72 #define AR9170_RX_STATUS_MPDU_MIDDLE 0x30
73 #define AR9170_RX_STATUS_MPDU_LAST 0x10
75 #define AR9170_RX_ERROR_RXTO 0x01
76 #define AR9170_RX_ERROR_OVERRUN 0x02
77 #define AR9170_RX_ERROR_DECRYPT 0x04
78 #define AR9170_RX_ERROR_FCS 0x08
79 #define AR9170_RX_ERROR_WRONG_RA 0x10
80 #define AR9170_RX_ERROR_PLCP 0x20
81 #define AR9170_RX_ERROR_MMIC 0x40
82 #define AR9170_RX_ERROR_FATAL 0x80
84 /* these are either-or */
85 #define AR9170_TX_MAC_PROT_RTS 0x0001
86 #define AR9170_TX_MAC_PROT_CTS 0x0002
87 #define AR9170_TX_MAC_PROT_MASK 0x0003
89 #define AR9170_TX_MAC_NO_ACK 0x0004
90 /* if unset, MAC will only do SIFS space before frame */
91 #define AR9170_TX_MAC_BACKOFF 0x0008
92 #define AR9170_TX_MAC_BURST 0x0010
93 #define AR9170_TX_MAC_AGGR 0x0020
95 /* encryption is a two-bit field */
96 #define AR9170_TX_MAC_ENCR_NONE 0x0000
97 #define AR9170_TX_MAC_ENCR_RC4 0x0040
98 #define AR9170_TX_MAC_ENCR_CENC 0x0080
99 #define AR9170_TX_MAC_ENCR_AES 0x00c0
101 #define AR9170_TX_MAC_MMIC 0x0100
102 #define AR9170_TX_MAC_HW_DURATION 0x0200
103 #define AR9170_TX_MAC_QOS_S 10
104 #define AR9170_TX_MAC_QOS 0x0c00
105 #define AR9170_TX_MAC_DISABLE_TXOP 0x1000
106 #define AR9170_TX_MAC_TXOP_RIFS 0x2000
107 #define AR9170_TX_MAC_IMM_BA 0x4000
110 #define AR9170_TX_PHY_MOD_CCK 0x00000000
111 #define AR9170_TX_PHY_MOD_OFDM 0x00000001
112 #define AR9170_TX_PHY_MOD_HT 0x00000002
114 /* depends on modulation */
115 #define AR9170_TX_PHY_SHORT_PREAMBLE 0x00000004
116 #define AR9170_TX_PHY_GREENFIELD 0x00000004
118 #define AR9170_TX_PHY_BW_SHIFT 3
119 #define AR9170_TX_PHY_BW_MASK (3 << AR9170_TX_PHY_BW_SHIFT)
120 #define AR9170_TX_PHY_BW_20MHZ 0
121 #define AR9170_TX_PHY_BW_40MHZ 2
122 #define AR9170_TX_PHY_BW_40MHZ_DUP 3
124 #define AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT 6
125 #define AR9170_TX_PHY_TX_HEAVY_CLIP_MASK (7 << AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT)
127 #define AR9170_TX_PHY_TX_PWR_SHIFT 9
128 #define AR9170_TX_PHY_TX_PWR_MASK (0x3f << AR9170_TX_PHY_TX_PWR_SHIFT)
130 #define AR9170_TX_PHY_TXCHAIN_SHIFT 15
131 #define AR9170_TX_PHY_TXCHAIN_MASK (7 << AR9170_TX_PHY_TXCHAIN_SHIFT)
132 #define AR9170_TX_PHY_TXCHAIN_1 1
133 /* use for cck, ofdm 6/9/12/18/24 and HT if capable */
134 #define AR9170_TX_PHY_TXCHAIN_2 5
136 #define AR9170_TX_PHY_MCS_SHIFT 18
137 #define AR9170_TX_PHY_MCS_MASK (0x7f << AR9170_TX_PHY_MCS_SHIFT)
139 #define AR9170_TX_PHY_RATE_CCK_1M 0x0
140 #define AR9170_TX_PHY_RATE_CCK_2M 0x1
141 #define AR9170_TX_PHY_RATE_CCK_5M 0x2
142 #define AR9170_TX_PHY_RATE_CCK_11M 0x3
144 /* same as AR9170_RX_PHY_RATE */
145 #define AR9170_TXRX_PHY_RATE_OFDM_6M 0xb
146 #define AR9170_TXRX_PHY_RATE_OFDM_9M 0xf
147 #define AR9170_TXRX_PHY_RATE_OFDM_12M 0xa
148 #define AR9170_TXRX_PHY_RATE_OFDM_18M 0xe
149 #define AR9170_TXRX_PHY_RATE_OFDM_24M 0x9
150 #define AR9170_TXRX_PHY_RATE_OFDM_36M 0xd
151 #define AR9170_TXRX_PHY_RATE_OFDM_48M 0x8
152 #define AR9170_TXRX_PHY_RATE_OFDM_54M 0xc
154 #define AR9170_TXRX_PHY_RATE_HT_MCS0 0x0
155 #define AR9170_TXRX_PHY_RATE_HT_MCS1 0x1
156 #define AR9170_TXRX_PHY_RATE_HT_MCS2 0x2
157 #define AR9170_TXRX_PHY_RATE_HT_MCS3 0x3
158 #define AR9170_TXRX_PHY_RATE_HT_MCS4 0x4
159 #define AR9170_TXRX_PHY_RATE_HT_MCS5 0x5
160 #define AR9170_TXRX_PHY_RATE_HT_MCS6 0x6
161 #define AR9170_TXRX_PHY_RATE_HT_MCS7 0x7
162 #define AR9170_TXRX_PHY_RATE_HT_MCS8 0x8
163 #define AR9170_TXRX_PHY_RATE_HT_MCS9 0x9
164 #define AR9170_TXRX_PHY_RATE_HT_MCS10 0xa
165 #define AR9170_TXRX_PHY_RATE_HT_MCS11 0xb
166 #define AR9170_TXRX_PHY_RATE_HT_MCS12 0xc
167 #define AR9170_TXRX_PHY_RATE_HT_MCS13 0xd
168 #define AR9170_TXRX_PHY_RATE_HT_MCS14 0xe
169 #define AR9170_TXRX_PHY_RATE_HT_MCS15 0xf
171 #define AR9170_TX_PHY_SHORT_GI 0x80000000
173 #ifdef __CARL9170FW__
174 struct ar9170_tx_hw_mac_control {
178 * Beware of compiler bugs in all gcc pre 4.4!
205 struct ar9170_tx_hw_phy_control {
209 * Beware of compiler bugs in all gcc pre 4.4!
228 struct carl9170_tx_superdesc {
235 u8 ampdu_commit_density:1;
236 u8 ampdu_commit_factor:1;
237 u8 ampdu_unused_bit:1;
243 u8 tries[CARL9170_TX_MAX_RATES];
244 struct ar9170_tx_hw_phy_control rr[CARL9170_TX_MAX_RETRY_RATES];
247 struct ar9170_tx_hwdesc {
249 struct ar9170_tx_hw_mac_control mac;
250 struct ar9170_tx_hw_phy_control phy;
253 struct ar9170_tx_frame {
254 struct ar9170_tx_hwdesc hdr;
257 struct ieee80211_hdr i3e;
262 struct carl9170_tx_superframe {
263 struct carl9170_tx_superdesc s;
264 struct ar9170_tx_frame f;
267 #endif /* __CARL9170FW__ */
269 struct _ar9170_tx_hwdesc {
275 #define CARL9170_TX_SUPER_AMPDU_DENSITY_S 0
276 #define CARL9170_TX_SUPER_AMPDU_DENSITY 0x7
277 #define CARL9170_TX_SUPER_AMPDU_FACTOR 0x18
278 #define CARL9170_TX_SUPER_AMPDU_FACTOR_S 3
279 #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY 0x20
280 #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY_S 5
281 #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR 0x40
282 #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR_S 6
284 #define CARL9170_TX_SUPER_MISC_QUEUE 0x7
285 #define CARL9170_TX_SUPER_MISC_QUEUE_S 0
286 #define CARL9170_TX_SUPER_MISC_VIF_ID 0x38
287 #define CARL9170_TX_SUPER_MISC_VIF_ID_S 3
288 #define CARL9170_TX_SUPER_MISC_FILL_IN_TSF 0x40
289 #define CARL9170_TX_SUPER_MISC_CAB 0x80
291 struct _carl9170_tx_superdesc {
299 u8 tries[CARL9170_TX_MAX_RATES];
300 __le32 rr[CARL9170_TX_MAX_RETRY_RATES];
303 struct _carl9170_tx_superframe {
304 struct _carl9170_tx_superdesc s;
305 struct _ar9170_tx_hwdesc f;
309 #define CARL9170_TX_SUPERDESC_LEN 24
310 #define AR9170_TX_HWDESC_LEN 8
311 #define AR9170_TX_SUPERFRAME_LEN (CARL9170_TX_HWDESC_LEN + \
312 AR9170_TX_SUPERDESC_LEN)
314 struct ar9170_rx_head {
318 struct ar9170_rx_phystatus {
321 u8 rssi_ant0, rssi_ant1, rssi_ant2,
322 rssi_ant0x, rssi_ant1x, rssi_ant2x,
328 u8 evm_stream0[6], evm_stream1[6];
332 struct ar9170_rx_macstatus {
338 struct ar9170_rx_frame_single {
339 struct ar9170_rx_head phy_head;
340 struct ieee80211_hdr i3e;
341 struct ar9170_rx_phystatus phy_tail;
342 struct ar9170_rx_macstatus macstatus;
345 struct ar9170_rx_frame_head {
346 struct ar9170_rx_head phy_head;
347 struct ieee80211_hdr i3e;
348 struct ar9170_rx_macstatus macstatus;
351 struct ar9170_rx_frame_middle {
352 struct ieee80211_hdr i3e;
353 struct ar9170_rx_macstatus macstatus;
356 struct ar9170_rx_frame_tail {
357 struct ieee80211_hdr i3e;
358 struct ar9170_rx_phystatus phy_tail;
359 struct ar9170_rx_macstatus macstatus;
362 struct ar9170_rx_frame {
364 struct ar9170_rx_frame_single single;
365 struct ar9170_rx_frame_head head;
366 struct ar9170_rx_frame_middle middle;
367 struct ar9170_rx_frame_tail tail;
371 static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t)
373 return (t->SAidx & 0xc0) >> 4 |
374 (t->DAidx & 0xc0) >> 6;
389 static const u8 ar9170_qmap[__AR9170_NUM_TXQ] = { 2, 1, 0, 3 };
391 #define AR9170_TXQ_DEPTH 32
393 #endif /* __CARL9170_SHARED_WLAN_H */