carlfw/src/rf.c

   1 /*
   2  * carl9170 firmware - used by the ar9170 wireless device
   3  *
   4  * PHY and RF functions
   5  *
   6  * Copyright (c) 2000-2005 ZyDAS Technology Corporation
   7  * Copyright (c) 2007-2009 Atheros Communications, Inc.
   8  * Copyright    2009    Johannes Berg <johannes@sipsolutions.net>
   9  * Copyright 2009-2011  Christian Lamparter <chunkeey@googlemail.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License along
  22  * with this program; if not, write to the Free Software Foundation, Inc.,
  23  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  24  */
  25
  26 #include "carl9170.h"
  27 #include "timer.h"
  28 #include "printf.h"
  29 #include "rf.h"
  30 #include "shared/phy.h"
  31
  32 #ifdef CONFIG_CARL9170FW_RADIO_FUNCTIONS
  33 static void set_channel_start(void)
  34 {
  35         /* Manipulate CCA threshold to stop transmission */
  36         set(AR9170_PHY_REG_CCA_THRESHOLD, 0x300);
  37         /* Enable Virtual CCA */
  38         orl(AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA,
  39             AR9170_MAC_VIRTUAL_CCA_ALL);
  40 }
  41
  42 static void set_channel_end(void)
  43 {
  44         /* Manipulate CCA threshold to resume transmission */
  45         set(AR9170_PHY_REG_CCA_THRESHOLD, 0x0);
  46         /* Disable Virtual CCA */
  47         andl(AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA,
  48              ~AR9170_MAC_VIRTUAL_CCA_ALL);
  49 }
  50
  51 void rf_notify_set_channel(void)
  52 {
  53         set_channel_start();
  54 }
  55
  56 /*
  57  * Update delta slope coeff man and exp
  58  */
  59 static void hw_turn_off_dyn(const uint32_t delta_slope_coeff_exp,
  60                             const uint32_t delta_slope_coeff_man,
  61                             const uint32_t delta_slope_coeff_exp_shgi,
  62                             const uint32_t delta_slope_coeff_man_shgi)
  63 {
  64         uint32_t tmp;
  65
  66         tmp = get_async(AR9170_PHY_REG_TIMING3) & 0x00001fff;
  67         tmp |= (delta_slope_coeff_man << AR9170_PHY_TIMING3_DSC_MAN_S) &
  68                 AR9170_PHY_TIMING3_DSC_MAN;
  69         tmp |= (delta_slope_coeff_exp << AR9170_PHY_TIMING3_DSC_EXP_S) &
  70                 AR9170_PHY_TIMING3_DSC_EXP;
  71
  72         set(AR9170_PHY_REG_TIMING3, tmp);
  73
  74         tmp = (delta_slope_coeff_man_shgi << AR9170_PHY_HALFGI_DSC_MAN_S) &
  75                 AR9170_PHY_HALFGI_DSC_MAN;
  76
  77         tmp |= (delta_slope_coeff_exp_shgi << AR9170_PHY_HALFGI_DSC_EXP_S) &
  78                 AR9170_PHY_HALFGI_DSC_EXP;
  79
  80         set(AR9170_PHY_REG_HALFGI, tmp);
  81 }
  82
  83 static void program_ADDAC(void)
  84 {
  85         /* ??? Select Internal ADDAC ??? (is external radio) */
  86         set(AR9170_PHY_REG_ADC_SERIAL_CTL, AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO);
  87
  88         delay(10);
  89
  90         set(0x1c589c, 0x00000000);      /*# 7-0 */
  91         set(0x1c589c, 0x00000000);      /*# 15-8 */
  92         set(0x1c589c, 0x00000000);      /*# 23-16 */
  93         set(0x1c589c, 0x00000000);      /*# 31- */
  94
  95         set(0x1c589c, 0x00000000);      /*# 39- */
  96         set(0x1c589c, 0x00000000);      /*# 47- */
  97         set(0x1c589c, 0x00000000);      /*# 55- [48]:doubles the xtalosc bias current */
  98         set(0x1c589c, 0x00000000);      /*# 63- */
  99
 100         set(0x1c589c, 0x00000000);      /*# 71- */
 101         set(0x1c589c, 0x00000000);      /*# 79- */
 102         set(0x1c589c, 0x00000000);      /*# 87- */
 103         set(0x1c589c, 0x00000000);      /*# 95- */
 104
 105         set(0x1c589c, 0x00000000);      /*# 103- */
 106         set(0x1c589c, 0x00000000);      /*# 111- */
 107         set(0x1c589c, 0x00000000);      /*# 119- */
 108         set(0x1c589c, 0x00000000);      /*# 127- */
 109
 110         set(0x1c589c, 0x00000000);      /*# 135- */
 111         set(0x1c589c, 0x00000000);      /*# 143- */
 112         set(0x1c589c, 0x00000000);      /*# 151- */
 113         set(0x1c589c, 0x00000030);      /*# 159- #[158:156]=xlnabufmode */
 114
 115         set(0x1c589c, 0x00000004);      /*# 167-  [162]:disable clkp_driver to flow */
 116         set(0x1c589c, 0x00000000);      /*# 175- */
 117         set(0x1c589c, 0x00000000);      /*# 183-176 */
 118         set(0x1c589c, 0x00000000);      /*# 191-184 */
 119
 120         set(0x1c589c, 0x00000000);      /*# 199- */
 121         set(0x1c589c, 0x00000000);      /*# 207- */
 122         set(0x1c589c, 0x00000000);      /*# 215- */
 123         set(0x1c589c, 0x00000000);      /*# 223- */
 124
 125         set(0x1c589c, 0x00000000);      /*# 231- */
 126         set(0x1c58c4, 0x00000000);      /*# 233-232 */
 127
 128         delay(10);
 129
 130         /* Select External Flow ???? (is internal addac??) */
 131         set(AR9170_PHY_REG_ADC_SERIAL_CTL, AR9170_PHY_ADC_SCTL_SEL_INTERNAL_ADDAC);
 132 }
 133
 134 static uint32_t AGC_calibration(uint32_t loop)
 135 {
 136         uint32_t wrdata;
 137         uint32_t ret;
 138
 139 #define AGC_CAL_NF      (AR9170_PHY_AGC_CONTROL_CAL | AR9170_PHY_AGC_CONTROL_NF)
 140
 141         wrdata = get_async(AR9170_PHY_REG_AGC_CONTROL) | AGC_CAL_NF;
 142         set(AR9170_PHY_REG_AGC_CONTROL, wrdata);
 143
 144         ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
 145
 146         /* sitesurvey : 100 ms / current connected 200 ms */
 147         while ((ret != 0) && loop--) {
 148                 udelay(100);
 149
 150                 ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
 151         }
 152
 153         /* return the AGC/Noise calibration state to the driver */
 154         return ret;
 155 }
 156
 157 #define EIGHTY_FLAG (CARL9170FW_PHY_HT_ENABLE | CARL9170FW_PHY_HT_DYN2040)
 158
 159 static uint32_t rf_init(const uint32_t delta_slope_coeff_exp,
 160                         const uint32_t delta_slope_coeff_man,
 161                         const uint32_t delta_slope_coeff_exp_shgi,
 162                         const uint32_t delta_slope_coeff_man_shgi,
 163                         const uint32_t finiteLoopCount,
 164                         const bool initialize)
 165 {
 166         uint32_t ret;
 167
 168         hw_turn_off_dyn(delta_slope_coeff_exp,
 169                         delta_slope_coeff_man,
 170                         delta_slope_coeff_exp_shgi,
 171                         delta_slope_coeff_man_shgi);
 172
 173         if (initialize) {
 174                 /* Real Chip */
 175                 program_ADDAC();
 176
 177                 /* inverse chain 0 <-> chain 2 */
 178                 set(AR9170_PHY_REG_ANALOG_SWAP, AR9170_PHY_ANALOG_SWAP_AB);
 179
 180                 /* swap chain 0 and chain 2 */
 181                 set(AR9170_PHY_REG_ANALOG_SWAP, AR9170_PHY_ANALOG_SWAP_AB |
 182                                                 AR9170_PHY_ANALOG_SWAP_ALT_CHAIN);
 183
 184                 /* Activate BB */
 185                 set(AR9170_PHY_REG_ACTIVE, AR9170_PHY_ACTIVE_EN);
 186                 delay(10);
 187         }
 188
 189         ret = AGC_calibration(finiteLoopCount);
 190
 191         set_channel_end();
 192         return ret;
 193 }
 194
 195 void rf_cmd(const struct carl9170_cmd *cmd, struct carl9170_rsp *resp)
 196 {
 197         uint32_t ret;
 198
 199         fw.phy.ht_settings = cmd->rf_init.ht_settings;
 200         fw.phy.frequency = cmd->rf_init.freq;
 201
 202         /*
 203          * Is the clock controlled by the PHY?
 204          */
 205         if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
 206                 clock_set(AHB_80_88MHZ, true);
 207         else
 208                 clock_set(AHB_40_44MHZ, true);
 209
 210         ret = rf_init(le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp),
 211                       le32_to_cpu(cmd->rf_init.delta_slope_coeff_man),
 212                       le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp_shgi),
 213                       le32_to_cpu(cmd->rf_init.delta_slope_coeff_man_shgi),
 214                       le32_to_cpu(cmd->rf_init.finiteLoopCount),
 215                       cmd->hdr.cmd == CARL9170_CMD_RF_INIT);
 216
 217         resp->hdr.len = sizeof(struct carl9170_rf_init_result);
 218         resp->rf_init_res.ret = cpu_to_le32(ret);
 219 }
 220
 221 void rf_psm(void)
 222 {
 223         u32 bank3;
 224
 225         /*
 226          * FIXME: Does not work on 5GHz band!
 227          */
 228
 229         if (fw.phy.psm.state == CARL9170_PSM_SOFTWARE) {
 230                 /* not enabled by the driver */
 231                 return;
 232         }
 233
 234         if (fw.phy.psm.state & CARL9170_PSM_SLEEP) {
 235                 fw.phy.psm.state &= ~CARL9170_PSM_SLEEP;
 236
 237                 /* disable all agc gain and offset updates to a2 */
 238                 set(AR9170_PHY_REG_TEST2, 0x8000000);
 239
 240                 /* power down ADDAC */
 241                 set(AR9170_PHY_REG_ADC_CTL,
 242                     AR9170_PHY_ADC_CTL_OFF_PWDDAC |
 243                     AR9170_PHY_ADC_CTL_OFF_PWDADC |
 244                     0xa0000000);
 245
 246                 /* Synthesizer off + RX off */
 247                 bank3 = 0x00400018;
 248
 249                 clock_set(AHB_20_22MHZ, false);
 250         } else {
 251                 /* advance to the next PSM step */
 252                 fw.phy.psm.state--;
 253
 254                 if (fw.phy.psm.state == CARL9170_PSM_WAKE) {
 255                         /* wake up ADDAC */
 256                         set(AR9170_PHY_REG_ADC_CTL,
 257                             AR9170_PHY_ADC_CTL_OFF_PWDDAC |
 258                             AR9170_PHY_ADC_CTL_OFF_PWDADC);
 259
 260                         /* enable all agc gain and offset updates to a2 */
 261                         set(AR9170_PHY_REG_TEST2, 0x0);
 262
 263                         /* Synthesizer on + RX on */
 264                         bank3 = 0x01420098;
 265
 266                         if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
 267                                 clock_set(AHB_80_88MHZ, true);
 268                         else
 269                                 clock_set(AHB_40_44MHZ, true);
 270                 } else {
 271                         return ;
 272                 }
 273         }
 274
 275         if (fw.phy.frequency < 3000000)
 276                 bank3 |= 0x00800000;
 277
 278         set(0x1c58f0, bank3);
 279 }
 280
 281 #endif /* CONFIG_CARL9170FW_RADIO_FUNCTIONS */