carlfw/include/dma.h

   1 /*
   2  * carl9170 firmware - used by the ar9170 wireless device
   3  *
   4  * This module contains DMA descriptor related definitions.
   5  *
   6  * Copyright (c) 2000-2005 ZyDAS Technology Corporation
   7  * Copyright (c) 2007-2009 Atheros Communications, Inc.
   8  * Copyright    2009    Johannes Berg <johannes@sipsolutions.net>
   9  * Copyright 2009-2011  Christian Lamparter <chunkeey@googlemail.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License along
  22  * with this program; if not, write to the Free Software Foundation, Inc.,
  23  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  24  */
  25
  26 #ifndef __CARL9170FW_DMA_H
  27 #define __CARL9170FW_DMA_H
  28
  29 #include "config.h"
  30 #include "types.h"
  31 #include "compiler.h"
  32 #include "hw.h"
  33 #include "ieee80211.h"
  34 #include "wlan.h"
  35
  36 struct dma_desc {
  37         volatile uint16_t status;       /* Descriptor status */
  38         volatile uint16_t ctrl;         /* Descriptor control */
  39         volatile uint16_t dataSize;     /* Data size */
  40         volatile uint16_t totalLen;     /* Total length */
  41         struct dma_desc *lastAddr;      /* Last address of this chain */
  42         union {
  43                 uint8_t *_dataAddr;     /* Data buffer address */
  44                 void *dataAddr;
  45         } __packed;
  46         struct dma_desc *nextAddr;      /* Next TD address */
  47 } __packed __aligned(4);
  48
  49 /* Up, Dn, 5x Tx, retry, Rx, [USB Int], (CAB), (BA) */
  50 #define AR9170_TERMINATOR_NUMBER_B      9
  51
  52 #define AR9170_TERMINATOR_NUMBER_INT    1
  53
  54 #ifdef CONFIG_CARL9170FW_CAB_QUEUE
  55 #define AR9170_TERMINATOR_NUMBER_CAB    CARL9170_INTF_NUM
  56 #else
  57 #define AR9170_TERMINATOR_NUMBER_CAB    0
  58 #endif /* CONFIG_CARL9170FW_CAB_QUEUE */
  59
  60 #ifdef CONFIG_CARL9170FW_HANDLE_BACK_REQ
  61 #define AR9170_TERMINATOR_NUMBER_BA     1
  62 #else
  63 #define AR9170_TERMINATOR_NUMBER_BA     0
  64 #endif /* CONFIG_CARL9170FW_HANDLE_BACK_REQ */
  65 #define AR9170_TERMINATOR_NUMBER (AR9170_TERMINATOR_NUMBER_B + \
  66                                   AR9170_TERMINATOR_NUMBER_INT + \
  67                                   AR9170_TERMINATOR_NUMBER_CAB + \
  68                                   AR9170_TERMINATOR_NUMBER_BA)
  69
  70 #define AR9170_BLOCK_SIZE           (256 + 64)
  71
  72 #define AR9170_DESCRIPTOR_SIZE      (sizeof(struct dma_desc))
  73
  74 struct ar9170_tx_ba_frame {
  75         struct ar9170_tx_hwdesc hdr;
  76         struct ieee80211_ba ba;
  77 } __packed;
  78
  79 struct carl9170_tx_ba_superframe {
  80         struct carl9170_tx_superdesc s;
  81         struct ar9170_tx_ba_frame f;
  82 } __packed;
  83
  84 #define CARL9170_BA_BUFFER_LEN  (__roundup(sizeof(struct carl9170_tx_ba_superframe), 16))
  85 #define CARL9170_RSP_BUFFER_LEN AR9170_BLOCK_SIZE
  86
  87 struct carl9170_sram_reserved {
  88 #ifdef CONFIG_CARL9170FW_HANDLE_BACK_REQ
  89         union {
  90                 uint32_t buf[CARL9170_BA_BUFFER_LEN / sizeof(uint32_t)];
  91                 struct carl9170_tx_ba_superframe ba;
  92         } ba;
  93 #endif /* CONFIG_CARL9170FW_HANDLE_BACK_REQ */
  94         union {
  95                 uint32_t buf[CARL9170_MAX_CMD_LEN / sizeof(uint32_t)];
  96                 struct carl9170_cmd cmd;
  97         } cmd;
  98
  99         union {
 100                 uint32_t buf[CARL9170_RSP_BUFFER_LEN / sizeof(uint32_t)];
 101                 struct carl9170_rsp rsp;
 102         } rsp;
 103
 104         union {
 105                 uint32_t buf[CARL9170_INTF_NUM][AR9170_MAC_BCN_LENGTH_MAX / sizeof(uint32_t)];
 106         } bcn;
 107 };
 108
 109 /*
 110  * Memory layout in RAM:
 111  *
 112  * 0x100000                     +--
 113  *                              | terminator descriptors (dma_desc)
 114  *                              |  - Up (to USB host)
 115  *                              |  - Down (from USB host)
 116  *                              |  - TX (5x, to wifi)
 117  *                              |  - AMPDU TX retry
 118  *                              |  - RX (from wifi)
 119  *                              |  - CAB Queue
 120  *                              |  - FW cmd & req descriptor
 121  *                              |  - BlockAck descriptor
 122  *                              | total: AR9170_TERMINATOR_NUMBER
 123  *                              +--
 124  *                              | block descriptors (dma_desc)
 125  *                              | (AR9170_BLOCK_NUMBER)
 126  * AR9170_BLOCK_BUFFER_BASE     +-- align to multiple of 64
 127  *                              | block buffers (AR9170_BLOCK_SIZE each)
 128  *                              | (AR9170_BLOCK_NUMBER)
 129  * approx. 0x117c00             +--
 130  *                              | BA buffer (128 bytes)
 131  *                              +--
 132  *                              | CMD buffer (128 bytes)
 133  *                              +--
 134  *                              | RSP buffer (320 bytes)
 135  *                              +--
 136  *                              | BEACON buffer (256 bytes)
 137  *                              +--
 138  *                              | unaccounted space / padding
 139  *                              +--
 140  * 0x18000
 141  */
 142
 143 #define CARL9170_SRAM_RESERVED          (sizeof(struct carl9170_sram_reserved))
 144
 145 #define AR9170_FRAME_MEMORY_SIZE        (AR9170_SRAM_SIZE - CARL9170_SRAM_RESERVED)
 146
 147 #define BLOCK_ALIGNMENT         64
 148
 149 #define NONBLOCK_DESCRIPTORS_SIZE       \
 150         (AR9170_DESCRIPTOR_SIZE * (AR9170_TERMINATOR_NUMBER))
 151
 152 #define NONBLOCK_DESCRIPTORS_SIZE_ALIGNED       \
 153         (ALIGN(NONBLOCK_DESCRIPTORS_SIZE, BLOCK_ALIGNMENT))
 154
 155 #define AR9170_BLOCK_NUMBER     ((AR9170_FRAME_MEMORY_SIZE - NONBLOCK_DESCRIPTORS_SIZE_ALIGNED) / \
 156                                  (AR9170_BLOCK_SIZE + AR9170_DESCRIPTOR_SIZE))
 157
 158 struct ar9170_data_block {
 159         uint8_t data[AR9170_BLOCK_SIZE];
 160 };
 161
 162 struct ar9170_dma_memory {
 163         struct dma_desc                 terminator[AR9170_TERMINATOR_NUMBER];
 164         struct dma_desc                 block[AR9170_BLOCK_NUMBER];
 165         struct ar9170_data_block        data[AR9170_BLOCK_NUMBER] __aligned(BLOCK_ALIGNMENT);
 166         struct carl9170_sram_reserved   reserved __aligned(BLOCK_ALIGNMENT);
 167 };
 168
 169 extern struct ar9170_dma_memory dma_mem;
 170
 171 #define AR9170_DOWN_BLOCK_RATIO 2
 172 #define AR9170_RX_BLOCK_RATIO   1
 173 /* Tx 16*2 = 32 packets => 32*(5*320) */
 174 #define AR9170_TX_BLOCK_NUMBER  (AR9170_BLOCK_NUMBER * AR9170_DOWN_BLOCK_RATIO / \
 175                                 (AR9170_RX_BLOCK_RATIO + AR9170_DOWN_BLOCK_RATIO))
 176 #define AR9170_RX_BLOCK_NUMBER  (AR9170_BLOCK_NUMBER - AR9170_TX_BLOCK_NUMBER)
 177
 178 /* Error code */
 179 #define AR9170_ERR_FS_BIT       1
 180 #define AR9170_ERR_LS_BIT       2
 181 #define AR9170_ERR_OWN_BITS     3
 182 #define AR9170_ERR_DATA_SIZE    4
 183 #define AR9170_ERR_TOTAL_LEN    5
 184 #define AR9170_ERR_DATA         6
 185 #define AR9170_ERR_SEQ          7
 186 #define AR9170_ERR_LEN          8
 187
 188 /* Status bits definitions */
 189 /* Own bits definitions */
 190 #define AR9170_OWN_BITS         0x3
 191 #define AR9170_OWN_BITS_S       0
 192 #define AR9170_OWN_BITS_SW      0x0
 193 #define AR9170_OWN_BITS_HW      0x1
 194 #define AR9170_OWN_BITS_SE      0x2
 195
 196 /* Control bits definitions */
 197 #define AR9170_CTRL_TXFAIL      1
 198 #define AR9170_CTRL_BAFAIL      2
 199 #define AR9170_CTRL_FAIL        (AR9170_CTRL_TXFAIL | AR9170_CTRL_BAFAIL)
 200
 201 /* First segament bit */
 202 #define AR9170_CTRL_LS_BIT      0x100
 203 /* Last segament bit */
 204 #define AR9170_CTRL_FS_BIT      0x200
 205
 206 struct dma_queue {
 207         struct dma_desc *head;
 208         struct dma_desc *terminator;
 209 };
 210
 211 #define DESC_PAYLOAD(a)                 ((void *)a->dataAddr)
 212 #define DESC_PAYLOAD_OFF(a, offset)     ((void *)((unsigned long)(a->_dataAddr) + offset))
 213
 214 struct dma_desc *dma_unlink_head(struct dma_queue *queue);
 215 void dma_init_descriptors(void);
 216 void dma_reclaim(struct dma_queue *q, struct dma_desc *desc);
 217 void dma_put(struct dma_queue *q, struct dma_desc *desc);
 218
 219 static inline __inline bool is_terminator(struct dma_queue *q, struct dma_desc *desc)
 220 {
 221         return q->terminator == desc;
 222 }
 223
 224 static inline __inline bool queue_empty(struct dma_queue *q)
 225 {
 226         return q->head == q->terminator;
 227 }
 228
 229 /*
 230  * Get a completed packet with # descriptors. Return the first
 231  * descriptor and pointer the head directly by lastAddr->nextAddr
 232  */
 233 static inline __inline struct dma_desc *dma_dequeue_bits(struct dma_queue *q,
 234                                                 uint16_t bits)
 235 {
 236         struct dma_desc *desc = NULL;
 237
 238         if ((q->head->status & AR9170_OWN_BITS) == bits)
 239                 desc = dma_unlink_head(q);
 240
 241         return desc;
 242 }
 243
 244 static inline __inline struct dma_desc *dma_dequeue_not_bits(struct dma_queue *q,
 245                                                     uint16_t bits)
 246 {
 247         struct dma_desc *desc = NULL;
 248
 249         /* AR9170_OWN_BITS_HW will be filtered out here too. */
 250         if ((q->head->status & AR9170_OWN_BITS) != bits)
 251                 desc = dma_unlink_head(q);
 252
 253         return desc;
 254 }
 255
 256 #define for_each_desc_bits(desc, queue, bits)                           \
 257         while ((desc = dma_dequeue_bits(queue, bits)))
 258
 259 #define for_each_desc_not_bits(desc, queue, bits)                       \
 260         while ((desc = dma_dequeue_not_bits(queue, bits)))
 261
 262 #define for_each_desc(desc, queue)                                      \
 263         while ((desc = dma_unlink_head(queue)))
 264
 265 #define __for_each_desc_bits(desc, queue, bits)                         \
 266         for (desc = (queue)->head;                                      \
 267              (desc != (queue)->terminator &&                            \
 268              (desc->status & AR9170_OWN_BITS) == bits);                 \
 269              desc = desc->lastAddr->nextAddr)
 270
 271 #define __while_desc_bits(desc, queue, bits)                            \
 272         for (desc = (queue)->head;                                      \
 273              (!queue_empty(queue) &&                                    \
 274              (desc->status & AR9170_OWN_BITS) == bits);                 \
 275              desc = (queue)->head)
 276
 277 #define __for_each_desc_continue(desc, queue)                           \
 278         for (;desc != (queue)->terminator;                              \
 279              desc = (desc)->lastAddr->nextAddr)
 280
 281 #define __for_each_desc(desc, queue)                                    \
 282         for (desc = (queue)->head;                                      \
 283              desc != (queue)->terminator;                               \
 284              desc = (desc)->lastAddr->nextAddr)
 285
 286 #define __for_each_desc_safe(desc, tmp, queue)                          \
 287         for (desc = (queue)->head, tmp = desc->lastAddr->nextAddr;      \
 288              desc != (queue)->terminator;                               \
 289              desc = tmp, tmp = tmp->lastAddr->nextAddr)
 290
 291 #define __while_subdesc(desc, queue)                                    \
 292         for (desc = (queue)->head;                                      \
 293              desc != (queue)->terminator;                               \
 294              desc = (desc)->nextAddr)
 295
 296 static inline __inline unsigned int queue_len(struct dma_queue *q)
 297 {
 298         struct dma_desc *desc;
 299         unsigned int i = 0;
 300
 301         __while_subdesc(desc, q)
 302                 i++;
 303
 304         return i;
 305 }
 306
 307 /*
 308  * rearm a completed packet, so it will be processed agian.
 309  */
 310 static inline __inline void dma_rearm(struct dma_desc *desc)
 311 {
 312         /* Set OWN bit to HW */
 313         desc->status = ((desc->status & (~AR9170_OWN_BITS)) |
 314                         AR9170_OWN_BITS_HW);
 315 }
 316
 317 static inline __inline void dma_fix_downqueue(struct dma_desc *desc)
 318 {
 319         desc->status = AR9170_OWN_BITS_HW;
 320         desc->ctrl = 0;
 321         desc->dataSize = 0;
 322         desc->totalLen = AR9170_BLOCK_SIZE;
 323         desc->lastAddr = desc;
 324 }
 325
 326 static inline void __check_desc(void)
 327 {
 328         struct ar9170_dma_memory mem;
 329         BUILD_BUG_ON(sizeof(struct ar9170_data_block) != AR9170_BLOCK_SIZE);
 330         BUILD_BUG_ON(sizeof(struct dma_desc) != 20);
 331
 332         BUILD_BUG_ON(sizeof(mem) > AR9170_SRAM_SIZE);
 333
 334 #ifdef CONFIG_CARL9170FW_HANDLE_BACK_REQ
 335         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, ba.buf) & (BLOCK_ALIGNMENT - 1));
 336 #endif /* CONFIG_CARL9170FW_HANDLE_BACK_REQ */
 337         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, cmd.buf) & (BLOCK_ALIGNMENT - 1));
 338         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, rsp.buf) & (BLOCK_ALIGNMENT - 1));
 339         BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, bcn.buf) & (BLOCK_ALIGNMENT - 1));
 340 }
 341
 342 #endif /* __CARL9170FW_DMA_H */