2 * Copyright (C) 2006-2007 Michael Buesch <mb@bu3sch.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2
6 * as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
26 extern int yyparse(void);
30 const char *infile_name;
31 const char *outfile_name;
41 unsigned int operand; /* For NORMAL */
42 struct label *label; /* For LABELREF */
52 /* Set to true, if this is a jump instruction.
53 * This is only used when assembling RET to check
54 * whether the previous instruction was a jump or not. */
58 struct out_operand operands[3];
60 /* The absolute address of this instruction.
61 * Only used in resolve_labels(). */
64 const char *labelname; /* only for OUT_LABEL */
65 /* Set to 1, if this is the %start instruction. */
68 struct list_head list;
71 struct assembler_context {
72 /* The architecture version (802.11 core revision) */
75 struct label *start_label;
78 struct statement *cur_stmt;
80 struct list_head output;
84 #define for_each_statement(ctx, s) \
85 list_for_each_entry(s, &infile.sl, list) { \
88 #define for_each_statement_end(ctx, s) \
89 } do { ctx->cur_stmt = NULL; } while (0)
91 #define _msg_helper(type, stmt, msg, x...) do { \
92 fprintf(stderr, "Assembler " type); \
94 fprintf(stderr, " (file \"%s\", line %u)", \
98 fprintf(stderr, ":\n " msg "\n" ,##x); \
101 #define asm_error(ctx, msg, x...) do { \
102 _msg_helper("ERROR", (ctx)->cur_stmt, msg ,##x); \
106 #define asm_warn(ctx, msg, x...) \
107 _msg_helper("warning", (ctx)->cur_stmt, msg ,##x)
109 #define asm_info(ctx, msg, x...) \
110 _msg_helper("info", (ctx)->cur_stmt, msg ,##x)
113 static void eval_directives(struct assembler_context *ctx)
118 int have_start_label = 0;
121 for_each_statement(ctx, s) {
122 if (s->type == STMT_ASMDIR) {
127 asm_error(ctx, "Multiple %%arch definitions");
128 ctx->arch = ad->u.arch;
129 if (ctx->arch != 5 && ctx->arch != 15) {
130 asm_error(ctx, "Architecture version %u unsupported",
136 if (have_start_label)
137 asm_error(ctx, "Multiple %%start definitions");
138 ctx->start_label = ad->u.start;
139 have_start_label = 1;
142 asm_error(ctx, "Unknown ASM directive");
145 } for_each_statement_end(ctx, s);
148 asm_error(ctx, "No %%arch defined");
149 if (!have_start_label)
150 asm_info(ctx, "Using start address 0");
153 static bool is_possible_imm(unsigned int imm)
157 /* Immediates are only possible up to 16bit (wordsize). */
160 if (imm & (1 << 15)) {
161 if ((imm & mask) != mask &&
165 if ((imm & mask) != 0)
172 static unsigned int immediate_nr_bits(struct assembler_context *ctx)
176 return 10; /* 10 bits */
178 return 11; /* 11 bits */
180 asm_error(ctx, "Internal error: immediate_nr_bits unknown arch\n");
183 static bool is_valid_imm(struct assembler_context *ctx,
187 unsigned int immediate_size;
189 /* This function checks if the immediate value is representable
190 * as a native immediate operand.
192 * For v5 architecture the immediate can be 10bit long.
193 * For v15 architecture the immediate can be 11bit long.
195 * The value is sign-extended, so we allow values
196 * of 0xFFFA, for example.
199 if (!is_possible_imm(imm))
203 immediate_size = immediate_nr_bits(ctx);
205 /* First create a mask with all possible bits for
206 * an immediate value unset. */
207 mask = (~0 << immediate_size) & 0xFFFF;
208 /* Is the sign bit of the immediate set? */
209 if (imm & (1 << (immediate_size - 1))) {
210 /* Yes, so all bits above that must also
211 * be set, otherwise we can't represent this
212 * value in an operand. */
213 if ((imm & mask) != mask)
216 /* All bits above the immediate's size must
225 /* This checks if the value is nonzero and a power of two. */
226 static bool is_power_of_two(unsigned int value)
228 return (value && ((value & (value - 1)) == 0));
231 /* This checks if all bits set in the mask are contiguous.
232 * Zero is also considered a contiguous mask. */
233 static bool is_contiguous_bitmask(unsigned int mask)
235 unsigned int low_zeros_mask;
240 /* Turn the lowest zeros of the mask into a bitmask.
241 * Example: 0b00011000 -> 0b00000111 */
242 low_zeros_mask = (mask - 1) & ~mask;
243 /* Adding the low_zeros_mask to the original mask
244 * basically is a bitwise OR operation.
245 * If the original mask was contiguous, we end up with a
246 * contiguous bitmask from bit 0 to the highest bit
247 * set in the original mask. Adding 1 will result in a single
248 * bit set, which is a power of two. */
249 is_contiguous = is_power_of_two(mask + low_zeros_mask + 1);
251 return is_contiguous;
254 static unsigned int generate_imm_operand(struct assembler_context *ctx,
255 const struct immediate *imm)
257 unsigned int val, tmp;
265 if (!is_valid_imm(ctx, tmp)) {
266 asm_warn(ctx, "IMMEDIATE 0x%X (%d) too long "
267 "(> %u bits + sign). Did you intend to "
268 "use implicit sign extension?",
269 tmp, (int)tmp, immediate_nr_bits(ctx) - 1);
281 static unsigned int generate_reg_operand(struct assembler_context *ctx,
282 const struct registr *reg)
284 unsigned int val = 0;
291 if (reg->nr & ~0x3F) /* REVISIT: 128 regs for v15 arch possible? Probably not... */
292 asm_error(ctx, "GPR-nr too big");
299 if (reg->nr & ~0x1FF)
300 asm_error(ctx, "SPR-nr too big");
308 asm_error(ctx, "OFFR-nr too big");
312 asm_error(ctx, "generate_reg_operand() regtype");
318 static unsigned int generate_mem_operand(struct assembler_context *ctx,
319 const struct memory *mem)
321 unsigned int val = 0, off, reg, off_mask, reg_shift;
329 asm_warn(ctx, "DIRECT memoffset 0x%X too long (> 11 bits)", off);
335 asm_warn(ctx, "DIRECT memoffset 0x%X too long (> 12 bits)", off);
340 asm_error(ctx, "Internal error: generate_mem_operand invalid arch");
357 asm_error(ctx, "Internal error: MEM_INDIRECT invalid arch\n");
362 if (off & ~off_mask) {
363 asm_warn(ctx, "INDIRECT memoffset 0x%X too long (> %u bits)",
368 /* Assembler bug. The parser shouldn't pass this value. */
369 asm_error(ctx, "OFFR-nr too big");
372 asm_warn(ctx, "Using offset register 6. This register is broken "
373 "on certain devices. Use off0 to off5 only.");
376 val |= (reg << reg_shift);
379 asm_error(ctx, "generate_mem_operand() memtype");
385 static void generate_operand(struct assembler_context *ctx,
386 const struct operand *oper,
387 struct out_operand *out)
389 out->type = OUTOPER_NORMAL;
391 switch (oper->type) {
393 out->u.operand = generate_imm_operand(ctx, oper->u.imm);
396 out->u.operand = generate_reg_operand(ctx, oper->u.reg);
399 out->u.operand = generate_mem_operand(ctx, oper->u.mem);
402 out->type = OUTOPER_LABELREF;
403 out->u.label = oper->u.label;
406 out->u.operand = oper->u.addr->addr;
409 out->u.operand = oper->u.raw;
412 asm_error(ctx, "generate_operand() operstate");
416 static struct code_output * do_assemble_insn(struct assembler_context *ctx,
417 struct instruction *insn,
424 struct code_output *out;
425 struct label *labelref = NULL;
426 struct operand *oper;
427 int have_spr_operand = 0;
428 int have_mem_operand = 0;
430 out = xmalloc(sizeof(*out));
431 INIT_LIST_HEAD(&out->list);
432 out->opcode = opcode;
435 if (ARRAY_SIZE(out->operands) > ARRAY_SIZE(ol->oper))
436 asm_error(ctx, "Internal operand array confusion");
438 for (i = 0; i < ARRAY_SIZE(out->operands); i++) {
443 /* If this is an INPUT operand (first or second), we must
444 * make sure that not both are accessing SPR or MEMORY.
445 * The device only supports one SPR or MEMORY operand in
446 * the input operands. */
447 if ((i == 0) || (i == 1)) {
448 if ((oper->type == OPER_REG) &&
449 (oper->u.reg->type == SPR)) {
450 if (have_spr_operand)
451 asm_error(ctx, "Multiple SPR input operands in one instruction");
452 have_spr_operand = 1;
454 if (oper->type == OPER_MEM) {
455 if (have_mem_operand)
456 asm_error(ctx, "Multiple MEMORY input operands in on instruction");
457 have_mem_operand = 1;
461 generate_operand(ctx, oper, &out->operands[i]);
465 asm_error(ctx, "Internal error: nr_oper at "
466 "lowlevel do_assemble_insn");
468 list_add_tail(&out->list, &ctx->output);
473 static unsigned int merge_ext_into_opcode(struct assembler_context *ctx,
475 struct instruction *insn)
479 unsigned int mask, shift;
483 mask = ol->oper[0]->u.raw;
485 asm_error(ctx, "opcode MASK extension too big (> 0xF)");
486 shift = ol->oper[1]->u.raw;
488 asm_error(ctx, "opcode SHIFT extension too big (> 0xF)");
489 opcode |= (mask << 4);
491 ol->oper[0] = ol->oper[2];
492 ol->oper[1] = ol->oper[3];
493 ol->oper[2] = ol->oper[4];
498 static unsigned int merge_external_jmp_into_opcode(struct assembler_context *ctx,
500 struct instruction *insn)
502 struct operand *fake;
503 struct registr *fake_reg;
504 struct operand *target;
511 cond = ol->oper[0]->u.imm->imm;
513 asm_error(ctx, "External jump condition value too big (> 0xFF)");
515 target = ol->oper[1];
516 memset(ol->oper, 0, sizeof(ol->oper));
518 /* This instruction has two fake r0 operands
519 * at position 0 and 1. */
520 fake = xmalloc(sizeof(*fake));
521 fake_reg = xmalloc(sizeof(*fake_reg));
522 fake->type = OPER_REG;
523 fake->u.reg = fake_reg;
524 fake_reg->type = GPR;
529 ol->oper[2] = target;
534 static void assemble_instruction(struct assembler_context *ctx,
535 struct instruction *insn);
537 static void emulate_mov_insn(struct assembler_context *ctx,
538 struct instruction *insn)
540 struct instruction em_insn;
541 struct operlist em_ol;
542 struct operand em_op_shift;
543 struct operand em_op_mask;
544 struct operand em_op_x;
545 struct operand em_op_y;
546 struct immediate em_imm_x;
547 struct immediate em_imm_y;
549 struct operand *in, *out;
552 /* This is a pseudo-OP. We emulate it by OR or ORX */
554 in = insn->operands->oper[0];
555 out = insn->operands->oper[1];
560 em_op_x.type = OPER_IMM;
561 em_op_x.u.imm = &em_imm_x;
562 em_ol.oper[1] = &em_op_x;
565 if (in->type == OPER_IMM) {
566 tmp = in->u.imm->imm;
567 if (!is_possible_imm(tmp))
568 asm_error(ctx, "MOV operand 0x%X > 16bit", tmp);
569 if (!is_valid_imm(ctx, tmp)) {
570 /* Immediate too big for plain OR */
573 em_op_mask.type = OPER_RAW;
574 em_op_mask.u.raw = 0x7;
575 em_op_shift.type = OPER_RAW;
576 em_op_shift.u.raw = 0x8;
578 em_imm_x.imm = (tmp & 0xFF00) >> 8;
579 em_op_x.type = OPER_IMM;
580 em_op_x.u.imm = &em_imm_x;
582 em_imm_y.imm = (tmp & 0x00FF);
583 em_op_y.type = OPER_IMM;
584 em_op_y.u.imm = &em_imm_y;
586 em_ol.oper[0] = &em_op_mask;
587 em_ol.oper[1] = &em_op_shift;
588 em_ol.oper[2] = &em_op_x;
589 em_ol.oper[3] = &em_op_y;
594 em_insn.operands = &em_ol;
595 assemble_instruction(ctx, &em_insn); /* recurse */
598 static void emulate_jmp_insn(struct assembler_context *ctx,
599 struct instruction *insn)
601 struct instruction em_insn;
602 struct operlist em_ol;
603 struct immediate em_condition;
604 struct operand em_cond_op;
606 /* This is a pseudo-OP. We emulate it with
607 * JEXT 0x7F, target */
609 em_insn.op = OP_JEXT;
610 em_condition.imm = 0x7F; /* Ext cond: Always true */
611 em_cond_op.type = OPER_IMM;
612 em_cond_op.u.imm = &em_condition;
613 em_ol.oper[0] = &em_cond_op;
614 em_ol.oper[1] = insn->operands->oper[0]; /* Target */
615 em_insn.operands = &em_ol;
617 assemble_instruction(ctx, &em_insn); /* recurse */
620 static void emulate_jand_insn(struct assembler_context *ctx,
621 struct instruction *insn,
624 struct code_output *out;
625 struct instruction em_insn;
626 struct operlist em_ol;
627 struct operand em_op_shift;
628 struct operand em_op_mask;
629 struct operand em_op_y;
630 struct immediate em_imm;
632 struct operand *oper0, *oper1, *oper2;
633 struct operand *imm_oper = NULL;
635 int first_bit, last_bit;
637 oper0 = insn->operands->oper[0];
638 oper1 = insn->operands->oper[1];
639 oper2 = insn->operands->oper[2];
641 if (oper0->type == OPER_IMM)
643 if (oper1->type == OPER_IMM)
645 if (oper0->type == OPER_IMM && oper1->type == OPER_IMM)
649 /* We have a single immediate operand.
650 * Check if it's representable by a normal JAND insn.
652 tmp = imm_oper->u.imm->imm;
653 if (!is_valid_imm(ctx, tmp)) {
654 /* Nope, this must be emulated by JZX/JNZX */
655 if (!is_contiguous_bitmask(tmp)) {
656 asm_error(ctx, "Long bitmask 0x%X is not contiguous",
660 first_bit = ffs(tmp);
661 last_bit = ffs(~(tmp >> (first_bit - 1))) - 1 + first_bit - 1;
666 em_insn.op = OP_JNZX;
667 em_op_shift.type = OPER_RAW;
668 em_op_shift.u.raw = first_bit - 1;
669 em_op_mask.type = OPER_RAW;
670 em_op_mask.u.raw = last_bit - first_bit;
673 em_op_y.type = OPER_IMM;
674 em_op_y.u.imm = &em_imm;
676 em_ol.oper[0] = &em_op_mask;
677 em_ol.oper[1] = &em_op_shift;
678 if (oper0->type != OPER_IMM)
679 em_ol.oper[2] = oper0;
681 em_ol.oper[2] = oper1;
682 em_ol.oper[3] = &em_op_y;
683 em_ol.oper[4] = oper2;
685 em_insn.operands = &em_ol;
687 assemble_instruction(ctx, &em_insn); /* recurse */
692 /* Do a normal JAND/JNAND instruction */
694 out = do_assemble_insn(ctx, insn, 0x040 | 0x1);
696 out = do_assemble_insn(ctx, insn, 0x040);
697 out->is_jump_insn = 1;
700 static void assemble_instruction(struct assembler_context *ctx,
701 struct instruction *insn)
703 struct code_output *out;
708 do_assemble_insn(ctx, insn, 0x1C0);
711 do_assemble_insn(ctx, insn, 0x1C2);
714 do_assemble_insn(ctx, insn, 0x1C1);
717 do_assemble_insn(ctx, insn, 0x1C3);
720 do_assemble_insn(ctx, insn, 0x1D0);
723 do_assemble_insn(ctx, insn, 0x1D2);
726 do_assemble_insn(ctx, insn, 0x1D1);
729 do_assemble_insn(ctx, insn, 0x1D3);
732 do_assemble_insn(ctx, insn, 0x130);
735 do_assemble_insn(ctx, insn, 0x160);
738 do_assemble_insn(ctx, insn, 0x140);
741 do_assemble_insn(ctx, insn, 0x170);
744 do_assemble_insn(ctx, insn, 0x120);
747 opcode = merge_ext_into_opcode(ctx, 0x200, insn);
748 do_assemble_insn(ctx, insn, opcode);
751 do_assemble_insn(ctx, insn, 0x110);
754 do_assemble_insn(ctx, insn, 0x1A0);
757 do_assemble_insn(ctx, insn, 0x1B0);
760 do_assemble_insn(ctx, insn, 0x150);
763 opcode = merge_ext_into_opcode(ctx, 0x300, insn);
764 do_assemble_insn(ctx, insn, opcode);
767 emulate_mov_insn(ctx, insn);
770 emulate_jmp_insn(ctx, insn);
773 emulate_jand_insn(ctx, insn, 0);
776 emulate_jand_insn(ctx, insn, 1);
779 out = do_assemble_insn(ctx, insn, 0x050);
780 out->is_jump_insn = 1;
783 out = do_assemble_insn(ctx, insn, 0x050 | 0x1);
784 out->is_jump_insn = 1;
787 out = do_assemble_insn(ctx, insn, 0x0D0);
788 out->is_jump_insn = 1;
791 out = do_assemble_insn(ctx, insn, 0x0D0 | 0x1);
792 out->is_jump_insn = 1;
795 out = do_assemble_insn(ctx, insn, 0x0D2);
796 out->is_jump_insn = 1;
799 out = do_assemble_insn(ctx, insn, 0x0D2 | 0x1);
800 out->is_jump_insn = 1;
803 out = do_assemble_insn(ctx, insn, 0x0D4);
804 out->is_jump_insn = 1;
807 out = do_assemble_insn(ctx, insn, 0x0D4 | 0x1);
808 out->is_jump_insn = 1;
811 out = do_assemble_insn(ctx, insn, 0x0DA);
812 out->is_jump_insn = 1;
815 out = do_assemble_insn(ctx, insn, 0x0DA | 0x1);
816 out->is_jump_insn = 1;
819 out = do_assemble_insn(ctx, insn, 0x0DC);
822 out = do_assemble_insn(ctx, insn, 0x0DC | 0x1);
823 out->is_jump_insn = 1;
826 opcode = merge_ext_into_opcode(ctx, 0x400, insn);
827 out = do_assemble_insn(ctx, insn, opcode);
828 out->is_jump_insn = 1;
831 opcode = merge_ext_into_opcode(ctx, 0x500, insn);
832 out = do_assemble_insn(ctx, insn, opcode);
833 out->is_jump_insn = 1;
836 opcode = merge_external_jmp_into_opcode(ctx, 0x700, insn);
837 out = do_assemble_insn(ctx, insn, opcode);
838 out->is_jump_insn = 1;
841 opcode = merge_external_jmp_into_opcode(ctx, 0x600, insn);
842 out = do_assemble_insn(ctx, insn, opcode);
843 out->is_jump_insn = 1;
846 do_assemble_insn(ctx, insn, 0x002);
849 /* Get the previous instruction and check whether it
850 * is a jump instruction. */
851 list_for_each_entry_reverse(out, &ctx->output, list) {
852 /* Search the last insn. */
853 if (out->type == OUT_INSN) {
854 if (out->is_jump_insn) {
855 asm_warn(ctx, "RET instruction directly after "
856 "jump instruction. The hardware won't like this.");
861 do_assemble_insn(ctx, insn, 0x003);
867 do_assemble_insn(ctx, insn, 0x1E0);
870 do_assemble_insn(ctx, insn, 0x001);
873 do_assemble_insn(ctx, insn, insn->opcode);
876 asm_error(ctx, "Unknown op");
880 static void assemble_instructions(struct assembler_context *ctx)
883 struct instruction *insn;
884 struct code_output *out;
886 if (ctx->start_label) {
887 /* Generate a jump instruction at offset 0 to
888 * jump to the code start.
890 struct instruction sjmp;
894 oper.type = OPER_LABEL;
895 oper.u.label = ctx->start_label;
900 assemble_instruction(ctx, &sjmp);
901 out = list_entry(ctx->output.next, struct code_output, list);
902 out->is_start_insn = 1;
905 for_each_statement(ctx, s) {
910 assemble_instruction(ctx, insn);
913 out = xmalloc(sizeof(*out));
914 INIT_LIST_HEAD(&out->list);
915 out->type = OUT_LABEL;
916 out->labelname = s->u.label->name;
918 list_add_tail(&out->list, &ctx->output);
923 } for_each_statement_end(ctx, s);
926 /* Resolve a label reference to the address it points to. */
927 static int get_labeladdress(struct assembler_context *ctx,
928 struct code_output *this_insn,
929 struct label *labelref)
931 struct code_output *c;
935 switch (labelref->direction) {
936 case LABELREF_ABSOLUTE:
937 list_for_each_entry(c, &ctx->output, list) {
938 if (c->type != OUT_LABEL)
940 if (strcmp(c->labelname, labelref->name) != 0)
943 asm_error(ctx, "Ambiguous label reference \"%s\"",
947 address = c->address;
950 case LABELREF_RELATIVE_BACK:
951 for (c = list_entry(this_insn->list.prev, typeof(*c), list);
952 &c->list != &ctx->output;
953 c = list_entry(c->list.prev, typeof(*c), list)) {
954 if (c->type != OUT_LABEL)
956 if (strcmp(c->labelname, labelref->name) == 0) {
958 address = c->address;
963 case LABELREF_RELATIVE_FORWARD:
964 for (c = list_entry(this_insn->list.next, typeof(*c), list);
965 &c->list != &ctx->output;
966 c = list_entry(c->list.next, typeof(*c), list)) {
967 if (c->type != OUT_LABEL)
969 if (strcmp(c->labelname, labelref->name) == 0) {
971 address = c->address;
981 static void resolve_labels(struct assembler_context *ctx)
983 struct code_output *c;
986 unsigned int current_address;
988 /* Calculate the absolute addresses for each instruction. */
989 recalculate_addresses:
991 list_for_each_entry(c, &ctx->output, list) {
994 c->address = current_address;
998 c->address = current_address;
1003 /* Resolve the symbolic label references. */
1004 list_for_each_entry(c, &ctx->output, list) {
1007 if (c->is_start_insn) {
1008 /* If the first %start-jump jumps to 001, we can
1009 * optimize it away, as it's unneeded.
1012 if (c->operands[i].type != OUTOPER_LABELREF)
1013 asm_error(ctx, "Internal error, %%start insn oper 2 not labelref");
1014 if (c->operands[i].u.label->direction != LABELREF_ABSOLUTE)
1015 asm_error(ctx, "%%start label reference not absolute");
1016 addr = get_labeladdress(ctx, c, c->operands[i].u.label);
1018 goto does_not_exist;
1020 list_del(&c->list); /* Kill it */
1021 goto recalculate_addresses;
1025 for (i = 0; i < ARRAY_SIZE(c->operands); i++) {
1026 if (c->operands[i].type != OUTOPER_LABELREF)
1028 addr = get_labeladdress(ctx, c, c->operands[i].u.label);
1030 goto does_not_exist;
1031 c->operands[i].u.operand = addr;
1033 /* Is not a jump target.
1034 * Make it be an immediate */
1036 c->operands[i].u.operand |= 0xC00;
1037 else if (ctx->arch == 15)
1038 c->operands[i].u.operand |= 0xC00 << 1;
1040 asm_error(ctx, "Internal error: label res imm");
1051 asm_error(ctx, "Label \"%s\" does not exist",
1052 c->operands[i].u.label->name);
1055 static void emit_code(struct assembler_context *ctx)
1059 struct code_output *c;
1061 unsigned char outbuf[8];
1062 unsigned int insn_count = 0, insn_count_limit;
1063 struct fw_header hdr;
1066 fd = fopen(fn, "w+");
1068 fprintf(stderr, "Could not open microcode output file \"%s\"\n", fn);
1071 if (IS_VERBOSE_DEBUG)
1072 fprintf(stderr, "\nCode:\n");
1074 list_for_each_entry(c, &ctx->output, list) {
1084 switch (output_format) {
1090 memset(&hdr, 0, sizeof(hdr));
1091 hdr.type = FW_TYPE_UCODE;
1092 hdr.ver = FW_HDR_VER;
1093 hdr.size = cpu_to_be32(8 * insn_count);
1094 if (fwrite(&hdr, sizeof(hdr), 1, fd) != 1) {
1095 fprintf(stderr, "Could not write microcode outfile\n");
1101 switch (ctx->arch) {
1103 insn_count_limit = NUM_INSN_LIMIT_R5;
1106 insn_count_limit = ~0; //FIXME limit currently unknown.
1109 asm_error(ctx, "Internal error: emit_code unknown arch\n");
1111 if (insn_count > insn_count_limit)
1112 asm_warn(ctx, "Generating more than %u instructions. This "
1113 "will overflow the device microcode memory.",
1116 list_for_each_entry(c, &ctx->output, list) {
1119 if (IS_VERBOSE_DEBUG) {
1120 fprintf(stderr, "%03X %03X,%03X,%03X\n",
1122 c->operands[0].u.operand,
1123 c->operands[1].u.operand,
1124 c->operands[2].u.operand);
1127 switch (ctx->arch) {
1130 code |= ((uint64_t)c->operands[2].u.operand);
1131 code |= ((uint64_t)c->operands[1].u.operand) << 12;
1132 code |= ((uint64_t)c->operands[0].u.operand) << 24;
1133 code |= ((uint64_t)c->opcode) << 36;
1137 code |= ((uint64_t)c->operands[2].u.operand);
1138 code |= ((uint64_t)c->operands[1].u.operand) << 13;
1139 code |= ((uint64_t)c->operands[0].u.operand) << 26;
1140 code |= ((uint64_t)c->opcode) << 39;
1143 asm_error(ctx, "No emit format for arch %u",
1147 switch (output_format) {
1150 code = ((code & (uint64_t)0xFFFFFFFF00000000ULL) >> 32) |
1151 ((code & (uint64_t)0x00000000FFFFFFFFULL) << 32);
1152 outbuf[0] = (code & (uint64_t)0xFF00000000000000ULL) >> 56;
1153 outbuf[1] = (code & (uint64_t)0x00FF000000000000ULL) >> 48;
1154 outbuf[2] = (code & (uint64_t)0x0000FF0000000000ULL) >> 40;
1155 outbuf[3] = (code & (uint64_t)0x000000FF00000000ULL) >> 32;
1156 outbuf[4] = (code & (uint64_t)0x00000000FF000000ULL) >> 24;
1157 outbuf[5] = (code & (uint64_t)0x0000000000FF0000ULL) >> 16;
1158 outbuf[6] = (code & (uint64_t)0x000000000000FF00ULL) >> 8;
1159 outbuf[7] = (code & (uint64_t)0x00000000000000FFULL) >> 0;
1162 outbuf[7] = (code & (uint64_t)0xFF00000000000000ULL) >> 56;
1163 outbuf[6] = (code & (uint64_t)0x00FF000000000000ULL) >> 48;
1164 outbuf[5] = (code & (uint64_t)0x0000FF0000000000ULL) >> 40;
1165 outbuf[4] = (code & (uint64_t)0x000000FF00000000ULL) >> 32;
1166 outbuf[3] = (code & (uint64_t)0x00000000FF000000ULL) >> 24;
1167 outbuf[2] = (code & (uint64_t)0x0000000000FF0000ULL) >> 16;
1168 outbuf[1] = (code & (uint64_t)0x000000000000FF00ULL) >> 8;
1169 outbuf[0] = (code & (uint64_t)0x00000000000000FFULL) >> 0;
1173 if (fwrite(&outbuf, ARRAY_SIZE(outbuf), 1, fd) != 1) {
1174 fprintf(stderr, "Could not write microcode outfile\n");
1183 if (arg_print_sizes) {
1184 printf("%s: text = %u instructions (%u bytes)\n",
1186 (unsigned int)(insn_count * sizeof(uint64_t)));
1192 static void assemble(void)
1194 struct assembler_context ctx;
1196 memset(&ctx, 0, sizeof(ctx));
1197 INIT_LIST_HEAD(&ctx.output);
1199 eval_directives(&ctx);
1200 assemble_instructions(&ctx);
1201 resolve_labels(&ctx);
1205 static void initialize(void)
1207 INIT_LIST_HEAD(&infile.sl);
1208 INIT_LIST_HEAD(&infile.ivals);
1210 if (IS_INSANE_DEBUG)
1214 #endif /* YYDEBUG */
1217 int main(int argc, char **argv)
1221 err = parse_args(argc, argv);
1228 err = open_input_file();
1234 assemble_initvals();
1238 /* Lazyman simply leaks all allocated memory. */