This patch enables experimental support for 5 and 10 MHz channel.
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
/* PHY/RF state */
unsigned int frequency;
- unsigned int ht_settings;
+ unsigned int settings;
enum carl9170_phy_state state;
struct carl9170_psm psm;
}
}
-void clock_set(enum cpu_clock_t _clock, bool on);
+void clock_set(const enum cpu_clock_t _clock, const bool on, const unsigned int div);
void handle_timer(void);
void timer_init(const unsigned int timer, const unsigned int interval);
BIT(CARL9170FW_HW_COUNTERS) |
BIT(CARL9170FW_RX_BA_FILTER) |
BIT(CARL9170FW_USB_INIT_FIRMWARE) |
+ BIT(CARL9170FW_HALF_QUARTER_CHANNEL) |
#ifdef CONFIG_CARL9170FW_USB_UP_STREAM
BIT(CARL9170FW_USB_UP_STREAM) |
#endif /* CONFIG_CARL9170FW_USB_UP_STREAM */
void __section(boot) __noreturn __visible start(void)
{
- clock_set(AHB_40MHZ_OSC, true);
+ clock_set(AHB_40MHZ_OSC, true, 0);
/* watchdog magic pattern check */
if ((get(AR9170_PWR_REG_WATCH_DOG_MAGIC) & 0xffff0000) == 0x12340000) {
void rf_cmd(const struct carl9170_cmd *cmd, struct carl9170_rsp *resp)
{
- uint32_t ret;
+ uint32_t ret, div;
- fw.phy.ht_settings = cmd->rf_init.ht_settings;
+ fw.phy.settings = cmd->rf_init.settings;
fw.phy.frequency = cmd->rf_init.freq;
+ div = GET_VAL(CARL9170FW_PHY_RF_DIV, fw.phy.settings);
/*
* Is the clock controlled by the PHY?
*/
- if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
- clock_set(AHB_80_88MHZ, true);
+ if ((fw.phy.settings & EIGHTY_FLAG) == EIGHTY_FLAG)
+ clock_set(AHB_80_88MHZ, true, div);
else
- clock_set(AHB_40_44MHZ, true);
+ clock_set(AHB_40_44MHZ, true, div);
ret = rf_init(le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp),
le32_to_cpu(cmd->rf_init.delta_slope_coeff_man),
orl(AR9170_TIMER_REG_INTERRUPT, BIT(timer));
}
-void clock_set(enum cpu_clock_t clock_, bool on)
+void clock_set(const enum cpu_clock_t clock_, const bool on, const unsigned int div)
{
/*
* Word of Warning!
fw.ticks_per_usec = GET_VAL(AR9170_PWR_PLL_ADDAC_DIV,
get(AR9170_PWR_REG_PLL_ADDAC));
- set(AR9170_PWR_REG_CLOCK_SEL, (uint32_t) ((on ? 0x70 : 0x600) | clock_));
+ set(AR9170_PWR_REG_CLOCK_SEL, (uint32_t) ((on ? 0x70 : 0x600) | clock_ |
+ SET_CONSTVAL(AR9170_PWR_CLK_ADDAC_CLK160, div))));
switch (clock_) {
case AHB_20_22MHZ:
AR9170_PWR_RESET_WLAN_MASK);
set(AR9170_PWR_REG_RESET, 0x0);
- clock_set(AHB_20_22MHZ, false);
+ clock_set(AHB_20_22MHZ, false, 0);
set(AR9170_PWR_REG_PLL_ADDAC, 0x5163); /* 0x502b; */
set(AR9170_PHY_REG_ADC_SERIAL_CTL, AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO);
#define CARL9170FW_PHY_HT_DYN2040 0x8
#define CARL9170FW_PHY_HT_EXT_CHAN_OFF 0x3
#define CARL9170FW_PHY_HT_EXT_CHAN_OFF_S 2
+#define CARL9170FW_PHY_RF_DIV (BIT(4) | BIT(5))
+#define CARL9170FW_PHY_RF_BW_10MHZ BIT(4)
+#define CARL9170FW_PHY_RF_BW_5MHZ BIT(5)
+#define CARL9170FW_PHY_RF_DIV_S 4
+
struct carl9170_rf_init {
__le32 freq;
- u8 ht_settings;
+ u8 settings;
u8 padding2[3];
__le32 delta_slope_coeff_exp;
__le32 delta_slope_coeff_man;
/* Firmware will pass BA when BARs are queued */
CARL9170FW_RX_BA_FILTER,
+ /* Supports 10MHz / 5 MHz channels */
+ CARL9170FW_HALF_QUARTER_CHANNEL,
+
/* KEEP LAST */
__CARL9170FW_FEATURE_NUM
};
#define AR9170_PWR_CLK_AHB_20_22MHZ 1
#define AR9170_PWR_CLK_AHB_40_44MHZ 2
#define AR9170_PWR_CLK_AHB_80_88MHZ 3
+#define AR9170_PWR_CLK_ADDAC_CLK160 (BIT(2) | (BIT(3))
+#define AR9170_PWR_CLK_ADDAC_CLK160_S 2
#define AR9170_PWR_CLK_DAC_160_INV_DLY 0x70
#define AR9170_PWR_REG_CHIP_REVISION (AR9170_PWR_REG_BASE + 0x010)
CHECK_FOR_FEATURE(CARL9170FW_FIXED_5GHZ_PSM),
CHECK_FOR_FEATURE(CARL9170FW_HW_COUNTERS),
CHECK_FOR_FEATURE(CARL9170FW_RX_BA_FILTER),
+ CHECK_FOR_FEATURE(CARL9170FW_HALF_QUARTER_CHANNEL),
};
static void check_feature_list(const struct carl9170fw_desc_head *head,