1 // reset-unneeded.S -- Optional Extraneous Reset Code
2 // $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/reset-unneeded.S#2 $
4 // Copyright (c) 2002-2006 Tensilica Inc.
6 // Permission is hereby granted, free of charge, to any person obtaining
7 // a copy of this software and associated documentation files (the
8 // "Software"), to deal in the Software without restriction, including
9 // without limitation the rights to use, copy, modify, merge, publish,
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11 // permit persons to whom the Software is furnished to do so, subject to
12 // the following conditions:
14 // The above copyright notice and this permission notice shall be included
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20 // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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23 // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 // This file is meant to be included by another, e.g. crt1-***.S .
26 // The code it contains is generally not needed, so is kept in a
27 // separate file for clarity of other code.
29 #if XTOS_RESET_UNNEEDED
31 * Reset registers that don't really need to be reset,
32 * but may provide more predictability when buggy code
33 * relies on uninitialized state. It might also clear
34 * "X"s a bit earlier in hardware simulations.
36 * NOTE: This code is by no means exhaustive.
37 * More processor registers/states could be reset if desired.
38 * This is just an example.
40 * ASSUMPTION: a0 is still zero at this point.
43 // Interrupt initialization.
44 // Because INTENABLE is cleared by the reset vector, clearing the
45 // interrupt-pending register should not be needed. This assumes
46 // that any application setting up an interrupt will register and
47 // clear it before enabling it, which is the recommended sequence.
49 #if XCHAL_HAVE_INTERRUPTS && (XCHAL_INTCLEARABLE_MASK != 0) && !XCHAL_HAVE_FULL_RESET
50 movi a2, XCHAL_INTCLEARABLE_MASK
51 wsr a2, INTCLEAR // clear software and edge-trig ints
54 // Timer initialization (not strictly required, but sometimes helpful)
55 .macro reset_timer num
56 wsr a0, CCOMPARE_0 + \num
58 iterate 0, XCHAL_NUM_TIMERS-1, reset_timer
60 # if XCHAL_HAVE_WINDOWED
61 // Windowed address register init -- initialize entire physical AR file
62 movi a0, XCHAL_NUM_AREGS/8 // number of 8-register chunks
64 addi a8, a0, -1 // countdown into next chunk's a0
73 rotw 2 // rotate to next chunk
75 // NOTE: WINDOWBASE is back to zero at this point.
76 # else /* XCHAL_HAVE_WINDOWED */
77 // Non-windowed address register init
93 # endif /* XCHAL_HAVE_WINDOWED */
94 // Now all address registers are zero.
96 // Initialize LBEG, LEND, and LCOUNT.
98 wsr a0, LCOUNT // note: LCOUNT gets cleared by processor reset
103 # if XCHAL_HAVE_DEBUG
104 .macro reset_dbreaka num
105 wsr a0, DBREAKA + \num
107 .macro reset_ibreaka num
108 wsr a0, IBREAKA + \num
110 iterate 0, XCHAL_NUM_DBREAK-1, reset_dbreaka
111 iterate 0, XCHAL_NUM_IBREAK-1, reset_ibreaka
114 // SAR initialization
117 // Exception initialization
118 # if XCHAL_HAVE_EXCEPTIONS
124 # if XCHAL_HAVE_HIGHLEVEL_INTERRUPTS
128 wsr a0, EXCSAVE + \num
130 iterate 2, XCHAL_NUM_INTLEVELS, reset_int
133 // Booleans initialization
134 # if XCHAL_HAVE_BOOLEANS
138 // MAC16 initialization
139 # if XCHAL_HAVE_MAC16
148 // OCD initialization
153 isync // wait for all the above to take effect
155 #endif /* XTOS_RESET_UNNEEDED */