2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 /************************************************************************/
36 /* Copyright (c) 2013 Qualcomm Atheros, All Rights Reserved. */
38 /* Module Name : desc_def.h */
41 /* This module contains DMA descriptor related definitions. */
46 /************************************************************************/
58 volatile u16_t ctrl; // Descriptor control
59 volatile u16_t status; // Descriptor status
61 volatile u16_t totalLen; // Total length
62 volatile u16_t dataSize; // Data size
65 volatile u16_t status; // Descriptor status
66 volatile u16_t ctrl; // Descriptor control
67 volatile u16_t dataSize; // Data size
68 volatile u16_t totalLen; // Total length
70 struct zsDmaDesc* lastAddr; // Last address of this chain
71 volatile u32_t dataAddr; // Data buffer address
72 struct zsDmaDesc* nextAddr; // Next TD address
76 /* Tx5 Dn Rx Up Int */
78 #define ZM_TERMINATOR_NUMBER_B 8
80 #if ZM_BAR_AUTO_BA == 1
81 #define ZM_TERMINATOR_NUMBER_BAR 1
83 #define ZM_TERMINATOR_NUMBER_BAR 0
86 #if ZM_INT_USE_EP2 == 1
87 #define ZM_TERMINATOR_NUMBER_INT 1
89 #define ZM_TERMINATOR_NUMBER_INT 0
92 #define ZM_TX_DELAY_DESC_NUM 16
93 #define ZM_TERMINATOR_NUMBER (8 + ZM_TERMINATOR_NUMBER_BAR + \
94 ZM_TERMINATOR_NUMBER_INT + \
98 #define ZM_BLOCK_SIZE (256+64)
99 #define ZM_DESCRIPTOR_SIZE (sizeof(struct zsDmaDesc))
102 //#define ZM_FRAME_MEMORY_BASE 0x100000
106 //#define ZM_FRAME_MEMROY_SIZE 0xf000
108 //#define ZM_FRAME_MEMROY_SIZE 0x17000
113 #define ZM_FRAME_MEMROY_SIZE (ZM_BLOCK_SIZE+ZM_DESCRIPTOR_SIZE)*(160+60) + \
114 (ZM_DESCRIPTOR_SIZE*ZM_TERMINATOR_NUMBER)+64
117 #define ZM_BLOCK_NUMBER ((ZM_FRAME_MEMROY_SIZE-(ZM_DESCRIPTOR_SIZE* \
118 ZM_TERMINATOR_NUMBER)-64)/(ZM_BLOCK_SIZE \
119 +ZM_DESCRIPTOR_SIZE))
120 #define ZM_DESC_NUMBER (ZM_BLOCK_NUMBER + ZM_TERMINATOR_NUMBER)
122 #define ZM_DESCRIPTOR_BASE ZM_FRAME_MEMORY_BASE
123 #define ZM_BLOCK_BUFFER_BASE (((((ZM_BLOCK_NUMBER+ZM_TERMINATOR_NUMBER) \
124 *ZM_DESCRIPTOR_SIZE) >> 6) << 6) + 0x40 \
125 + ZM_FRAME_MEMORY_BASE)
127 #define ZM_DOWN_BLOCK_RATIO 2
128 #define ZM_RX_BLOCK_RATIO 1
129 /* Tx 16*2 = 32 packets => 32*(5*320) */
130 #define ZM_TX_BLOCK_NUMBER ZM_BLOCK_NUMBER * ZM_DOWN_BLOCK_RATIO / \
131 (ZM_RX_BLOCK_RATIO + ZM_DOWN_BLOCK_RATIO)
132 #define ZM_RX_BLOCK_NUMBER ZM_BLOCK_NUMBER-ZM_TX_BLOCK_NUMBER
133 //ZM_BLOCK_NUMBER * ZM_RX_BLOCK_RATIO / \
134 //(ZM_RX_BLOCK_RATIO + ZM_DOWN_BLOCK_RATIO)
137 #define ZM_TX_DELAY_DESC_BASE ZM_FRAME_MEMORY_BASE + ZM_DESCRIPTOR_SIZE*(ZM_TERMINATOR_NUMBER-ZM_TX_DELAY_DESC_NUM)
141 #define ZM_ERR_FS_BIT 1
142 #define ZM_ERR_LS_BIT 2
143 #define ZM_ERR_OWN_BITS 3
144 #define ZM_ERR_DATA_SIZE 4
145 #define ZM_ERR_TOTAL_LEN 5
146 #define ZM_ERR_DATA 6
150 /* Status bits definitions */
151 /* Own bits definitions */
152 #define ZM_OWN_BITS_MASK 0x3
153 #define ZM_OWN_BITS_SW 0x0
154 #define ZM_OWN_BITS_HW 0x1
155 #define ZM_OWN_BITS_SE 0x2
157 /* Control bits definitions */
158 /* First segament bit */
159 #define ZM_LS_BIT 0x100
160 /* Last segament bit */
161 #define ZM_FS_BIT 0x200
166 struct zsDmaDesc* head;
167 struct zsDmaDesc* terminator;
174 extern struct zsDmaDesc* zfDmaGetPacket(struct zsDmaQueue* q);
175 extern void zfDmaReclaimPacket(struct zsDmaQueue* q, struct zsDmaDesc* desc);
176 extern void zfDmaPutPacket(struct zsDmaQueue* q, struct zsDmaDesc* desc);
178 #endif /* #ifndef _DESC_DEFS_H */