2 xtensa/hal.h -- contains a definition of the Core HAL interface
4 All definitions in this header file are independent of any specific
5 Xtensa processor configuration. Thus software (eg. OS, application,
6 etc) can include this header file and be compiled into configuration-
7 independent objects that can be distributed and eventually linked
8 to the HAL library (libhal.a) to create a configuration-specific
11 Certain definitions, however, are release/version-specific -- such as
12 the XTHAL_RELEASE_xxx macros (or additions made in later versions).
15 $Id: //depot/rel/BadgerPass/Xtensa/OS/target-os-src/hal.h.tpp#2 $
17 Copyright (c) 1999-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
18 These coded instructions, statements, and computer programs are the
19 copyrighted works and confidential proprietary information of Tensilica Inc.
20 They may not be modified, copied, reproduced, distributed, or disclosed to
21 third parties in any manner, medium, or form, in whole or in part, without
22 the prior written consent of Tensilica Inc.
29 /****************************************************************************
30 Definitions Useful for Any Code, USER or PRIVILEGED
31 ****************************************************************************/
34 /*----------------------------------------------------------------------
35 Constant Definitions (shared with assembly)
36 ----------------------------------------------------------------------*/
39 * Software (Xtensa Tools) version information. Not configuration-specific!
41 * NOTE: "release" is a misnomer here, these are really product "version"
42 * numbers. A "release" is a collection of product versions
43 * made available at once (together) to customers.
44 * In the past, release and version names all matched in T####.# form,
45 * making the distinction irrelevant. This is no longer the case.
47 #define XTHAL_RELEASE_MAJOR 7010
48 #define XTHAL_RELEASE_MINOR 0
49 #define XTHAL_RELEASE_NAME "7.1.0"
51 #define XTHAL_REL_7_1 1
52 #define XTHAL_REL_7_1_0 1
54 /* HAL version numbers (these names are for backward compatibility): */
55 #define XTHAL_MAJOR_REV XTHAL_RELEASE_MAJOR
56 #define XTHAL_MINOR_REV XTHAL_RELEASE_MINOR
58 * A bit of software release/version history on values of XTHAL_{MAJOR,MINOR}_REV:
60 * SW Version MAJOR MINOR Comment
61 * ======= ===== ===== =======
62 * T1015.n n/a n/a (HAL not yet available)
63 * T1020.{0,1,2} 0 1 (HAL beta)
64 * T1020.{3,4} 0 2 First release.
65 * T1020.n (n>4) 0 2 or >3 (TBD)
66 * T1030.0 0 1 (HAL beta)
67 * T1030.{1,2} 0 3 Equivalent to first release.
68 * T1030.n (n>=3) 0 >= 3 (TBD)
69 * T1040.n 1040 n Full CHAL available from T1040.2
71 * 6.0.n 6000 n Xtensa Tools v6 (RA-200x.n)
72 * 7.0.n 7000 n Xtensa Tools v7 (RB-200x.n)
73 * 7.1.n 7010 n Xtensa Tools v7.1 (RB-200x.(n+2))
76 * Note: there is a distinction between the software version with
77 * which something is compiled (accessible using XTHAL_RELEASE_* macros)
78 * and the software version with which the HAL library was compiled
79 * (accessible using Xthal_release_* global variables). This
80 * distinction is particularly relevant for vendors that distribute
81 * configuration-independent binaries (eg. an OS), where their customer
82 * might link it with a HAL of a different Xtensa software version.
83 * In this case, it may be appropriate for the OS to verify at run-time
84 * whether XTHAL_RELEASE_* and Xthal_release_* are compatible.
85 * [Guidelines as to which version is compatible with which are not
86 * currently provided explicitly, but might be inferred from reading
87 * OSKit documentation for all releases -- compatibility is also highly
88 * dependent on which HAL features are used. Each version is usually
89 * backward compatible, with very few exceptions if any.]
92 * Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only.
93 * Tornado 2.0.2 supported in T1040.2+, T1050, and 6.0.
94 * Compile-time HAL port of NucleusPlus supported by T1040.2 and later.
97 /* Version comparison operators (among major/minor pairs): */
98 #define XTHAL_REL_GE(maja,mina, majb,minb) ((maja) > (majb) || \
99 ((maja) == (majb) && (mina) >= (minb)))
100 #define XTHAL_REL_GT(maja,mina, majb,minb) ((maja) > (majb) || \
101 ((maja) == (majb) && (mina) > (minb)))
102 #define XTHAL_REL_LE(maja,mina, majb,minb) ((maja) < (majb) || \
103 ((maja) == (majb) && (mina) <= (minb)))
104 #define XTHAL_REL_LT(maja,mina, majb,minb) ((maja) < (majb) || \
105 ((maja) == (majb) && (mina) < (minb)))
106 #define XTHAL_REL_EQ(maja,mina, majb,minb) ((maja) == (majb) && (mina) == (minb))
108 /* Fuzzy (3-way) logic operators: */
109 #define XTHAL_MAYBE -1 /* 0=NO, 1=YES, -1=MAYBE */
110 #define XTHAL_FUZZY_AND(a,b) (((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE)
111 #define XTHAL_FUZZY_OR(a,b) (((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE)
112 #define XTHAL_FUZZY_NOT(a) (((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE)
116 * Architectural limit, independent of configuration:
118 #define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */
121 #define XTHAL_LITTLEENDIAN 0
122 #define XTHAL_BIGENDIAN 1
126 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
131 /*----------------------------------------------------------------------
133 ----------------------------------------------------------------------*/
135 /* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */
136 extern const unsigned int Xthal_rev_no;
139 /*----------------------------------------------------------------------
140 Optional/Custom Processor State
141 ----------------------------------------------------------------------*/
143 /* save & restore the extra processor state */
144 extern void xthal_save_extra(void *base);
145 extern void xthal_restore_extra(void *base);
147 extern void xthal_save_cpregs(void *base, int);
148 extern void xthal_restore_cpregs(void *base, int);
149 /* versions specific to each coprocessor id */
150 extern void xthal_save_cp0(void *base);
151 extern void xthal_save_cp1(void *base);
152 extern void xthal_save_cp2(void *base);
153 extern void xthal_save_cp3(void *base);
154 extern void xthal_save_cp4(void *base);
155 extern void xthal_save_cp5(void *base);
156 extern void xthal_save_cp6(void *base);
157 extern void xthal_save_cp7(void *base);
158 extern void xthal_restore_cp0(void *base);
159 extern void xthal_restore_cp1(void *base);
160 extern void xthal_restore_cp2(void *base);
161 extern void xthal_restore_cp3(void *base);
162 extern void xthal_restore_cp4(void *base);
163 extern void xthal_restore_cp5(void *base);
164 extern void xthal_restore_cp6(void *base);
165 extern void xthal_restore_cp7(void *base);
166 /* pointers to each of the functions above */
167 extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS];
168 extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS];
169 /* similarly for non-windowed ABI (may be same or different) */
170 extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS];
171 extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS];
173 /*extern void xthal_save_all_extra(void *base);*/
174 /*extern void xthal_restore_all_extra(void *base);*/
176 /* space for processor state */
177 extern const unsigned int Xthal_extra_size;
178 extern const unsigned int Xthal_extra_align;
179 extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];
180 extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];
181 extern const unsigned int Xthal_all_extra_size;
182 extern const unsigned int Xthal_all_extra_align;
183 /* coprocessor names */
184 extern const char * const Xthal_cp_names[XTHAL_MAX_CPS];
186 /* initialize the extra processor */
187 /*extern void xthal_init_extra(void);*/
188 /* initialize the TIE coprocessor */
189 /*extern void xthal_init_cp(int);*/
191 /* initialize the extra processor */
192 extern void xthal_init_mem_extra(void *);
193 /* initialize the TIE coprocessor */
194 extern void xthal_init_mem_cp(void *, int);
196 /* the number of TIE coprocessors contiguous from zero (for Tor2) */
197 extern const unsigned int Xthal_num_coprocessors;
199 /* actual number of coprocessors */
200 extern const unsigned char Xthal_cp_num;
201 /* index of highest numbered coprocessor, plus one */
202 extern const unsigned char Xthal_cp_max;
203 /* index of highest allowed coprocessor number, per cfg, plus one */
204 /*extern const unsigned char Xthal_cp_maxcfg;*/
205 /* bitmask of which coprocessors are present */
206 extern const unsigned int Xthal_cp_mask;
208 /* read & write extra state register */
209 /*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/
210 /*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/
212 /* read & write a TIE coprocessor register */
213 /*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/
214 /*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/
216 /* return coprocessor number based on register */
217 /*extern int xthal_which_cp(unsigned reg);*/
220 /*----------------------------------------------------------------------
222 ----------------------------------------------------------------------*/
224 /* number of registers in register window */
225 extern const unsigned int Xthal_num_aregs;
226 extern const unsigned char Xthal_num_aregs_log2;
229 /*----------------------------------------------------------------------
231 ----------------------------------------------------------------------*/
233 /* size of the cache lines in log2(bytes) */
234 extern const unsigned char Xthal_icache_linewidth;
235 extern const unsigned char Xthal_dcache_linewidth;
236 /* size of the cache lines in bytes (2^linewidth) */
237 extern const unsigned short Xthal_icache_linesize;
238 extern const unsigned short Xthal_dcache_linesize;
240 /* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */
241 extern const unsigned int Xthal_icache_size;
242 extern const unsigned int Xthal_dcache_size;
244 extern const unsigned char Xthal_dcache_is_writeback;
246 /* invalidate the caches */
247 extern void xthal_icache_region_invalidate( void *addr, unsigned size );
248 extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
249 extern void xthal_icache_line_invalidate(void *addr);
250 extern void xthal_dcache_line_invalidate(void *addr);
251 /* write dirty data back */
252 extern void xthal_dcache_region_writeback( void *addr, unsigned size );
253 extern void xthal_dcache_line_writeback(void *addr);
254 /* write dirty data back and invalidate */
255 extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
256 extern void xthal_dcache_line_writeback_inv(void *addr);
258 /* sync icache and memory */
259 extern void xthal_icache_sync( void );
260 /* sync dcache and memory */
261 extern void xthal_dcache_sync( void );
264 /*----------------------------------------------------------------------
266 ----------------------------------------------------------------------*/
268 /* 1 if debug option configured, 0 if not: */
269 extern const int Xthal_debug_configured;
271 /* Set (plant) and remove software breakpoint, both synchronizing cache: */
272 extern unsigned int xthal_set_soft_break(void *addr);
273 extern void xthal_remove_soft_break(void *addr, unsigned int);
276 /*----------------------------------------------------------------------
278 ----------------------------------------------------------------------*/
280 /* Max expected size of the return buffer for a disassembled instruction (hint only): */
281 #define XTHAL_DISASM_BUFSIZE 80
283 /* Disassembly option bits for selecting what to return: */
284 #define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */
285 #define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */
286 #define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */
287 #define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */
288 #define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */
290 /* routine to get a string for the disassembled instruction */
291 extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,
292 char *buffer, unsigned buflen, unsigned options );
294 /* routine to get the size of the next instruction. Returns 0 for
295 illegal instruction */
296 extern int xthal_disassemble_size( unsigned char *instr_buf );
299 /*----------------------------------------------------------------------
300 Instruction/Data RAM/ROM Access
301 ----------------------------------------------------------------------*/
303 extern void* xthal_memcpy(void *dst, const void *src, unsigned len);
304 extern void* xthal_bcopy(const void *src, void *dst, unsigned len);
307 /*----------------------------------------------------------------------
309 ----------------------------------------------------------------------*/
311 extern int xthal_compare_and_set( int *addr, int test_val, int compare_val );
313 /*extern const char Xthal_have_s32c1i;*/
316 /*----------------------------------------------------------------------
318 ----------------------------------------------------------------------*/
320 extern const unsigned int Xthal_release_major;
321 extern const unsigned int Xthal_release_minor;
322 extern const char * const Xthal_release_name;
323 extern const char * const Xthal_release_internal;
325 extern const unsigned char Xthal_memory_order;
326 extern const unsigned char Xthal_have_windowed;
327 extern const unsigned char Xthal_have_density;
328 extern const unsigned char Xthal_have_booleans;
329 extern const unsigned char Xthal_have_loops;
330 extern const unsigned char Xthal_have_nsa;
331 extern const unsigned char Xthal_have_minmax;
332 extern const unsigned char Xthal_have_sext;
333 extern const unsigned char Xthal_have_clamps;
334 extern const unsigned char Xthal_have_mac16;
335 extern const unsigned char Xthal_have_mul16;
336 extern const unsigned char Xthal_have_fp;
337 extern const unsigned char Xthal_have_speculation;
338 extern const unsigned char Xthal_have_threadptr;
340 extern const unsigned char Xthal_have_pif;
341 extern const unsigned short Xthal_num_writebuffer_entries;
343 extern const unsigned int Xthal_build_unique_id;
344 /* Version info for hardware targeted by software upgrades: */
345 extern const unsigned int Xthal_hw_configid0;
346 extern const unsigned int Xthal_hw_configid1;
347 extern const unsigned int Xthal_hw_release_major;
348 extern const unsigned int Xthal_hw_release_minor;
349 extern const char * const Xthal_hw_release_name;
350 extern const char * const Xthal_hw_release_internal;
355 #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
361 /****************************************************************************
362 Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
363 ****************************************************************************/
366 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
368 /*----------------------------------------------------------------------
369 Constant Definitions (shared with assembly)
370 ----------------------------------------------------------------------*/
373 * Architectural limits, independent of configuration.
374 * Note that these are ISA-defined limits, not micro-architecture implementation
375 * limits enforced by the Xtensa Processor Generator (which may be stricter than
378 #define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */
379 #define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */
380 /* (as of T1040, implementation limit is 7: 0..6) */
381 #define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */
382 /* (as of T1040, implementation limit is 3: 0..2) */
384 /* Interrupt types: */
385 #define XTHAL_INTTYPE_UNCONFIGURED 0
386 #define XTHAL_INTTYPE_SOFTWARE 1
387 #define XTHAL_INTTYPE_EXTERN_EDGE 2
388 #define XTHAL_INTTYPE_EXTERN_LEVEL 3
389 #define XTHAL_INTTYPE_TIMER 4
390 #define XTHAL_INTTYPE_NMI 5
391 #define XTHAL_INTTYPE_WRITE_ERROR 6
392 #define XTHAL_MAX_INTTYPES 7 /* number of interrupt types */
395 #define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */
396 #define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */
398 /* Local Memory ECC/Parity: */
399 #define XTHAL_MEMEP_PARITY 1
400 #define XTHAL_MEMEP_ECC 2
401 /* Flags parameter to xthal_memep_inject_error(): */
402 #define XTHAL_MEMEP_F_LOCAL 0 /* local memory (default) */
403 #define XTHAL_MEMEP_F_DCACHE_DATA 4 /* data cache data */
404 #define XTHAL_MEMEP_F_DCACHE_TAG 5 /* data cache tag */
405 #define XTHAL_MEMEP_F_ICACHE_DATA 6 /* instruction cache data */
406 #define XTHAL_MEMEP_F_ICACHE_TAG 7 /* instruction cache tag */
407 #define XTHAL_MEMEP_F_CORRECTABLE 16 /* inject correctable error
408 (default is non-corr.) */
411 /* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */
412 #define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none
413 exception on any access (aka "illegal") */
414 #define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI)
415 [or H HC] way from tag match;
416 [or U UC] (ISA: same except Isolate case) */
417 #define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none
418 [or F FI fill] refill cache on miss, way from LRU
419 (ISA: Read/Write Miss Refill) */
420 #define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT
421 store immediately to memory (ISA: same) */
422 #define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none
423 use cache regardless of hit-vs-miss,
424 way from vaddr (ISA: use-cache-on-miss+hit) */
425 #define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G *
426 non-speculative; spec/replay refs not permitted */
428 #define XTHAL_AMB_COHERENT 6 /* 040 M MC ?ls: Mem/MP Coherent M
429 on read, other CPU/bus-master may need to supply data;
430 on write, maybe redirect to or flush other CPU dirty line; etc */
431 #define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G *
432 mem accesses cannot be out of order */
433 #define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none
434 allow combining/merging multiple writes
435 (to same datapath data unit) into one
436 (implied by writeback) */
437 #define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none
438 memory will not bus error (if it does,
439 handle as fatal imprecise interrupt) */
440 #define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none
441 on refill, read line+1 into prefetch buffers */
442 #define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none
443 access one of N stream buffers */
446 #define XTHAL_AM_EXCEPTION (1<<XTHAL_AMB_EXCEPTION)
447 #define XTHAL_AM_HITCACHE (1<<XTHAL_AMB_HITCACHE)
448 #define XTHAL_AM_ALLOCATE (1<<XTHAL_AMB_ALLOCATE)
449 #define XTHAL_AM_WRITETHRU (1<<XTHAL_AMB_WRITETHRU)
450 #define XTHAL_AM_ISOLATE (1<<XTHAL_AMB_ISOLATE)
451 #define XTHAL_AM_GUARD (1<<XTHAL_AMB_GUARD)
453 #define XTHAL_AM_ORDERED (1<<XTHAL_AMB_ORDERED)
454 #define XTHAL_AM_FUSEWRITES (1<<XTHAL_AMB_FUSEWRITES)
455 #define XTHAL_AM_COHERENT (1<<XTHAL_AMB_COHERENT)
456 #define XTHAL_AM_TRUSTED (1<<XTHAL_AMB_TRUSTED)
457 #define XTHAL_AM_PREFETCH (1<<XTHAL_AMB_PREFETCH)
458 #define XTHAL_AM_STREAM (1<<XTHAL_AMB_STREAM)
462 * Allowed Access Modes (bit combinations).
466 * Access mode bits (see XTHAL_AMB_xxx above).
467 * <letter> = bit is set
469 * '.' = bit is irrelevant / don't care, as follows:
470 * E=1 makes all others irrelevant
471 * W,F relevant only for stores
473 * Indicates which Xtensa releases support the corresponding
474 * access mode. Releases for each character column are:
475 * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1
476 * 3 = T1020.2 and later: T1020.2+, T1030
478 * 5 = T1050 (maybe), LX1, LX2, LX2.1
480 * And the character column contents are:
481 * <number> = support by release(s)
482 * "." = unsupported by release(s)
483 * "?" = support unknown
485 /* FOMGIWACE 23457 */
486 /* For instruction fetch: */
487 #define XTHAL_FAM_EXCEPTION 0x001 /* ........E 23457 exception */
488 #define XTHAL_FAM_ISOLATE 0x012 /* .---I.-C- ..... isolate */
489 #define XTHAL_FAM_BYPASS 0x000 /* .----.--- 23457 bypass */
490 #define XTHAL_FAM_NACACHED 0x002 /* .----.-C- ..... cached no-allocate (frozen) */
491 #define XTHAL_FAM_CACHED 0x006 /* .----.AC- 23457 cached */
493 #define XTHAL_LAM_EXCEPTION 0x001 /* ........E 23457 exception */
494 #define XTHAL_LAM_ISOLATE 0x012 /* .---I.-C- 23457 isolate */
495 #define XTHAL_LAM_BYPASS 0x000 /* .O---.--- 2.... bypass speculative */
496 #define XTHAL_LAM_BYPASSG 0x020 /* .O-G-.--- .3457 bypass guarded */
497 #define XTHAL_LAM_NACACHED 0x002 /* .O---.-C- 2.... cached no-allocate speculative */
498 #define XTHAL_LAM_NACACHEDG 0x022 /* .O-G-.-C- .3457 cached no-allocate guarded */
499 #define XTHAL_LAM_CACHED 0x006 /* .----.AC- 23457 cached speculative */
500 #define XTHAL_LAM_CACHEDG 0x026 /* .?-G-.AC- ..... cached guarded */
501 #define XTHAL_LAM_CACHEDM 0x046 /* .-M--.AC- ....7 cached MP-coherent (experimental) */
502 /* For data store: */
503 #define XTHAL_SAM_EXCEPTION 0x001 /* ........E 23457 exception */
504 #define XTHAL_SAM_ISOLATE 0x032 /* .--GI--C- 23457 isolate */
505 #define XTHAL_SAM_BYPASS 0x028 /* -O-G-W--- 23457 bypass */
506 /*efine XTHAL_SAM_BYPASSF 0x028*/ /* F--G-W--- ..... bypass write-combined */
507 #define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 23457 writethrough */
508 /*efine XTHAL_SAM_WRITETHRUF 0x02A*/ /* F--G-W-C- ..... writethrough write-combined */
509 #define XTHAL_SAM_WRITEALLOC 0x02E /* -O-G-WAC- ..... writethrough-allocate */
510 /*efine XTHAL_SAM_WRITEALLOCF 0x02E*/ /* F--G-WAC- ..... writethrough-allocate write-combined */
511 #define XTHAL_SAM_WRITEBACK 0x066 /* F-MG--AC- ...57 writeback (MP-coherent if configured) */
515 Cache attribute encoding for CACHEATTR (per ISA):
516 (Note: if this differs from ISA Ref Manual, ISA has precedence)
518 Inst-fetches Loads Stores
519 ------------- ------------ -------------
520 0x0 FCA_EXCEPTION ?LCA_NACACHED_G* SCA_WRITETHRU "uncached" (cached no-allocate)
521 0x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached
522 0x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass
523 0x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate
524 or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
525 0x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK write-back
526 or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
527 0x5..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved)
528 0xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate
529 0xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal
530 * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)
535 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
541 /*----------------------------------------------------------------------
543 ----------------------------------------------------------------------*/
545 /* This spill any live register windows (other than the caller's):
546 * (NOTE: current implementation require privileged code, but
547 * a user-callable implementation is possible.) */
548 extern void xthal_window_spill( void );
551 /*----------------------------------------------------------------------
552 Optional/Custom Processor State
553 ----------------------------------------------------------------------*/
555 /* validate & invalidate the TIE register file */
556 extern void xthal_validate_cp(int);
557 extern void xthal_invalidate_cp(int);
559 /* read and write cpenable register */
560 extern void xthal_set_cpenable(unsigned);
561 extern unsigned xthal_get_cpenable(void);
564 /*----------------------------------------------------------------------
566 ----------------------------------------------------------------------*/
568 /* the number of interrupt levels */
569 extern const unsigned char Xthal_num_intlevels;
570 /* the number of interrupts */
571 extern const unsigned char Xthal_num_interrupts;
573 /* mask for level of interrupts */
574 extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];
575 /* mask for level 0 to N interrupts */
576 extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];
578 /* level of each interrupt */
579 extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];
581 /* type per interrupt */
582 extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];
584 /* masks of each type of interrupt */
585 extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];
587 /* interrupt numbers assigned to each timer interrupt */
588 extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];
590 /* INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions: */
591 extern unsigned xthal_get_intenable( void );
592 extern void xthal_set_intenable( unsigned );
593 extern unsigned xthal_get_interrupt( void );
594 #define xthal_get_intread xthal_get_interrupt /* backward compatibility */
595 extern void xthal_set_intset( unsigned );
596 extern void xthal_set_intclear( unsigned );
599 /*----------------------------------------------------------------------
601 ----------------------------------------------------------------------*/
603 /* Number of instruction and data break registers: */
604 extern const int Xthal_num_ibreak;
605 extern const int Xthal_num_dbreak;
608 /*----------------------------------------------------------------------
610 ----------------------------------------------------------------------*/
613 extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */
614 extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */
616 /* get CCOUNT register (if not present return 0) */
617 extern unsigned xthal_get_ccount(void);
619 /* set and get CCOMPAREn registers (if not present, get returns 0) */
620 extern void xthal_set_ccompare(int, unsigned);
621 extern unsigned xthal_get_ccompare(int);
624 /*----------------------------------------------------------------------
626 ----------------------------------------------------------------------*/
628 extern const unsigned char Xthal_have_prid;
629 extern const unsigned char Xthal_have_exceptions;
630 extern const unsigned char Xthal_xea_version;
631 extern const unsigned char Xthal_have_interrupts;
632 extern const unsigned char Xthal_have_highlevel_interrupts;
633 extern const unsigned char Xthal_have_nmi;
635 extern unsigned xthal_get_prid( void );
638 /*----------------------------------------------------------------------
639 Virtual interrupt prioritization (DEPRECATED)
640 ----------------------------------------------------------------------*/
642 /* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */
643 extern unsigned xthal_vpri_to_intlevel(unsigned vpri);
644 extern unsigned xthal_intlevel_to_vpri(unsigned intlevel);
646 /* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */
647 extern unsigned xthal_int_enable(unsigned);
648 extern unsigned xthal_int_disable(unsigned);
650 /* Set/get virtual priority of an interrupt: */
651 extern int xthal_set_int_vpri(int intnum, int vpri);
652 extern int xthal_get_int_vpri(int intnum);
654 /* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */
655 extern void xthal_set_vpri_locklevel(unsigned intlevel);
656 extern unsigned xthal_get_vpri_locklevel(void);
658 /* Set/get current virtual interrupt priority: */
659 extern unsigned xthal_set_vpri(unsigned vpri);
660 extern unsigned xthal_get_vpri(void);
661 extern unsigned xthal_set_vpri_intlevel(unsigned intlevel);
662 extern unsigned xthal_set_vpri_lock(void);
665 /*----------------------------------------------------------------------
666 Generic Interrupt Trampolining Support (DEPRECATED)
667 ----------------------------------------------------------------------*/
669 typedef void (XtHalVoidFunc)(void);
671 /* Bitmask of interrupts currently trampolining down: */
672 extern unsigned Xthal_tram_pending;
675 * Bitmask of which interrupts currently trampolining down synchronously are
676 * actually enabled; this bitmask is necessary because INTENABLE cannot hold
677 * that state (sync-trampolining interrupts must be kept disabled while
678 * trampolining); in the current implementation, any bit set here is not set
679 * in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level
680 * one), its enable bit must be moved from here to INTENABLE:
682 extern unsigned Xthal_tram_enabled;
684 /* Bitmask of interrupts configured for sync trampolining: */
685 extern unsigned Xthal_tram_sync;
687 /* Trampoline support functions: */
688 extern unsigned xthal_tram_pending_to_service( void );
689 extern void xthal_tram_done( unsigned serviced_mask );
690 extern int xthal_tram_set_sync( int intnum, int sync );
691 extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );
694 /*----------------------------------------------------------------------
696 ----------------------------------------------------------------------*/
698 extern const unsigned char Xthal_num_instrom;
699 extern const unsigned char Xthal_num_instram;
700 extern const unsigned char Xthal_num_datarom;
701 extern const unsigned char Xthal_num_dataram;
702 extern const unsigned char Xthal_num_xlmi;
704 /* Each of the following arrays contains at least one entry,
705 * or as many entries as needed if more than one: */
706 extern const unsigned int Xthal_instrom_vaddr[];
707 extern const unsigned int Xthal_instrom_paddr[];
708 extern const unsigned int Xthal_instrom_size [];
709 extern const unsigned int Xthal_instram_vaddr[];
710 extern const unsigned int Xthal_instram_paddr[];
711 extern const unsigned int Xthal_instram_size [];
712 extern const unsigned int Xthal_datarom_vaddr[];
713 extern const unsigned int Xthal_datarom_paddr[];
714 extern const unsigned int Xthal_datarom_size [];
715 extern const unsigned int Xthal_dataram_vaddr[];
716 extern const unsigned int Xthal_dataram_paddr[];
717 extern const unsigned int Xthal_dataram_size [];
718 extern const unsigned int Xthal_xlmi_vaddr[];
719 extern const unsigned int Xthal_xlmi_paddr[];
720 extern const unsigned int Xthal_xlmi_size [];
723 /*----------------------------------------------------------------------
725 ----------------------------------------------------------------------*/
727 /* number of cache sets in log2(lines per way) */
728 extern const unsigned char Xthal_icache_setwidth;
729 extern const unsigned char Xthal_dcache_setwidth;
730 /* cache set associativity (number of ways) */
731 extern const unsigned int Xthal_icache_ways;
732 extern const unsigned int Xthal_dcache_ways;
734 extern const unsigned char Xthal_icache_line_lockable;
735 extern const unsigned char Xthal_dcache_line_lockable;
737 /* cache attribute register control (used by other HAL routines) */
738 extern unsigned xthal_get_cacheattr( void );
739 extern unsigned xthal_get_icacheattr( void );
740 extern unsigned xthal_get_dcacheattr( void );
741 extern void xthal_set_cacheattr( unsigned );
742 extern void xthal_set_icacheattr( unsigned );
743 extern void xthal_set_dcacheattr( unsigned );
744 /* set cache attribute (access modes) for a range of memory */
745 extern int xthal_set_region_attribute( void *addr, unsigned size,
746 unsigned cattr, unsigned flags );
747 /* Bits of flags parameter to xthal_set_region_attribute(): */
748 #define XTHAL_CAFLAG_EXPAND 0x000100 /* only expand allowed access to range, don't reduce it */
749 #define XTHAL_CAFLAG_EXACT 0x000200 /* return error if can't apply change to exact range specified */
750 #define XTHAL_CAFLAG_NO_PARTIAL 0x000400 /* don't apply change to regions partially covered by range */
751 #define XTHAL_CAFLAG_NO_AUTO_WB 0x000800 /* don't writeback data after leaving writeback attribute */
752 #define XTHAL_CAFLAG_NO_AUTO_INV 0x001000 /* don't invalidate after disabling cache (entering bypass) */
755 extern void xthal_icache_enable( void ); /* DEPRECATED */
756 extern void xthal_dcache_enable( void ); /* DEPRECATED */
758 extern void xthal_icache_disable( void ); /* DEPRECATED */
759 extern void xthal_dcache_disable( void ); /* DEPRECATED */
761 /* invalidate the caches */
762 extern void xthal_icache_all_invalidate( void );
763 extern void xthal_dcache_all_invalidate( void );
764 /* write dirty data back */
765 extern void xthal_dcache_all_writeback( void );
766 /* write dirty data back and invalidate */
767 extern void xthal_dcache_all_writeback_inv( void );
768 /* prefetch and lock specified memory range into cache */
769 extern void xthal_icache_region_lock( void *addr, unsigned size );
770 extern void xthal_dcache_region_lock( void *addr, unsigned size );
771 extern void xthal_icache_line_lock(void *addr);
772 extern void xthal_dcache_line_lock(void *addr);
773 /* unlock from cache */
774 extern void xthal_icache_all_unlock( void );
775 extern void xthal_dcache_all_unlock( void );
776 extern void xthal_icache_region_unlock( void *addr, unsigned size );
777 extern void xthal_dcache_region_unlock( void *addr, unsigned size );
778 extern void xthal_icache_line_unlock(void *addr);
779 extern void xthal_dcache_line_unlock(void *addr);
783 /*----------------------------------------------------------------------
784 Local Memory ECC/Parity
785 ----------------------------------------------------------------------*/
787 /* Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx: */
788 extern void xthal_memep_inject_error(void *addr, int size, int flags);
792 /*----------------------------------------------------------------------
793 Memory Management Unit
794 ----------------------------------------------------------------------*/
796 extern const unsigned char Xthal_have_spanning_way;
797 extern const unsigned char Xthal_have_identity_map;
798 extern const unsigned char Xthal_have_mimic_cacheattr;
799 extern const unsigned char Xthal_have_xlt_cacheattr;
800 extern const unsigned char Xthal_have_cacheattr;
801 extern const unsigned char Xthal_have_tlbs;
803 extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */
804 extern const unsigned char Xthal_mmu_asid_kernel;
805 extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
806 extern const unsigned char Xthal_mmu_ring_bits;
807 extern const unsigned char Xthal_mmu_sr_bits;
808 extern const unsigned char Xthal_mmu_ca_bits;
809 extern const unsigned int Xthal_mmu_max_pte_page_size;
810 extern const unsigned int Xthal_mmu_min_pte_page_size;
812 extern const unsigned char Xthal_itlb_way_bits;
813 extern const unsigned char Xthal_itlb_ways;
814 extern const unsigned char Xthal_itlb_arf_ways;
815 extern const unsigned char Xthal_dtlb_way_bits;
816 extern const unsigned char Xthal_dtlb_ways;
817 extern const unsigned char Xthal_dtlb_arf_ways;
819 /* Convert between virtual and physical addresses (through static maps only): */
820 /*** WARNING: these two functions may go away in a future release; don't depend on them! ***/
821 extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
822 extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
828 #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
830 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
835 /****************************************************************************
836 EXPERIMENTAL and DEPRECATED Definitions
837 ****************************************************************************/
840 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
845 #ifdef INCLUDE_DEPRECATED_HAL_CODE
846 extern const unsigned char Xthal_have_old_exc_arch;
847 extern const unsigned char Xthal_have_mmu;
848 extern const unsigned int Xthal_num_regs;
849 extern const unsigned char Xthal_num_iroms;
850 extern const unsigned char Xthal_num_irams;
851 extern const unsigned char Xthal_num_droms;
852 extern const unsigned char Xthal_num_drams;
853 extern const unsigned int Xthal_configid0;
854 extern const unsigned int Xthal_configid1;
857 #ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
858 #define XTHAL_24_BIT_BREAK 0x80000000
859 #define XTHAL_16_BIT_BREAK 0x40000000
860 extern const unsigned short Xthal_ill_inst_16[16];
861 #define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */
862 #define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */
863 #define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */
864 #define XTHAL_RFW_INST 0x00000800
865 #define XTHAL_RFUE_INST 0x00000400
866 #define XTHAL_RFI_INST 0x00000200
867 #define XTHAL_RFE_INST 0x00000100
868 #define XTHAL_RET_INST 0x00000080
869 #define XTHAL_BREAK_INST 0x00000040
870 #define XTHAL_SYSCALL_INST 0x00000020
871 #define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */
872 #define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */
873 #define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */
874 #define XTHAL_24_BIT_INST 0x00000002
875 #define XTHAL_16_BIT_INST 0x00000001
876 typedef struct xthal_state {
883 unsigned cpregs_ptr[XTHAL_MAX_CPS];
885 extern unsigned int xthal_inst_type(void *addr);
886 extern unsigned int xthal_branch_addr(void *addr);
887 extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);
888 #endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
893 #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
895 #endif /*XTENSA_HAL_H*/