2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 /*************************************************************************/
36 /* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */
38 /* Module Name : reg_defs.h */
41 /* This file contains the register addr and marco definition. */
46 /*************************************************************************/
52 #define BIT_SET(bit) (1<<bit)
53 #define BIT_CLR(bit) (0<<bit)
55 /***** REGISTER BASE ADDRESS DEFINITION *****/
56 #define RESET_VECTOR_ADDRESS 0x8e0000
57 /********************************************/
59 /***** REGISTER BASE ADDRESS DEFINITION *****/
60 #define USB_CTRL_BASE_ADDRESS 0x00010000
61 #define RST_BASE_ADDRESS 0x00050000
62 #define UART_BASE_ADDRESS 0x00051000
63 #define HOST_DMA_BASE_ADDRESS 0x00053000
64 #define USB_DMA_BASE_ADDRESS 0x00055000
65 #define SPI_REG_BASE_ADDRESS 0x0005B000
66 #define WLAN_BASE_ADDRESS 0x10000000
67 #define MAC_REG_BASE_ADDRESS WLAN_BASE_ADDRESS
68 /*******************************************************************************/
70 #define MAGPEI_REG_RST_BASE_ADDR RST_BASE_ADDRESS
72 #define REG_GENERAL_TIMER_OFFSET 0x0
73 #define REG_GENERAL_TIMER_RELOAD_OFFSET 0x4
74 #define REG_WATCHDOG_TIMER_CONTROL_OFFSET 0x8
75 #define REG_WATCHDOG_TIMER_OFFSET 0xC
76 #define REG_RESET_OFFSET 0x10
77 #define REG_BOOTSTRAP 0x14
78 #define REG_AHB_ARB 0x18
79 #define REG_WATCHDOG_INTR_OFFSET 0x1C
80 #define REG_GENERAL_TIMER_INTR_OFFSET 0x20
81 #define REG_REVISION_ID 0x90
82 #define REG_CLOCK_CONTROL_OFFSET 0x40
83 #define REG_RST_PWDN_CONTROL_OFFSET 0x44
84 #define REG_USB_PLL_OFFSET 0x48
85 #define REG_RST_STATUS_OFFSET 0x4C
88 #define MAGPEI_REG_RST_GENERAL_TIMER_ADDR (RST_BASE_ADDRESS+REG_GENERAL_TIMER_OFFSET)
89 #define MAGPIE_REG_RST_GENERAL_TIMER_RLD_ADDR (RST_BASE_ADDRESS+REG_GENERAL_TIMER_RELOAD_OFFSET)
90 #define MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR (RST_BASE_ADDRESS+REG_WATCHDOG_TIMER_CONTROL_OFFSET)
91 #define MAGPIE_REG_RST_WDT_TIMER_ADDR (RST_BASE_ADDRESS+REG_WATCHDOG_TIMER_OFFSET)
92 #define MAGPIE_REG_RST_RESET_ADDR (RST_BASE_ADDRESS+REG_RESET_OFFSET)
93 #define MAGPIE_REG_RST_BOOTSTRAP_ADDR (RST_BASE_ADDRESS+REG_BOOTSTRAP)
94 #define MAGPIE_REG_AHB_ARB_ADDR (RST_BASE_ADDRESS+REG_AHB_ARB)
95 #define MAGPIE_REG_RST_WDT_INTR_ADDR (RST_BASE_ADDRESS+REG_WATCHDOG_INTR_OFFSET)
96 #define MAGPIE_REG_RST_GENERAL_TIMER_INTR_ADDR (RST_BASE_ADDRESS+REG_GENERAL_TIMER_INTR_OFFSET)
97 #define MAGPIE_REG_REVISION_ID_ADDR (RST_BASE_ADDRESS+REG_REVISION_ID)
98 #define MAGPIE_REG_CLOCK_CTRL_ADDR (RST_BASE_ADDRESS+REG_CLOCK_CONTROL_OFFSET)
99 #define MAGPIE_REG_RST_PWDN_CTRL_ADDR (RST_BASE_ADDRESS+REG_RST_PWDN_CONTROL_OFFSET)
100 #define MAGPIE_REG_USB_PLL_ADDR (RST_BASE_ADDRESS+REG_USB_PLL_OFFSET)
101 #define MAGPIE_REG_RST_STATUS_ADDR (RST_BASE_ADDRESS+REG_RST_STATUS_OFFSET)
103 #define MAGPEI_REG_RST_GENERAL_TIMER (*((volatile u32_t*)(MAGPEI_REG_RST_GENERAL_TIMER_ADDR)))
104 #define MAGPIE_REG_RST_GENERAL_TIMER_RLD (*((volatile u32_t*)(MAGPIE_REG_RST_GENERAL_TIMER_RLD_ADDR)))
105 #define MAGPIE_REG_RST_WDT_TIMER_CTRL (*((volatile u32_t*)(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR)))
106 #define MAGPIE_REG_RST_WDT_TIMER (*((volatile u32_t*)(MAGPIE_REG_RST_WDT_TIMER_ADDR)))
107 #define MAGPIE_REG_RST_RESET (*((volatile u32_t*)(MAGPIE_REG_RST_RESET_ADDR)))
108 #define MAGPIE_REG_RST_BOOTSTRAP (*((volatile u32_t*)(MAGPIE_REG_RST_BOOTSTRAP_ADDR)))
109 #define MAGPIE_REG_AHB_ARB (*((volatile u32_t*)(MAGPIE_REG_AHB_ARB_ADDR)))
110 #define MAGPIE_REG_REVISION_ID (*((volatile u32_t*)(MAGPIE_REG_REVISION_ID_ADDR)))
111 #define MAGPIE_REG_CLOCK_CTRL (*((volatile u32_t*)(MAGPIE_REG_CLOCK_CTRL_ADDR)))
112 #define MAGPIE_REG_RST_PWDN_CTRL (*((volatile u32_t*)(MAGPIE_REG_RST_PWDN_CTRL_ADDR)))
113 #define MAGPIE_REG_USB_PLL (*((volatile u32_t*)(MAGPIE_REG_USB_PLL_ADDR)))
114 #define MAGPIE_REG_RST_STATUS (*((volatile u32_t*)(MAGPIE_REG_RST_STATUS_ADDR)))
117 /*******************************************************************************/
118 /* USB DMA Register*/
120 #define MAGPIE_REG_USB_INTERRUPT_ADDR USB_DMA_BASE_ADDRESS
121 #define MAGPIE_REG_USB_INTERRUPT_MASK_ADDR (USB_DMA_BASE_ADDRESS + 0x4)
123 #define MAGPIE_REG_USB_RX0_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0x800)
124 #define MAGPIE_REG_USB_RX0_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0x804)
125 #define MAGPIE_REG_USB_RX0_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0x808)
126 #define MAGPIE_REG_USB_RX0_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0x814)
127 #define MAGPIE_REG_USB_RX0_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0x818)
128 #define MAGPIE_REG_USB_RX0_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0x81C)
130 #define MAGPIE_REG_USB_RX1_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0x900)
131 #define MAGPIE_REG_USB_RX1_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0x904)
132 #define MAGPIE_REG_USB_RX1_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0x908)
133 #define MAGPIE_REG_USB_RX1_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0x914)
134 #define MAGPIE_REG_USB_RX1_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0x918)
135 #define MAGPIE_REG_USB_RX1_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0x91C)
137 #define MAGPIE_REG_USB_RX2_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0xa00)
138 #define MAGPIE_REG_USB_RX2_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0xa04)
139 #define MAGPIE_REG_USB_RX2_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0xa08)
140 #define MAGPIE_REG_USB_RX2_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0xa14)
141 #define MAGPIE_REG_USB_RX2_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0xa18)
142 #define MAGPIE_REG_USB_RX2_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0xa1C)
144 #define MAGPIE_REG_USB_TX0_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0xC00)
145 #define MAGPIE_REG_USB_TX0_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0xC04)
146 #define MAGPIE_REG_USB_TX0_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0xC08)
147 #define MAGPIE_REG_USB_TX0_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0xC10)
148 #define MAGPIE_REG_USB_TX0_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0xC14)
149 #define MAGPIE_REG_USB_TX0_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0xC18)
151 #define MAGPIE_REG_USB_INTERRUPT_TX0_END (1<<24) //0x1000000
152 #define MAGPIE_REG_USB_INTERRUPT_TX0_COMPL (1<<16) //0x10000
153 #define MAGPIE_REG_USB_INTERRUPT_RX2_END (1<<10) //0x00400
154 #define MAGPIE_REG_USB_INTERRUPT_RX1_END (1<<9) //0x00200
155 #define MAGPIE_REG_USB_INTERRUPT_RX0_END (1<<8) //0x0100
156 #define MAGPIE_REG_USB_INTERRUPT_RX2_COMPL (1<<2) //0x00004
158 #define MAGPIE_REG_USB_INTERRUPT_RX1_COMPL (1<<1) //0x00002
159 #define MAGPIE_REG_USB_INTERRUPT_RX0_COMPL (1<<0) //0x00001
162 #define MAGPIE_REG_USB_INTERRUPT (*((volatile u32_t*)(MAGPIE_REG_USB_INTERRUPT_ADDR)))
163 #define MAGPIE_REG_USB_INTERRUPT_MASK (*((volatile u32_t*)(MAGPIE_REG_USB_INTERRUPT_MASK_ADDR)))
165 #define MAGPIE_REG_USB_RX0_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_DESC_START_ADDR)))
166 #define MAGPIE_REG_USB_RX0_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_DMA_START_ADDR)))
167 #define MAGPIE_REG_USB_RX0_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_BURST_SIZE_ADDR)))
168 #define MAGPIE_REG_USB_RX0_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_STATE_ADDR)))
169 #define MAGPIE_REG_USB_RX0_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_CUR_TRACE_ADDR)))
170 #define MAGPIE_REG_USB_RX0_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_SWAP_DATA_ADDR)))
173 #define MAGPIE_REG_USB_RX1_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_DESC_START_ADDR)))
174 #define MAGPIE_REG_USB_RX1_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_DMA_START_ADDR)))
175 #define MAGPIE_REG_USB_RX1_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_BURST_SIZE_ADDR)))
176 #define MAGPIE_REG_USB_RX1_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_STATE_ADDR)))
177 #define MAGPIE_REG_USB_RX1_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_CUR_TRACE_ADDR)))
178 #define MAGPIE_REG_USB_RX1_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_SWAP_DATA_ADDR)))
180 #define MAGPIE_REG_USB_RX2_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_DESC_START_ADDR)))
181 #define MAGPIE_REG_USB_RX2_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_DMA_START_ADDR)))
182 #define MAGPIE_REG_USB_RX2_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_BURST_SIZE_ADDR)))
183 #define MAGPIE_REG_USB_RX2_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_STATE_ADDR)))
184 #define MAGPIE_REG_USB_RX2_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_CUR_TRACE_ADDR)))
185 #define MAGPIE_REG_USB_RX2_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_SWAP_DATA_ADDR)))
188 #define MAGPIE_REG_USB_TX0_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_DESC_START_ADDR)))
189 #define MAGPIE_REG_USB_TX0_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_DMA_START_ADDR)))
190 #define MAGPIE_REG_USB_TX0_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_BURST_SIZE_ADDR)))
191 #define MAGPIE_REG_USB_TX0_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_STATE_ADDR)))
192 #define MAGPIE_REG_USB_TX0_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_CUR_TRACE_ADDR)))
193 #define MAGPIE_REG_USB_TX0_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_SWAP_DATA_ADDR)))
195 /*******************************************************************************/
196 /***************************/
197 #define MAGPIE_REG_SPI_BASE_ADDR SPI_REG_BASE_ADDRESS
199 #define REG_SPI_CS_OFFSET 0x0
200 #define REG_SPI_AO_OFFSET 0x4
201 #define REG_SPI_D_OFFSET 0x8
202 #define REG_SPI_CLKDIV_OFFSET 0x1C
205 #define MAGPIE_REG_SPI_CS_ADDR (SPI_REG_BASE_ADDRESS + REG_SPI_CS_OFFSET)
206 #define MAGPIE_REG_SPI_AO_ADDR (SPI_REG_BASE_ADDRESS + REG_SPI_AO_OFFSET)
207 #define MAGPIE_REG_SPI_D_ADDR (SPI_REG_BASE_ADDRESS + REG_SPI_D_OFFSET)
208 #define MAGPIE_REG_SPI_CLKDIV_ADDR (SPI_REG_BASE_ADDRESS + REG_SPI_CLKDIV_OFFSET)
210 /*******************************************************************************/
211 #define K2_REG_MAC_BASE_ADDR MAC_REG_BASE_ADDRESS
213 #define REG_PLL_CONTROL_OFFSET 0x7014
214 #define REG_RTC_FORCE_OFFSET 0x7040
215 #define REG_RTC_STATUS_OFFSET 0x7044
217 #define K2_REG_PLL_CONTROL_ADDR (MAC_REG_BASE_ADDRESS + REG_PLL_CONTROL_OFFSET)
218 #define K2_REG_RTC_FORCE_ADDR (MAC_REG_BASE_ADDRESS + REG_RTC_FORCE_OFFSET)
219 #define K2_REG_RTC_STATUS_ADDR (MAC_REG_BASE_ADDRESS + REG_RTC_STATUS_OFFSET)