2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #ifndef __AR6K_SOC_H__
36 #define __AR6K_SOC_H__
38 //#include "hw/apb_map.h"
39 //#include "hw/rtc_reg.h"
40 //#include "hw/mbox_reg.h"
43 * Basic types, appropriate for both
44 * the 32-bit MIPS core on AR6000 and
45 * the 32-bit XTensa core on AR6002
47 typedef signed char A_CHAR;
48 typedef signed char A_INT8;
49 typedef unsigned char A_UINT8;
50 typedef unsigned char A_UCHAR;
51 typedef short A_INT16;
52 typedef unsigned short A_UINT16;
54 typedef unsigned int A_UINT32;
55 typedef long long A_INT64;
56 typedef unsigned long long A_UINT64;
58 typedef unsigned int ULONG;
59 typedef ULONG A_ULONG;
60 typedef A_ULONG A_ADDR;
63 //#include "targaddrs.h"
66 * Some platform-specific macros and constants that may needed
71 * AR6001/MIPS uses a cache line size of 16 Bytes.
72 * AR6002/Xtensa has no caches; but existing code assumes
73 * that this constant is non-zero. To avoid code complexity
74 * and possibly subtle bugs we define a bogus cache
75 * line size for Xtensa that matches MIPs'.
77 #define A_CACHE_LINE_SIZE 16
80 #define A_MIPS_KSEG_UNCACHED 0xa0000000
81 #define A_MIPS_KSEG_CACHED 0x80000000
82 #define A_MIPS_KSEG_MASK 0xe0000000
85 * Convert a cached virtual address or a CPU physical address into
86 * an uncached virtual address.
88 #define A_UNCACHED_ADDR(addr) \
89 ((void *)(((A_UINT32)(addr)) | A_MIPS_KSEG_UNCACHED))
92 * Convert an uncached or CPU physical address into
93 * a cached virtual address.
95 #define A_CACHED_ADDR(addr) \
96 ((void *)((((A_UINT32)(addr)) & ~A_MIPS_KSEG_MASK) | A_MIPS_KSEG_CACHED))
98 /* Read/Write a 32-bit AR6000 SOC register, specified by its physical address */
99 #define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)A_UNCACHED_ADDR(addr)))
101 #define A_SOC_ADDR_WRITE(addr, val) \
103 (*((volatile A_UINT32 *)A_UNCACHED_ADDR(addr))) = (A_UINT32)(val); \
106 #define A_RTC_REG_READ(addr) A_SOC_ADDR_READ(addr)
107 #define A_MC_REG_READ(addr) A_SOC_ADDR_READ(addr)
108 #define A_UART_REG_READ(addr) A_SOC_ADDR_READ(addr)
109 #define A_SI_REG_READ(addr) A_SOC_ADDR_READ(addr)
110 #define A_GPIO_REG_READ(addr) A_SOC_ADDR_READ(addr)
111 #define A_MBOX_REG_READ(addr) A_SOC_ADDR_READ(addr)
112 #define A_WMAC_REG_READ(addr) A_SOC_ADDR_READ(addr)
113 #define A_ANALOG_REG_READ(addr) A_SOC_ADDR_READ(addr)
115 #define A_RTC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
116 #define A_MC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
117 #define A_UART_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
118 #define A_SI_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
119 #define A_GPIO_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
120 #define A_MBOX_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
121 #define A_WMAC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
122 #define A_ANALOG_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val))
126 #define A_UNCACHED_ADDR(addr) (addr)
127 #define A_CACHED_ADDR(addr) (addr)
129 #define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)(addr)))
131 #define A_SOC_ADDR_WRITE(addr, val) \
133 (*((volatile A_UINT32 *)(addr))) = (A_UINT32)(val); \
136 #define A_RTC_REG_READ(addr) A_SOC_ADDR_READ(RTC_BASE_ADDRESS|(A_UINT32)(addr))
137 #define A_MC_REG_READ(addr) A_SOC_ADDR_READ(VMC_BASE_ADDRESS|(A_UINT32)(addr))
138 #define A_UART_REG_READ(addr) A_SOC_ADDR_READ(UART_BASE_ADDRESS|(A_UINT32)(addr))
139 #define A_SI_REG_READ(addr) A_SOC_ADDR_READ(SI_BASE_ADDRESS|(A_UINT32)(addr))
140 #define A_GPIO_REG_READ(addr) A_SOC_ADDR_READ(GPIO_BASE_ADDRESS|(A_UINT32)(addr))
141 #define A_MBOX_REG_READ(addr) A_SOC_ADDR_READ(MBOX_BASE_ADDRESS|(A_UINT32)(addr))
142 #define A_WMAC_REG_READ(addr) A_SOC_ADDR_READ(MAC_BASE_ADDRESS|(A_UINT32)(addr))
143 #define A_ANALOG_REG_READ(addr) A_SOC_ADDR_READ(ANALOG_INTF_BASE_ADDRESS|(A_UINT32)(addr))
145 #define A_RTC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(RTC_BASE_ADDRESS|(A_UINT32)(addr), (val))
146 #define A_MC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(VMC_BASE_ADDRESS|(A_UINT32)(addr), (val))
147 #define A_UART_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(UART_BASE_ADDRESS|(A_UINT32)(addr), (val))
148 #define A_SI_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(SI_BASE_ADDRESS|(A_UINT32)(addr), (val))
149 #define A_GPIO_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(GPIO_BASE_ADDRESS|(A_UINT32)(addr), (val))
150 #define A_MBOX_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(MBOX_BASE_ADDRESS|(A_UINT32)(addr), (val))
151 #define A_WMAC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(MAC_BASE_ADDRESS|(A_UINT32)(addr), (val))
152 #define A_ANALOG_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(ANALOG_INTF_BASE_ADDRESS|(A_UINT32)(addr), (val))
157 * Sleep/stay awake control.
158 * It is the caller's responsibility to guarantee atomicity.
161 typedef A_UINT32 A_old_sleep_t;
163 #define A_SYSTEM_SLEEP_DISABLE(pOldSystemSleep) \
165 *(pOldSystemSleep) = A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); \
166 A_RTC_REG_WRITE(SYSTEM_SLEEP_ADDRESS, \
167 *(pOldSystemSleep) | SYSTEM_SLEEP_DISABLE_MASK); \
168 (void)A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); /* flush */ \
171 #define A_SYSTEM_SLEEP_RESTORE(OldSystemSleep) \
173 A_RTC_REG_WRITE(SYSTEM_SLEEP_ADDRESS, (OldSystemSleep)); \
174 (void)A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); /* flush */ \
179 * AR6K-specific High Frequency Timestamp support.
180 * This is intended for use as a performance tool, and
181 * is not to be used in normal operation.
184 A_UINT32 highfreq; /* ~40MHz resolution */
185 A_UINT32 lowfreq; /* ~32KHz resolution */
189 * Enable HighFrequency timer.
190 * Normally, we keep this OFF in order to save power.
192 #define HF_TIMER_CONTROL_START_MASK HF_TIMER_CONTROL_ON_MASK
193 #define A_TIMESTAMP_ENABLE() \
195 A_RTC_REG_WRITE(HF_TIMER_ADDRESS, (40000000/32768)<<12); \
196 A_RTC_REG_WRITE(HF_TIMER_CONTROL_ADDRESS, \
197 HF_TIMER_CONTROL_START_MASK | \
198 HF_TIMER_CONTROL_AUTO_RESTART_MASK | \
199 HF_TIMER_CONTROL_RESET_MASK); \
203 * Turn it OFF when you're done:
205 #define A_TIMESTAMP_DISABLE() A_RTC_REG_WRITE(HF_TIMER_CONTROL_ADDRESS, 0)
208 * Get a timestamp. It's the caller's responsibility to
209 * guarantee atomicity of the two reads, if needed.
211 #define A_TIMESTAMP(pTimestamp) \
213 (pTimestamp)->highfreq = A_RTC_REG_READ(HF_TIMER_COUNT_ADDRESS); \
214 (pTimestamp)->lowfreq = A_RTC_REG_READ(HF_LF_COUNT_ADDRESS); \
218 * Supported reference clock speeds.
220 * Note: MAC HAL code has multiple tables indexed by these values,
221 * so do not rearrange them. Add any new refclk values at the end.
224 AR6K_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */
225 AR6K_REFCLK_19_2_MHZ = 0,
226 AR6K_REFCLK_26_MHZ = 1,
227 AR6K_REFCLK_40_MHZ = 2,
228 AR6K_REFCLK_52_MHZ = 3,
229 AR6K_REFCLK_38_4_MHZ = 4,
230 AR6K_REFCLK_24_MHZ = 5,
233 #define A_REFCLK_UNKNOWN AR6K_REFCLK_UNKNOWN
234 #define A_REFCLK_19_2_MHZ AR6K_REFCLK_19_2_MHZ
235 #define A_REFCLK_26_MHZ AR6K_REFCLK_26_MHZ
236 #define A_REFCLK_40_MHZ AR6K_REFCLK_40_MHZ
237 #define A_REFCLK_52_MHZ AR6K_REFCLK_52_MHZ
238 #define A_REFCLK_38_4_MHZ AR6K_REFCLK_38_4_MHZ
239 #define A_REFCLK_24_MHZ AR6K_REFCLK_24_MHZ
241 /* System defaults to 2.4GHz settings */
242 #define A_BAND_DEFAULT A_BAND_24GHZ
245 #define FLASH_ADDR(n) AR6000_FLASH_ADDR(n)
249 #define HOST_INTEREST ((struct host_interest_s *)AR6002_HOST_INTEREST_ADDRESS)
251 #define HOST_INTEREST ((struct host_interest_s *)AR6001_HOST_INTEREST_ADDRESS)
254 #define AR6K_OPTION_TEST(option) \
255 (A_MBOX_REG_READ(LOCAL_SCRATCH_ADDRESS) & (option))
259 #endif /* __AR6K_SOC_H__ */