2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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6 * modification, are permitted (subject to the limitations in the
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17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
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22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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35 #include <adf_os_stdtypes.h>
36 #include <adf_os_types.h>
38 //#include <HIF_api.h>
39 #include <cmnos_api.h>
41 #include <Magpie_api.h>
43 #include <adf_os_util.h>
44 #include <adf_os_mem.h>
45 #include <adf_os_time.h>
51 /**************************Constants******************************/
53 GMAC_HST_QUERY = 0x0001,
54 GMAC_HST_REPLY = 0x0002,
55 GMAC_TGT_QUERY = 0x0003,
56 GMAC_TGT_REPLY = 0x0004
60 MAG_REG_GPIO_OE = 0x00052000,/*GPIO Output Enable*/
61 MAG_REG_RST = 0x00050010,/*Magpie reset reg*/
62 MAG_REG_RST_AHB = 0x00050018,/*Magpie AHB_ARB reset reg*/
63 MAG_REG_MII0_CTRL = 0x00054100,/*Magpie MII0 Control reg*/
64 MAG_REG_STAT_CTRL = 0x00054104,/*Magpie Status reg*/
65 MAG_REG_MDIO = 0x00054200,/*Mapie MDIO register*/
66 MAG_REG_MDIO_CMD = 0x00 + MAG_REG_MDIO,/*CMD register (0)*/
67 MAG_REG_MDIO_OWN = 0x02 + MAG_REG_MDIO,/*OWN register (1)*/
69 * XXX: Endianess inside the word & between words
71 MAG_REG_MDIO_ADDR0 = 0x04 + MAG_REG_MDIO,/*ADDR0 register (2)*/
72 MAG_REG_MDIO_ADDR1 = 0x06 + MAG_REG_MDIO,/*ADDR1 register (3)*/
73 MAG_REG_MDIO_WRITE0 = 0x08 + MAG_REG_MDIO,/*Data WRITE0 register (4)*/
74 MAG_REG_MDIO_WRITE1 = 0x0a + MAG_REG_MDIO,/*Data WRITE1 register (5)*/
75 MAG_REG_MDIO_READ0 = 0x0c + MAG_REG_MDIO,/*Data READ0 register (6)*/
76 MAG_REG_MDIO_READ1 = 0x0e + MAG_REG_MDIO,/*Data READ1 register (7)*/
80 GMAC_REG_BASE = 0x00060000,
81 GMAC_REG_MAC_CFG1 = 0x00 + GMAC_REG_BASE,/*MAC config 1*/
82 GMAC_REG_MAC_CFG2 = 0x04 + GMAC_REG_BASE,/*MAC config 2*/
83 GMAC_REG_IPG_IFG = 0x08 + GMAC_REG_BASE,/*Inter-packet-gap*/
84 GMAC_REG_HALF_DPLX = 0x0c + GMAC_REG_BASE,/*Half duplex*/
85 GMAC_REG_MAX_FRAME = 0x10 + GMAC_REG_BASE,/*Max frame length*/
86 GMAC_REG_MII_CFG = 0x20 + GMAC_REG_BASE,/*MII mgmt config*/
87 GMAC_REG_MII_CMD = 0x24 + GMAC_REG_BASE,/*MII mgmt command*/
88 GMAC_REG_MII_ADDR = 0x28 + GMAC_REG_BASE,/*MII mgmt address*/
89 GMAC_REG_MII_CTRL = 0x2c + GMAC_REG_BASE,/*MII mgmt control*/
90 GMAC_REG_MII_STAT = 0x30 + GMAC_REG_BASE,/*MII mgmt status*/
91 GMAC_REG_MII_PSTAT = 0x34 + GMAC_REG_BASE,/*MII mgmt Phy status/ind*/
92 GMAC_REG_IF_CTRL = 0x38 + GMAC_REG_BASE,/*Interface control*/
93 GMAC_REG_IF_STAT = 0x3c + GMAC_REG_BASE,/*Interface status*/
94 GMAC_REG_MAC_ADDR1 = 0x40 + GMAC_REG_BASE,/*MAC address 1*/
95 GMAC_REG_MAC_ADDR2 = 0x44 + GMAC_REG_BASE,/*MAC address 2*/
96 GMAC_REG_FIFO_CFG0 = 0x48 + GMAC_REG_BASE,/*FIFO config reg0*/
97 GMAC_REG_FIFO_CFG1 = 0x4c + GMAC_REG_BASE,/*FIFO config reg1*/
98 GMAC_REG_FIFO_CFG2 = 0x50 + GMAC_REG_BASE,/*FIFO config reg2*/
99 GMAC_REG_FIFO_CFG3 = 0x54 + GMAC_REG_BASE,/*FIFO config reg3*/
100 GMAC_REG_FIFO_CFG4 = 0x58 + GMAC_REG_BASE,/*FIFO config reg4*/
101 GMAC_REG_FIFO_CFG5 = 0x5c + GMAC_REG_BASE,/*FIFO config reg5*/
102 GMAC_REG_FIFO_RAM0 = 0x60 + GMAC_REG_BASE,/*FIFO RAM access reg0*/
103 GMAC_REG_FIFO_RAM1 = 0x64 + GMAC_REG_BASE,/*FIFO RAM access reg1*/
104 GMAC_REG_FIFO_RAM2 = 0x68 + GMAC_REG_BASE,/*FIFO RAM access reg2*/
105 GMAC_REG_FIFO_RAM3 = 0x6c + GMAC_REG_BASE,/*FIFO RAM access reg3*/
106 GMAC_REG_FIFO_RAM4 = 0x70 + GMAC_REG_BASE,/*FIFO RAM access reg4*/
107 GMAC_REG_FIFO_RAM5 = 0x74 + GMAC_REG_BASE,/*FIFO RAM access reg5*/
108 GMAC_REG_FIFO_RAM6 = 0x78 + GMAC_REG_BASE,/*FIFO RAM access reg6*/
109 GMAC_REG_FIFO_RAM7 = 0x7c + GMAC_REG_BASE,/*FIFO RAM access reg7*/
113 RST_GMAC = (1 << 9),/*Reset the GMAC */
114 RST_MII = (3 << 11),/*Reset the MII*/
115 RST_OTHERS = 0x5df,/*Reset everybody other than GMAC & MII*/
118 enum __mag_reg_rst_ahb{
121 enum __mag_mii0_ctrl{
122 MII0_CTRL_MODE = (1 << 0),/*MII mode*/
123 MII0_CTRL_100 = (1 << 4),/*MII control address 100 Mbps*/
127 MDIO_CMD_DONE = 0x01,/*Operation over*/
128 MDIO_CMD_WRITE = 0x02,/*Write data*/
129 MDIO_CMD_READ = 0x03 /*Read data*/
132 MDIO_OWN_HST = 0x00,/*Host can use CMD & Data Regs*/
133 MDIO_OWN_TGT = 0x01 /*Tgt can use CMD & Data Regs*/
136 enum __gmac_reg_mac_cfg1{
137 MAC_CFG1_TX_EN = (1 << 0),/*TX enable*/
138 MAC_CFG1_RX_EN = (1 << 2),/*RX enable*/
139 MAC_CFG1_TX_FLOW = (1 << 4),/*TX Flow control enable*/
140 MAC_CFG1_RX_FLOW = (1 << 5),/*RX Flow control enable*/
141 MAC_CFG1_LOOP_EN = (1 << 8),/*Enable loopback*/
143 enum __gmac_reg_mac_cfg2{
144 MAC_CFG2_FULL_DUP = (1 << 0),/*Enable Full Duplex*/
145 MAC_CFG2_PAD_CRC = (1 << 2),/*Enable MAC based CRC insertion*/
146 MAC_CFG2_CHK_LEN = (1 << 4),/*Check Length field*/
147 MAC_CFG2_HUGE_FRM = (1 << 5),/*Allow sending huge frames*/
148 MAC_CFG2_MII = (1 << 8),/*MAC is MII in mode*/
149 MAC_CFG2_GMII = (1 << 9),/*MAC is in GMII mode*/
150 MAC_CFG2_PREAMBLE = (7 << 12),/*Default Preamble Length*/
152 enum __gmac_reg_mii_cfg{
153 MII_CFG_CLK_2MHZ = 0x0006,/*Clock is 2Mhz*/
155 enum __gmac_reg_mii_addr{
156 MII_ADDR_RESET = 0x000,/*Flush the MII address register*/
157 MII_ADDR_PHY_REG = 0x011,/*Phy Status Reg*/
159 enum __gmac_reg_mii_ctrl{
160 MII_CTRL_FULL_DPLX = 0x0100,/*Full Duplex mode*/
161 MII_CTRL_SPEED_100 = 0x2000,/*Link Speed 100 Mbps*/
162 MII_CTRL_LOOPBACK = 0x4000,/*Enable Loopback mode at PHY*/
163 MII_CTRL_RESET = 0x8000,/*BMCR reset*/
165 enum __gma_reg_mii_cmd{
167 MII_CMD_READ = 0x1,/*Perform a Read cycle*/
169 enum __gmac_reg_fifo_cfg0{
170 FIFO_CFG0_EN = 0x1f00,/*Enable all the Fifo module*/
172 enum __gmac_reg_fifo_cfg1{
173 FIFO_CFG1_SIZE_2K = (0x7ff << 16),/*Fifo size is 2K*/
175 enum __gmac_reg_fifo_cfg4{
176 FIFO_CFG4_RX_ALL = 0x3ffff,/*receive all frames*/
178 enum __gmac_reg_if_ctrl{
179 IF_CTRL_SPEED_100 = (1 << 16),/*Interface speed 100 Mbps for MII*/
182 /*************************GMAC Data types*******************************/
183 typedef enum __gmac_pkt_type{
189 unsigned char dst[ETH_ALEN];/*destination eth addr */
190 unsigned char src[ETH_ALEN]; /*source ether addr*/
191 A_UINT16 etype;/*ether type*/
192 }__attribute__((packed));
194 * @brief this is will be in big endian format
206 }__attribute__((packed));
208 typedef struct __gmac_hdr{
211 A_UINT16 align_pad;/*pad it for 4 byte boundary*/
212 }__attribute__((packed)) __gmac_hdr_t;
214 /*********************************GMAC softC************************/
216 typedef struct __gmac_softc{
223 #define ret_pkt sw.send_buf_done
224 #define indicate_pkt sw.recv_buf
225 #define htc_ctx sw.context
226 /*********************************DEFINES**********************************/
227 #define hif_gmac_sc(_hdl) (__gmac_softc_t *)(_hdl)
228 #define gmac_hdr(_vbuf) (__gmac_hdr_t *)(_vbuf)->desc_list->buf_addr
229 #define GMAC_HLEN (sizeof(struct __gmac_hdr))
231 #define __gmac_mdelay(_msecs) A_DELAY_USECS((_msecs) * 1000)
233 int __gmac_xmit_buf(hif_handle_t hdl, int pipe, VBUF *vbuf);
234 void __gmac_reap_recv(__gmac_softc_t *sc, dma_engine_t eng_no);
236 /***********************************Globals********************************/
238 * @brief Engines are fixed
240 __gmac_softc_t gmac_sc = {
241 .gran = GMAC_MAX_PKT_LEN
243 A_UINT8 gmac_addr[ETH_ALEN] = {0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa};
244 A_UINT8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
246 /**************************************APIs********************************/
249 * @brief This a replica of the ADF_NBUF_ALLOC
258 __gmac_vbuf_alloc(A_UINT32 size, A_UINT32 reserve, A_UINT32 align)
263 buf = VBUF_alloc_vbuf();
265 desc = VDESC_alloc_vdesc();
266 desc->buf_addr = (A_UINT8 *)A_ALLOCRAM(size);
267 desc->buf_size = size;
268 desc->next_desc = NULL;
269 desc->data_offset = reserve;
273 buf->desc_list = desc;
280 * @brief This is a replica of ADF_NBUF_PULL_HEAD
288 __gmac_vbuf_pull_head(VBUF *buf, A_UINT32 len)
291 VDESC *desc = buf->desc_list;
293 desc->data_offset += len;
294 desc->data_size -= len;
295 buf->buf_length -= len;
296 ptr = desc->buf_addr + desc->data_offset;
301 * @brief This is a replica of ADF_NBUF_PUSH_HEAD
309 __gmac_vbuf_push_head(VBUF *buf, A_UINT32 len)
312 VDESC *desc = buf->desc_list;
314 desc->data_offset -= len;
315 desc->data_size += len;
316 buf->buf_length += len;
317 ptr = desc->buf_addr + desc->data_offset;
321 * @brief This is a replica ADF_NBUF_LAST
328 __gmac_vbuf_last(VBUF *buf)
330 VDESC *desc = buf->desc_list;
332 while(desc->next_desc != NULL)
333 desc = desc->next_desc;
338 * @brief This is a replica of ADF_NBUF_PUT_TAIL
346 __gmac_vbuf_put_tail(VBUF *buf, A_UINT32 len)
348 A_UINT8 *tail = NULL;
349 VDESC *last_desc = __gmac_vbuf_last(buf);
351 tail = ( last_desc->buf_addr + last_desc->data_offset +
352 last_desc->data_size );
354 last_desc->data_size += len;
355 buf->buf_length += len;
360 /************************************GMAC**********************************/
362 __gmac_reg_read16(A_UINT32 addr)
364 return *((volatile A_UINT16 *)addr);
368 __gmac_reg_write16(A_UINT32 addr, A_UINT16 val)
370 *((volatile A_UINT16 *)addr) = val;
375 __gmac_reg_read32(A_UINT32 addr)
377 return *((volatile A_UINT32 *)addr);
381 __gmac_reg_write32(A_UINT32 addr, A_UINT32 val)
383 *((volatile A_UINT32 *)addr) = val;
386 * @brief Read the MAC address from EEPROM
387 * XXX: read from real EEPROM
389 * @param mac (pointer to fill the mac address)
392 __gmac_rom_read_mac(A_UINT8 mac_addr[])
394 A_MEMCPY(mac_addr, gmac_addr, ETH_ALEN);
397 * @brief Write the MAC address into the Station address
403 __gmac_reg_write_mac(A_UINT8 mac_addr[])
405 A_UINT32 mac_lo = 0, mac_hi = 0;
407 A_MEMCPY(&mac_lo, mac_addr, 4);
408 A_MEMCPY(&mac_hi, mac_addr + 4, 2);
410 A_PRINTF("mac address = %x:%x:%x:%x:%x:%x\n",
411 mac_addr[0], mac_addr[1], mac_addr[2],
412 mac_addr[3], mac_addr[4], mac_addr[5]);
414 __gmac_reg_write32(GMAC_REG_MAC_ADDR1, mac_lo);
415 __gmac_reg_write32(GMAC_REG_MAC_ADDR2, mac_hi);
419 * @brief Wait for the MII operation to complete
422 __gmac_mii_op_wait(void)
426 r_data = __gmac_reg_read32(GMAC_REG_MII_PSTAT) & 0x1;
428 r_data = (__gmac_reg_read32(GMAC_REG_MII_PSTAT) & 0x1);
434 volatile A_UINT32 r_data;
435 volatile A_UINT32 w_data;
438 * Reset the GMAC controller from Magpie Reset Register
440 r_data = __gmac_reg_read32(MAG_REG_RST);
442 __gmac_reg_write32(MAG_REG_RST, r_data);
447 * Pull it out from the Reset State
449 r_data = __gmac_reg_read32(MAG_REG_RST);
451 __gmac_reg_write32(MAG_REG_RST, r_data);
456 r_data = __gmac_reg_read32(MAG_REG_RST);
457 r_data |= (RST_MII | RST_GMAC);
458 __gmac_reg_write32(MAG_REG_RST, r_data);
462 * Pull the MII out of reset
464 r_data = __gmac_reg_read32(MAG_REG_RST);
465 r_data &= ~( RST_MII | RST_GMAC);
466 __gmac_reg_write32(MAG_REG_RST, r_data);
471 * Reset other modules PCI, PCIE, USB & Eth PLL
474 // __gmac_reg_write32(MAG_REG_RST, RST_OTHERS);
479 * Reset the AHB Arb. Unit
481 r_data = __gmac_reg_read32(MAG_REG_RST_AHB);
482 r_data |= RST_AHB_GMAC;
483 __gmac_reg_write32(MAG_REG_RST_AHB, r_data);
486 * MII mode initialization
488 w_data = ( MAC_CFG2_FULL_DUP | MAC_CFG2_PAD_CRC | MAC_CFG2_CHK_LEN |
489 MAC_CFG2_HUGE_FRM | MAC_CFG2_MII | MAC_CFG2_PREAMBLE );
491 __gmac_reg_write32(GMAC_REG_MAC_CFG2, w_data);
494 * Enable FIFO modules
496 __gmac_reg_write32(GMAC_REG_FIFO_CFG0, FIFO_CFG0_EN);
499 * Mode = MII & Speed = 100 Mbps
501 w_data = ( MII0_CTRL_100 | MII0_CTRL_MODE );
502 __gmac_reg_write32(MAG_REG_MII0_CTRL, w_data);
505 * Set the interface speed to 100 Mbps
507 __gmac_reg_write32(GMAC_REG_IF_CTRL, IF_CTRL_SPEED_100);
510 * Fifo size set to 2K bytes
512 r_data = __gmac_reg_read32(GMAC_REG_FIFO_CFG1);
513 r_data |= FIFO_CFG1_SIZE_2K;
514 __gmac_reg_write32(GMAC_REG_FIFO_CFG1, r_data);
517 * Enable the transceiver
519 w_data = MAC_CFG1_RX_EN | MAC_CFG1_TX_EN;
520 __gmac_reg_write32(GMAC_REG_MAC_CFG1, w_data);
523 * Set the MII Clock to 2Mhz
525 __gmac_reg_write32(GMAC_REG_MII_CFG, MII_CFG_CLK_2MHZ);
528 * Programming the phy registers
530 __gmac_reg_write32(GMAC_REG_MII_ADDR, MII_ADDR_RESET);
533 * BMCR reset for the PHY
535 __gmac_reg_write32(GMAC_REG_MII_CTRL, MII_CTRL_RESET);
538 * Wait until the MII Reg write has been flushed
540 __gmac_mii_op_wait();
543 * PHY register 0x000 , BMCR
545 __gmac_reg_write32(GMAC_REG_MII_ADDR, MII_ADDR_RESET);
548 * Write the value in the register
550 w_data = ( MII_CTRL_FULL_DPLX | MII_CTRL_SPEED_100 | MII_CTRL_RESET);
551 __gmac_reg_write32(GMAC_REG_MII_CTRL, w_data);
553 __gmac_mii_op_wait();
556 * Pull the BMCR out of the reset state
558 __gmac_reg_write32(GMAC_REG_MII_ADDR, MII_ADDR_RESET);
560 w_data = (MII_CTRL_FULL_DPLX | MII_CTRL_SPEED_100);
561 __gmac_reg_write32(GMAC_REG_MII_ADDR, w_data);
563 __gmac_mii_op_wait();
566 * XXX: This should be for some debugging purpose, don't know
567 * why we should write into the GPIO Output Enable the value
568 * returned from PHY status register Read
570 __gmac_reg_write32(GMAC_REG_MII_CMD, MII_CMD_WRITE);
571 __gmac_reg_write32(GMAC_REG_MII_ADDR, MII_ADDR_PHY_REG);
572 __gmac_reg_write32(GMAC_REG_MII_CMD, MII_CMD_READ);
574 __gmac_mii_op_wait();
576 r_data = __gmac_reg_read32(GMAC_REG_MII_STAT);
578 __gmac_reg_write32(MAG_REG_GPIO_OE, r_data);
581 * Enable Receive Fifo
583 r_data = __gmac_reg_read32(GMAC_REG_FIFO_CFG4);
584 r_data |= FIFO_CFG4_RX_ALL;
585 __gmac_reg_write32(GMAC_REG_FIFO_CFG4, r_data);
589 * @brief return if the pipe is supported
595 static inline a_bool_t
596 __gmac_chk_pipe(hif_gmac_pipe_t pipe)
599 case HIF_GMAC_PIPE_TX:
600 case HIF_GMAC_PIPE_RX:
608 __gmac_pkt_alloc(A_UINT32 size)
617 buf = __gmac_vbuf_alloc(size, GMAC_HLEN, 0);
621 fill_size = size - GMAC_HLEN;
623 data = __gmac_vbuf_put_tail(buf, fill_size);
625 A_MEMSET(data, 0xaa, fill_size);
630 * @brief Slap the header
636 __gmac_put_hdr(VBUF * buf, __gmac_hdr_t *hdr)
640 data = __gmac_vbuf_push_head(buf, GMAC_HLEN);
642 A_MEMCPY(data, hdr, GMAC_HLEN);
651 __gmac_prep_ethhdr(__gmac_hdr_t *hdr, A_UINT8 *dst)
653 A_MEMCPY(hdr->eth.dst, dst, ETH_ALEN);
654 hdr->eth.etype = ETH_P_ATH;
659 __is_ath_header(__gmac_softc_t *sc, VBUF *vbuf)
661 __gmac_hdr_t *hdr = gmac_hdr(vbuf);
663 if(hdr->ath.proto != sc->hdr.ath.proto)
670 __gmac_process_discv(__gmac_softc_t *sc)
672 a_status_t err = A_STATUS_OK;
674 __gmac_hdr_t *buf_hdr ;
677 vbuf = dma_lib_reap_recv(DMA_ENGINE_RX0);
679 if(!__is_ath_header(sc, vbuf))
682 buf_hdr = gmac_hdr(vbuf);
684 A_MEMCPY(sc->hdr.eth.dst, buf_hdr->eth.src, ETH_ALEN);
686 __gmac_vbuf_pull_head(vbuf, GMAC_HLEN);
689 * Application should do the return_recv
691 sc->indicate_pkt(NULL, vbuf, sc->htc_ctx);
697 * This is not our packet
701 dma_lib_return_recv(DMA_ENGINE_RX0, vbuf);
706 * @brief The GMAC host discovery loop
709 __gmac_discover(void)
711 a_status_t err = A_STATUS_FAILED;
713 __gmac_softc_t *sc = &gmac_sc;
719 buf = __gmac_pkt_alloc(GMAC_DISCV_PKT_SZ);
722 * Prepare the broadcast packet
724 __gmac_prep_ethhdr(&sc->hdr, bcast_addr);
725 __gmac_put_hdr(buf, &sc->hdr);
730 dma_lib_hard_xmit(DMA_ENGINE_TX0, buf);
733 __gmac_mdelay(GMAC_DISCV_WAIT);
735 if(dma_lib_xmit_done(DMA_ENGINE_TX0))
736 buf = dma_lib_reap_xmitted(DMA_ENGINE_TX0);
739 while(dma_lib_recv_pkt(DMA_ENGINE_RX0) && err)
740 err = __gmac_process_discv(sc);
750 __gmac_mdio_check(void)
754 /*Read the Ownership register*/
756 own = __gmac_reg_read16(MAG_REG_MDIO_OWN);
757 } while ( own == MDIO_OWN_TGT );
762 __gmac_mdio_load_exec(void)
764 volatile A_UINT16 cmd, more = 1 ;
765 volatile A_UINT16 *addr[2];
766 void ( *exec_fn)(void) = NULL;
770 * Read the Command register
772 cmd = __gmac_reg_read16(MAG_REG_MDIO_CMD);
779 * 1. Read the address from Address register
780 * 2. Write the data from Data register into the address
782 (A_UINT16 *)addr[0] = __gmac_reg_read16(MAG_REG_MDIO_ADDR0);
783 *addr[0] = __gmac_reg_read16(MAG_REG_MDIO_WRITE0);
785 (A_UINT16 *)addr[1] = __gmac_reg_read16(MAG_REG_MDIO_ADDR1);
786 *addr[1] = __gmac_reg_read16(MAG_REG_MDIO_WRITE1);
791 exec_fn = (A_UINT32 *)addr;
802 * 1. Read the address from Address register
803 * 2. Write the data into the Data register from the address
805 addr[0] = (A_UINT16 *)__gmac_reg_read16(MAG_REG_MDIO_ADDR0);
806 __gmac_reg_write16(MAG_REG_MDIO_READ0, *addr[0]);
808 addr[1] = (A_UINT16 *)__gmac_reg_read16(MAG_REG_MDIO_ADDR1);
809 __gmac_reg_write16(MAG_REG_MDIO_READ1, *addr[1]);
814 A_PRINTF("Command not implemmented\n");
822 * Change the Ownership
824 __gmac_reg_write16(MAG_REG_MDIO_OWN, MDIO_OWN_HST);
832 __gmac_mdio_init(void)
838 * Check for Targets turn
843 * Load & execute or Read data, if this returns then keep
846 __gmac_mdio_load_exec();
849 * If we are here then Host wants some more function execs or
856 __gmac_boot_init(void)
858 __gmac_softc_t *sc = &gmac_sc;
866 sc->hdr.ath.proto = ATH_P_MAGBOOT;
868 dma_lib_tx_init(DMA_ENGINE_TX0, DMA_IF_GMAC);
869 dma_lib_rx_init(DMA_ENGINE_RX0, DMA_IF_GMAC);
871 dma_lib_rx_config(DMA_ENGINE_RX0, GMAC_MAX_DESC, GMAC_MAX_PKT_LEN);
874 * Read the MAC address from the ROM & Write it into the
877 __gmac_rom_read_mac(sc->hdr.eth.src);
878 __gmac_reg_write_mac(sc->hdr.eth.src);
890 * @return hif_handle_t
893 __gmac_init(HIF_CONFIG *pConfig)
895 __gmac_softc_t *sc = &gmac_sc;
897 sc->hdr.ath.proto = ATH_P_MAGNORM;
899 dma_lib_tx_init(DMA_ENGINE_TX0, DMA_IF_GMAC);
900 dma_lib_rx_init(DMA_ENGINE_RX0, DMA_IF_GMAC);
905 * @brief Configure the receive pipe
912 __gmac_cfg_pipe(hif_handle_t hdl, int pipe, int num_desc)
914 __gmac_softc_t *sc = &gmac_sc;
916 if(pipe == HIF_GMAC_PIPE_RX)
917 dma_lib_rx_config(DMA_ENGINE_RX0, num_desc, sc->gran);
920 * @brief Start the interface
925 __gmac_start(hif_handle_t hdl)
930 * @brief Register callback of thre HTC
936 __gmac_reg_callback(hif_handle_t hdl, HIF_CALLBACK *sw)
938 __gmac_softc_t *sc = &gmac_sc;
940 sc->htc_ctx = sw->context;
941 sc->indicate_pkt = sw->recv_buf;
942 sc->ret_pkt = sw->send_buf_done;
945 * @brief reap the transmit queue for trasnmitted packets
951 __gmac_reap_xmitted(__gmac_softc_t *sc, dma_engine_t eng_no)
955 * Walk through the all your TX engines
959 vbuf = dma_lib_reap_xmitted(eng_no);
963 __gmac_vbuf_pull_head(vbuf, GMAC_HLEN);
964 sc->ret_pkt(vbuf, sc->htc_ctx);
969 * @brief reap the receive queue for vbuf's on the specified
976 __gmac_reap_recv(__gmac_softc_t *sc, dma_engine_t eng_no)
981 vbuf = dma_lib_reap_recv(eng_no);
986 if(!__is_ath_header(sc, vbuf)){
987 dma_lib_return_recv(eng_no, vbuf);
991 __gmac_vbuf_pull_head(vbuf, GMAC_HLEN);
993 sc->indicate_pkt(NULL, vbuf, sc->htc_ctx);
998 * @brief The interrupt handler
1003 __gmac_isr_handler(hif_handle_t hdl)
1005 __gmac_softc_t *sc = &gmac_sc;
1007 if(dma_lib_xmit_done(DMA_ENGINE_TX0))
1008 __gmac_reap_xmitted(sc, DMA_ENGINE_TX0);
1010 if(dma_lib_recv_pkt(DMA_ENGINE_RX0))
1011 __gmac_reap_recv(sc, DMA_ENGINE_RX0);
1014 * @brief transmit the vbuf from the specified pipe
1023 __gmac_xmit_buf(hif_handle_t hdl, int pipe, VBUF *vbuf)
1025 __gmac_softc_t *sc = &gmac_sc;
1027 if (pipe != HIF_GMAC_PIPE_TX)
1031 adf_os_assert( vbuf->desc_list->data_offset >= GMAC_HLEN)
1034 __gmac_put_hdr(vbuf, &sc->hdr);
1036 return dma_lib_hard_xmit(DMA_ENGINE_TX0, vbuf);
1039 * @brief Submit the receive vbuf into the receive queue
1046 __gmac_return_recv(hif_handle_t hdl, int pipe, VBUF *vbuf)
1048 if (pipe == HIF_GMAC_PIPE_RX)
1049 dma_lib_return_recv(DMA_ENGINE_RX0, vbuf);
1052 * @brief Is this pipe number supported
1060 __gmac_is_pipe_supported(hif_handle_t hdl, int pipe)
1062 return __gmac_chk_pipe(pipe);
1065 * @brief maximum message length this pipe can support
1073 __gmac_get_max_msg_len(hif_handle_t hdl, int pipe)
1075 if(__gmac_chk_pipe(pipe))
1076 return GMAC_MAX_PKT_LEN;
1081 * @brief return the header room required by this HIF
1088 __gmac_get_reserved_headroom(hif_handle_t hdl)
1093 * @brief Device shutdown, HIF reset required
1098 __gmac_shutdown(hif_handle_t hdl)
1103 __gmac_get_def_pipe(hif_handle_t handle, A_UINT8 *pipe_uplink,
1104 A_UINT8 *pipe_downlink)
1106 *pipe_uplink = HIF_GMAC_PIPE_RX;
1107 *pipe_downlink = HIF_GMAC_PIPE_TX;
1111 * @brief This install the API's of the HIF
1116 hif_gmac_module_install(struct hif_api *apis)
1119 apis->_init = __gmac_init;
1120 apis->_start = __gmac_start;
1121 apis->_config_pipe = __gmac_cfg_pipe;
1122 apis->_isr_handler = __gmac_isr_handler;
1123 apis->_send_buffer = __gmac_xmit_buf;
1124 apis->_return_recv_buf = __gmac_return_recv;
1125 apis->_is_pipe_supported = __gmac_is_pipe_supported;
1126 apis->_get_max_msg_len = __gmac_get_max_msg_len;
1127 apis->_register_callback = __gmac_reg_callback;
1128 apis->_shutdown = __gmac_shutdown;/*XXX*/
1129 apis->_get_reserved_headroom = __gmac_get_reserved_headroom;
1130 apis->_get_default_pipe = __gmac_get_def_pipe;
1134 cmnos_gmac_module_install(struct gmac_api *boot_apis)
1136 boot_apis->gmac_boot_init = __gmac_boot_init;