1 #ifndef SHARED_MEMORY_H_
2 #define SHARED_MEMORY_H_
4 /* SHM (Shared Memory) offsets */
6 /* Host-side routing values for the SHM.
7 * This is only useful for the initvals */
8 #define HOST_SHM_UCODE 0
9 #define HOST_SHM_SHARED 1
10 #define HOST_SHM_SCRATCH 2
11 #define HOST_SHM_IHR 3
12 #define HOST_SHM_RCMTA 4
15 /* Macro to convert a host-SHM-address to a microcode-SHM-address.
16 * This also asserts that the address is word aligned. */
17 #define SHM(address) (((address) / 2) + \
18 (%assert((address & 1) == 0)))
19 /* Macro to convert a byte-offset into a microcode-SHM-word-offset.
20 * This does the same as SHM(), but is used to mark offsets that are not
21 * based on absolute zero, but relative. */
22 #define SHM_OFFSET(offset) SHM(offset)
25 /* BEGIN ABI: Start of the driver ABI definitions */
29 #define SHM_WLCOREREV SHM(0x016) /* 802.11 core revision */
30 #define SHM_PCTLWDPOS SHM(0x008)
31 #define SHM_RXPADOFF SHM(0x034) /* RX Padding data offset (PIO only) */
32 #define SHM_PHYVER SHM(0x050) /* PHY version */
33 #define SHM_PHYTYPE SHM(0x052) /* PHY type */
34 #define SHM_ANTSWAP SHM(0x05C) /* Antenna swap threshold */
36 // New SHM addresses; Source: d11.h 578947 2015-08-13 04:46:06Z
37 // http://github.com/tuapuikia/asuswrt-phantom/blob/master/release/src-rt-7.14.114.x/src/include/d11.h
38 /* Host flags to turn on ucode options */
39 #define SHM_HOST_FLAGS1 SHM(0x05E)
40 #define SHM_HOST_FLAGS1_ANTDIVHELP 0 /* bit0: ucode antenna div helper */
41 #define SHM_HOST_FLAGS1_SYMW 1 /* bit1: G-PHY SYM workaround */
42 #define SHM_HOST_FLAGS1_RXPULLW 2 /* bit2: RX pullup workaround */
43 #define SHM_HOST_FLAGS1_CCKBOOST 3 /* bit3: 4dB CCK power boost (exclusive with OFDM boost) */
44 #define SHM_HOST_FLAGS1_BTCOEX 4 /* bit4: Bluetooth coexistence */
45 #define SHM_HOST_FLAGS1_GDCW 5 /* bit5: G-PHY DC canceller filter bw workaround */
46 #define SHM_HOST_FLAGS1_OFDMPABOOST 6 /* bit6: Enable PA gain boost for OFDM */
47 #define SHM_HOST_FLAGS1_ACPR 7 /* bit7: Disable for Japan, channel 14 */
48 #define SHM_HOST_FLAGS1_EDCF 8 /* bit8: on if WME and MAC suspended */
49 #define SHM_HOST_FLAGS1_TSSIRPSMW 9 /* bit9: TSSI reset PSM ucode workaround */
50 #define SHM_HOST_FLAGS1_20IN40IQW 9 /* bit9: 20 in 40 MHz I/Q workaround (rev >= 13 only) */
51 #define SHM_HOST_FLAGS1_DSCRQ 10 /* bit10: Disable slow clock request in ucode */
52 #define SHM_HOST_FLAGS1_ACIW 11 /* bit11: ACI workaround: shift bits by 2 on PHY CRS */
53 #define SHM_HOST_FLAGS1_2060W 12 /* bit12: 2060 radio workaround */
54 #define SHM_HOST_FLAGS1_RADARW 13 /* bit13: Radar workaround */
55 #define SHM_HOST_FLAGS1_USEDEFKEYS 14 /* bit14: Enable use of default keys */
56 #define SHM_HOST_FLAGS1_AFTERBURNER 15 /* bit15: Afterburner enabled */
57 #define SHM_HOST_FLAGS2 SHM(0x060)
58 #define SHM_HOST_FLAGS2_BT4PRIOCOEX 0 /* bit0: Bluetooth 4-priority coexistence */
59 #define SHM_HOST_FLAGS2_FWKUP 1 /* bit1: Fast wake-up ucode */
60 #define SHM_HOST_FLAGS2_VCORECALC 2 /* bit2: Force VCO recalculation when powering up synthpu */
61 #define SHM_HOST_FLAGS2_PCISCW 3 /* bit3: PCI slow clock workaround */
62 #define SHM_HOST_FLAGS2_4318TSSI 5 /* bit5: 4318 TSSI */
63 #define SHM_HOST_FLAGS2_FBCMCFIFO 6 /* bit6: Flush bcast/mcast FIFO immediately */
64 #define SHM_HOST_FLAGS2_HWPCTL 7 /* bit7: Enable hardware power control */
65 #define SHM_HOST_FLAGS2_BTCOEXALT 8 /* bit8: Bluetooth coexistence in alternate pins */
66 #define SHM_HOST_FLAGS2_TXBTCHECK 9 /* bit9: Bluetooth check during transmission */
67 #define SHM_HOST_FLAGS2_SKCFPUP 10 /* bit10: Skip CFP update */
68 #define SHM_HOST_FLAGS2_N40W 11 /* bit11: N PHY 40 MHz workaround (rev >= 13 only) */
69 #define SHM_HOST_FLAGS2_ANTSEL 13 /* bit13: Antenna selection (for testing antenna div.) */
70 #define SHM_HOST_FLAGS2_BT3COEXT 13 /* bit13: Bluetooth 3-wire coexistence (rev >= 13 only) */
71 #define SHM_HOST_FLAGS2_BTCANT 14 /* bit14: Bluetooth coexistence (antenna mode) (rev >= 13 only) */
72 #define SHM_HOST_FLAGS3 SHM(0x062)
73 #define SHM_HOST_FLAGS3_ANTSELEN 0 /* bit0: Antenna selection enabled (rev >= 13 only) */
74 #define SHM_HOST_FLAGS3_ANTSELMODE 1 /* bit1: Antenna selection mode (rev >= 13 only) */
75 #define SHM_HOST_FLAGS3_MLADVW 4 /* bit4: N PHY ML ADV workaround (rev >= 13 only) */
76 #define SHM_HOST_FLAGS3_PR45960W 11 /* bit11: PR 45960 workaround (rev >= 13 only) */
77 #define SHM_HOST_FLAGS4 SHM(0x078)
78 #define SHM_HOST_FLAGS5 SHM(0x0D4)
80 #define SHM_RFATT SHM(0x064) /* Current radio attenuation value */
81 #define SHM_RADAR SHM(0x066) /* Radar register */
82 #define SHM_PHYTXNOI SHM(0x06E) /* PHY noise directly after TX (lower 8bit only) */
83 #define SHM_RFRXSP1 SHM(0x072) /* RF RX SP Register 1 */
84 #define SHM_CHAN SHM(0x0A0) /* Current channel (low 8bit only) */
85 #define SHM_GCLASSCTL SHM(0x0A6) /* Value for the G-PHY classify control register */
86 #define SHM_BCMCFIFOID SHM(0x108) /* Last posted cookie to the bcast/mcast FIFO */
88 /* TSSI information */
89 #define SHM_TSSI_CCK_LO SHM(0x058) /* TSSI for the last 4 CCK frames (low) */
90 #define SHM_TSSI_CCK_HI SHM(0x05A) /* TSSI for the last 4 CCK frames (high) */
91 #define SHM_TSSI_OFDM_A_LO SHM(0x068) /* TSSI for the last 4 OFDM (A) frames (low) */
92 #define SHM_TSSI_OFDM_A_HI SHM(0x06A) /* TSSI for the last 4 OFDM (A) frames (high) */
93 #define SHM_TSSI_OFDM_G_LO SHM(0x070) /* TSSI for the last 4 OFDM (G) frames (low) */
94 #define SHM_TSSI_OFDM_G_HI SHM(0x072) /* TSSI for the last 4 OFDM (G) frames (high) */
96 /* TX FIFO variables */
97 #define SHM_TXFIFO_SIZE01 SHM(0x098) /* TX FIFO size for FIFO 0 (low) and 1 (high) */
98 #define SHM_TXFIFO_SIZE23 SHM(0x09A) /* TX FIFO size for FIFO 2 and 3 */
99 #define SHM_TXFIFO_SIZE45 SHM(0x09C) /* TX FIFO size for FIFO 4 and 5 */
100 #define SHM_TXFIFO_SIZE67 SHM(0x09E) /* TX FIFO size for FIFO 6 and 7 */
102 /* Background noise */
103 #define SHM_JSSI0 SHM(0x088) /* Measure JSSI 0 */
104 #define SHM_JSSI1 SHM(0x08A) /* Measure JSSI 1 */
105 #define SHM_JSSIAUX SHM(0x08C) /* Measure JSSI AUX */
108 #define SHM_DEFAULTIV SHM(0x03C) /* Default IV location */
109 #define SHM_NRRXTRANS SHM(0x03E) /* # of soft RX transmitter addresses (max 8) */
110 #define SHM_KTP SHM(0x056) /* Key table pointer */
111 #define SHM_TKIP_P1KEYS SHM(0x2E0) /* TKIP Phase 1 keys. */
112 #define SHM_KEYIDXBLOCK SHM(0x5D4) /* Key index/algorithm block. */
115 #define SHM_EDCFSTAT SHM(0x00E) /* EDCF status */
116 #define SHM_TXFCUR SHM(0x030) /* TXF current index */
117 #define SHM_EDCFQ SHM(0x240) /* EDCF Q info */
119 /* Powersave mode related variables */
120 #define SHM_SLOTT SHM(0x010) /* Slot time */
121 #define SHM_DTIMPER SHM(0x012) /* DTIM period */
122 #define SHM_NOSLPZNATDTIM SHM(0x04C) /* NOSLPZNAT DTIM */
124 /* Beacon/AP variables */
125 #define SHM_BTL0 SHM(0x018) /* Beacon template length 0 */
126 #define SHM_BTL1 SHM(0x01A) /* Beacon template length 1 */
127 #define SHM_BTSFOFF SHM(0x01C) /* Beacon TSF offset */
128 #define SHM_TIMBPOS SHM(0x01E) /* TIM B position in beacon */
129 #define SHM_DTIMP SHM(0x012) /* DTIP period */
130 #define SHM_MCASTCOOKIE SHM(0x0A8) /* Last bcast/mcast frame ID */
131 #define SHM_SFFBLIM SHM(0x044) /* Short frame fallback retry limit */
132 #define SHM_LFFBLIM SHM(0x046) /* Long frame fallback retry limit */
133 #define SHM_BEACPHYCTL SHM(0x054) /* Beacon PHY TX control word (see PHY TX control) */
134 #define SHM_EXTNPHYCTL SHM(0x0B0) /* Extended bytes for beacon PHY control (N) */
136 /* ACK/CTS control */
137 #define SHM_ACKCTSPHYCTL SHM(0x022) /* ACK/CTS PHY control word (see PHY TX control) */
139 /* Probe response variables */
140 #define SHM_PRSSID SHM(0x160) /* Probe Response SSID */
141 #define SHM_PRSSIDLEN SHM(0x048) /* Probe Response SSID length */
142 #define SHM_PRTLEN SHM(0x04A) /* Probe Response template length */
143 #define SHM_PRMAXTIME SHM(0x074) /* Probe Response max time */
144 #define SHM_PRPHYCTL SHM(0x188) /* Probe Response PHY TX control word */
147 #define SHM_OFDMDIRECT SHM(0x1C0) /* Pointer to OFDM direct map */
148 #define SHM_OFDMBASIC SHM(0x1E0) /* Pointer to OFDM basic rate map */
149 #define SHM_CCKDIRECT SHM(0x200) /* Pointer to CCK direct map */
150 #define SHM_CCKBASIC SHM(0x220) /* Pointer to CCK basic rate map */
152 /* Microcode soft registers */
153 #define SHM_UCODEREV SHM(0x000) /* Microcode revision */
154 #define SHM_UCODEPATCH SHM(0x002) /* Microcode patchlevel */
155 #define SHM_UCODEDATE SHM(0x004) /* Microcode date */
156 #define SHM_UCODETIME SHM(0x006) /* Microcode time */
157 #define SHM_UCODESTAT SHM(0x040) /* Microcode debug status code */
158 #define SHM_UCODESTAT_INVALID 0
159 #define SHM_UCODESTAT_INIT 1
160 #define SHM_UCODESTAT_ACTIVE 2
161 #define SHM_UCODESTAT_SUSP 3 /* suspended */
162 #define SHM_UCODESTAT_SLEEP 4 /* asleep (PS) */
163 #define SHM_MAXBFRAMES SHM(0x080) /* Maximum number of frames in a burst */
164 #define SHM_SPUWKUP SHM(0x094) /* pre-wakeup for synth PU in us */
165 #define SHM_PRETBTT SHM(0x096) /* pre-TBTT in us */
169 /* TX header WORD(!) offsets. These are used as offsets into the TX header
170 * information fields in SHM for each FIFO via offset register pointer. */
171 #define TXHDR_MACLO SHM_OFFSET(0x00) /* MAC control lo */
172 #define TXHDR_MACLO_DFCS 6 /* bit6: Do not generate FCS */
173 #define TXHDR_MACHI SHM_OFFSET(0x02) /* MAC control hi */
174 #define TXHDR_FCTL SHM_OFFSET(0x04) /* Frame Control field copy */
175 #define TXHDR_FES SHM_OFFSET(0x06) /* TX FES Time Normal */
176 #define TXHDR_PHYCTL SHM_OFFSET(0x08) /* PHY control word */
177 #define TXHDR_PHYCTL1 SHM_OFFSET(0x0A) /* PHY control word 1 */
178 #define TXHDR_PHYCTL1FB SHM_OFFSET(0x0C) /* PHY control word 1 for fallback */
179 #define TXHDR_PHYCTL1RTS SHM_OFFSET(0x0E) /* PHY control word 1 RTS */
180 #define TXHDR_PHYCTL1RTSFB SHM_OFFSET(0x10) /* PHY control word 1 RTS for fallback */
181 #define TXHDR_PHYRATES SHM_OFFSET(0x12) /* PHY rates */
182 #define TXHDR_EFT SHM_OFFSET(0x14) /* Extra Frame Types */
183 #define TXHDR_IV SHM_OFFSET(0x16) /* IV / crypto field */
184 #define TXHDR_RA SHM_OFFSET(0x26) /* Frame receiver address */
185 #define TXHDR_FESFB SHM_OFFSET(0x2C) /* TX FES Time fallback */
186 #define TXHDR_RTSPLCPFB SHM_OFFSET(0x2E) /* RTS PLCP fallback */
187 #define TXHDR_RTSDURFB SHM_OFFSET(0x34) /* RTS duration fallback */
188 #define TXHDR_PLCPFB SHM_OFFSET(0x36) /* PLCP fallback */
189 #define TXHDR_DURFB SHM_OFFSET(0x3C) /* Duration fallback */
190 #define TXHDR_MIMOML SHM_OFFSET(0x3E) /* MIMO mode length */
191 #define TXHDR_MIMOFBRL SHM_OFFSET(0x40) /* MIMO fallback rate length */
192 #define TXHDR_TOLO SHM_OFFSET(0x42) /* Timeout low */
193 #define TXHDR_TOHI SHM_OFFSET(0x44) /* Timeout high */
194 #define TXHDR_MIMOAS SHM_OFFSET(0x46) /* MIMO antenna select */
195 #define TXHDR_PRELSZ SHM_OFFSET(0x48) /* Preload size */
196 #define TXHDR_UNUSED1 SHM_OFFSET(0x4A) /* Unused padding */
197 #define TXHDR_COOKIE SHM_OFFSET(0x4C) /* Frame ID */
198 #define TXHDR_STAT SHM_OFFSET(0x4E) /* Status */
199 #define TXHDR_RTSPLCP SHM_OFFSET(0x50) /* RTS PLCP header */
200 #define TXHDR_RTS SHM_OFFSET(0x56) /* RTS frame */
201 #define TXHDR_UNUSED2 SHM_OFFSET(0x66) /* Unused padding */
202 #define TXHDR_WSIZE (104 / 2) /* Header size, in words */
203 #define TXHDR_NR_COPY_BYTES (TXHDR_RTSPLCP * 2) /* We copy everything up to the RTS header to SHM */
206 /* END ABI: End of the driver ABI definitions */
208 #endif /* SHARED_MEMORY_H_ */
210 // vim: syntax=b43 ts=8