2 * carl9170 firmware - used by the ar9170 wireless device
4 * This module contains DMA descriptor related definitions.
6 * Copyright (c) 2000-2005 ZyDAS Technology Corporation
7 * Copyright (c) 2007-2009 Atheros Communications, Inc.
8 * Copyright 2009 Johannes Berg <johannes@sipsolutions.net>
9 * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
26 #ifndef __CARL9170FW_DMA_H
27 #define __CARL9170FW_DMA_H
33 #include "ieee80211.h"
37 volatile uint16_t status; /* Descriptor status */
38 volatile uint16_t ctrl; /* Descriptor control */
39 volatile uint16_t dataSize; /* Data size */
40 volatile uint16_t totalLen; /* Total length */
41 struct dma_desc *lastAddr; /* Last address of this chain */
43 uint8_t *_dataAddr; /* Data buffer address */
46 struct dma_desc *nextAddr; /* Next TD address */
47 } __packed __aligned(4);
49 /* Up, Dn, 5x Tx, retry, Rx, [USB Int], (CAB), FW */
50 #define AR9170_TERMINATOR_NUMBER_B 10
52 #define AR9170_TERMINATOR_NUMBER_INT 1
54 #ifdef CONFIG_CARL9170FW_CAB_QUEUE
55 #define AR9170_TERMINATOR_NUMBER_CAB CARL9170_INTF_NUM
57 #define AR9170_TERMINATOR_NUMBER_CAB 0
58 #endif /* CONFIG_CARL9170FW_CAB_QUEUE */
60 #define AR9170_TERMINATOR_NUMBER (AR9170_TERMINATOR_NUMBER_B + \
61 AR9170_TERMINATOR_NUMBER_INT + \
62 AR9170_TERMINATOR_NUMBER_CAB)
64 #define AR9170_BLOCK_SIZE (256 + 64)
66 #define AR9170_DESCRIPTOR_SIZE (sizeof(struct dma_desc))
68 struct ar9170_tx_ba_frame {
69 struct ar9170_tx_hwdesc hdr;
70 struct ieee80211_ba ba;
73 struct carl9170_tx_ba_superframe {
74 struct carl9170_tx_superdesc s;
75 struct ar9170_tx_ba_frame f;
78 struct ar9170_tx_null_frame {
79 struct ar9170_tx_hwdesc hdr;
80 struct ieee80211_hdr null;
83 struct carl9170_tx_null_superframe {
84 struct carl9170_tx_superdesc s;
85 struct ar9170_tx_null_frame f;
88 #define CARL9170_BA_BUFFER_LEN (__roundup(sizeof(struct carl9170_tx_ba_superframe), 16))
89 #define CARL9170_RSP_BUFFER_LEN AR9170_BLOCK_SIZE
91 struct carl9170_sram_reserved {
93 uint32_t buf[CARL9170_BA_BUFFER_LEN / sizeof(uint32_t)];
94 struct carl9170_tx_ba_superframe ba;
98 uint32_t buf[CARL9170_MAX_CMD_LEN / sizeof(uint32_t)];
99 struct carl9170_cmd cmd;
101 #ifdef CONFIG_CARL9170FW_WOL
102 struct carl9170_tx_null_superframe null;
103 #endif /* CONFIG_CARL9170FW_WOL */
107 uint32_t buf[CARL9170_RSP_BUFFER_LEN / sizeof(uint32_t)];
108 struct carl9170_rsp rsp;
112 uint32_t buf[CARL9170_INTF_NUM][AR9170_MAC_BCN_LENGTH_MAX / sizeof(uint32_t)];
117 * Memory layout in RAM:
120 * | terminator descriptors (dma_desc)
121 * | - Up (to USB host)
122 * | - Down (from USB host)
123 * | - TX (5x, to wifi)
127 * | - FW cmd & req descriptor
128 * | - BlockAck descriptor
129 * | total: AR9170_TERMINATOR_NUMBER
131 * | block descriptors (dma_desc)
132 * | (AR9170_BLOCK_NUMBER)
133 * AR9170_BLOCK_BUFFER_BASE +-- align to multiple of 64
134 * | block buffers (AR9170_BLOCK_SIZE each)
135 * | (AR9170_BLOCK_NUMBER)
136 * approx. 0x117c00 +--
137 * | BA buffer (128 bytes)
139 * | CMD buffer (128 bytes)
140 * | - used as NULLFRAME buffer (128 bytes) for WOL
142 * | RSP buffer (320 bytes)
144 * | BEACON buffer (256 bytes)
146 * | unaccounted space / padding
151 #define CARL9170_SRAM_RESERVED (sizeof(struct carl9170_sram_reserved))
153 #define AR9170_FRAME_MEMORY_SIZE (AR9170_SRAM_SIZE - CARL9170_SRAM_RESERVED)
155 #define BLOCK_ALIGNMENT 64
157 #define NONBLOCK_DESCRIPTORS_SIZE \
158 (AR9170_DESCRIPTOR_SIZE * (AR9170_TERMINATOR_NUMBER))
160 #define NONBLOCK_DESCRIPTORS_SIZE_ALIGNED \
161 (ALIGN(NONBLOCK_DESCRIPTORS_SIZE, BLOCK_ALIGNMENT))
163 #define AR9170_BLOCK_NUMBER ((AR9170_FRAME_MEMORY_SIZE - NONBLOCK_DESCRIPTORS_SIZE_ALIGNED) / \
164 (AR9170_BLOCK_SIZE + AR9170_DESCRIPTOR_SIZE))
166 struct ar9170_data_block {
167 uint8_t data[AR9170_BLOCK_SIZE];
170 struct ar9170_dma_memory {
171 struct dma_desc terminator[AR9170_TERMINATOR_NUMBER];
172 struct dma_desc block[AR9170_BLOCK_NUMBER];
173 struct ar9170_data_block data[AR9170_BLOCK_NUMBER] __aligned(BLOCK_ALIGNMENT);
174 struct carl9170_sram_reserved reserved __aligned(BLOCK_ALIGNMENT);
177 extern struct ar9170_dma_memory dma_mem;
179 #define AR9170_DOWN_BLOCK_RATIO 2
180 #define AR9170_RX_BLOCK_RATIO 1
181 /* Tx 16*2 = 32 packets => 32*(5*320) */
182 #define AR9170_TX_BLOCK_NUMBER (AR9170_BLOCK_NUMBER * AR9170_DOWN_BLOCK_RATIO / \
183 (AR9170_RX_BLOCK_RATIO + AR9170_DOWN_BLOCK_RATIO))
184 #define AR9170_RX_BLOCK_NUMBER (AR9170_BLOCK_NUMBER - AR9170_TX_BLOCK_NUMBER)
187 #define AR9170_ERR_FS_BIT 1
188 #define AR9170_ERR_LS_BIT 2
189 #define AR9170_ERR_OWN_BITS 3
190 #define AR9170_ERR_DATA_SIZE 4
191 #define AR9170_ERR_TOTAL_LEN 5
192 #define AR9170_ERR_DATA 6
193 #define AR9170_ERR_SEQ 7
194 #define AR9170_ERR_LEN 8
196 /* Status bits definitions */
197 /* Own bits definitions */
198 #define AR9170_OWN_BITS 0x3
199 #define AR9170_OWN_BITS_S 0
200 #define AR9170_OWN_BITS_SW 0x0
201 #define AR9170_OWN_BITS_HW 0x1
202 #define AR9170_OWN_BITS_SE 0x2
204 /* Control bits definitions */
205 #define AR9170_CTRL_TXFAIL 1
206 #define AR9170_CTRL_BAFAIL 2
207 #define AR9170_CTRL_FAIL (AR9170_CTRL_TXFAIL | AR9170_CTRL_BAFAIL)
209 /* First segament bit */
210 #define AR9170_CTRL_LS_BIT 0x100
211 /* Last segament bit */
212 #define AR9170_CTRL_FS_BIT 0x200
215 struct dma_desc *head;
216 struct dma_desc *terminator;
219 #define DESC_PAYLOAD(a) ((void *)a->dataAddr)
220 #define DESC_PAYLOAD_OFF(a, offset) ((void *)((unsigned long)(a->_dataAddr) + offset))
222 struct dma_desc *dma_unlink_head(struct dma_queue *queue);
223 void dma_init_descriptors(void);
224 void dma_reclaim(struct dma_queue *q, struct dma_desc *desc);
225 void dma_put(struct dma_queue *q, struct dma_desc *desc);
227 static inline __inline bool is_terminator(struct dma_queue *q, struct dma_desc *desc)
229 return q->terminator == desc;
232 static inline __inline bool queue_empty(struct dma_queue *q)
234 return q->head == q->terminator;
238 * Get a completed packet with # descriptors. Return the first
239 * descriptor and pointer the head directly by lastAddr->nextAddr
241 static inline __inline struct dma_desc *dma_dequeue_bits(struct dma_queue *q,
244 struct dma_desc *desc = NULL;
246 if ((q->head->status & AR9170_OWN_BITS) == bits)
247 desc = dma_unlink_head(q);
252 static inline __inline struct dma_desc *dma_dequeue_not_bits(struct dma_queue *q,
255 struct dma_desc *desc = NULL;
257 /* AR9170_OWN_BITS_HW will be filtered out here too. */
258 if ((q->head->status & AR9170_OWN_BITS) != bits)
259 desc = dma_unlink_head(q);
264 #define for_each_desc_bits(desc, queue, bits) \
265 while ((desc = dma_dequeue_bits(queue, bits)))
267 #define for_each_desc_not_bits(desc, queue, bits) \
268 while ((desc = dma_dequeue_not_bits(queue, bits)))
270 #define for_each_desc(desc, queue) \
271 while ((desc = dma_unlink_head(queue)))
273 #define __for_each_desc_bits(desc, queue, bits) \
274 for (desc = (queue)->head; \
275 (desc != (queue)->terminator && \
276 (desc->status & AR9170_OWN_BITS) == bits); \
277 desc = desc->lastAddr->nextAddr)
279 #define __while_desc_bits(desc, queue, bits) \
280 for (desc = (queue)->head; \
281 (!queue_empty(queue) && \
282 (desc->status & AR9170_OWN_BITS) == bits); \
283 desc = (queue)->head)
285 #define __for_each_desc_continue(desc, queue) \
286 for (;desc != (queue)->terminator; \
287 desc = (desc)->lastAddr->nextAddr)
289 #define __for_each_desc(desc, queue) \
290 for (desc = (queue)->head; \
291 desc != (queue)->terminator; \
292 desc = (desc)->lastAddr->nextAddr)
294 #define __for_each_desc_safe(desc, tmp, queue) \
295 for (desc = (queue)->head, tmp = desc->lastAddr->nextAddr; \
296 desc != (queue)->terminator; \
297 desc = tmp, tmp = tmp->lastAddr->nextAddr)
299 #define __while_subdesc(desc, queue) \
300 for (desc = (queue)->head; \
301 desc != (queue)->terminator; \
302 desc = (desc)->nextAddr)
304 static inline __inline unsigned int queue_len(struct dma_queue *q)
306 struct dma_desc *desc;
309 __while_subdesc(desc, q)
316 * rearm a completed packet, so it will be processed agian.
318 static inline __inline void dma_rearm(struct dma_desc *desc)
320 /* Set OWN bit to HW */
321 desc->status = ((desc->status & (~AR9170_OWN_BITS)) |
325 static inline __inline void dma_fix_downqueue(struct dma_desc *desc)
327 desc->status = AR9170_OWN_BITS_HW;
330 desc->totalLen = AR9170_BLOCK_SIZE;
331 desc->lastAddr = desc;
334 static inline void __check_desc(void)
336 struct ar9170_dma_memory mem;
337 BUILD_BUG_ON(sizeof(struct ar9170_data_block) != AR9170_BLOCK_SIZE);
338 BUILD_BUG_ON(sizeof(struct dma_desc) != 20);
340 BUILD_BUG_ON(sizeof(mem) > AR9170_SRAM_SIZE);
342 BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, ba.buf) & (BLOCK_ALIGNMENT - 1));
343 BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, cmd.buf) & (BLOCK_ALIGNMENT - 1));
344 BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, rsp.buf) & (BLOCK_ALIGNMENT - 1));
345 BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, bcn.buf) & (BLOCK_ALIGNMENT - 1));
346 BUILD_BUG_ON(sizeof(struct carl9170_tx_null_superframe) > CARL9170_MAX_CMD_LEN);
349 #endif /* __CARL9170FW_DMA_H */