carl9170 firmware: fix clock_set parameter mixup
authorChristian Lamparter <chunkeey@googlemail.com>
Thu, 30 Jun 2011 00:27:29 +0000 (02:27 +0200)
committerChristian Lamparter <chunkeey@googlemail.com>
Thu, 30 Jun 2011 00:53:43 +0000 (02:53 +0200)
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
carlfw/src/rf.c
carlfw/usb/main.c

index 10220481d3e8514e04c1ab1010dd73a81ae87538..ae9fd5464e4fcb6f59150c1f34e22dda95e30b4d 100644 (file)
@@ -243,7 +243,7 @@ void rf_psm(void)
                /* Synthesizer off + RX off */
                bank3 = 0x00400018;
 
-               clock_set(true, AHB_20_22MHZ);
+               clock_set(AHB_20_22MHZ, false);
        } else {
                /* advance to the next PSM step */
                fw.phy.psm.state--;
@@ -261,9 +261,9 @@ void rf_psm(void)
                        bank3 = 0x01420098;
 
                        if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
-                               clock_set(true, AHB_80_88MHZ);
+                               clock_set(AHB_80_88MHZ, true);
                        else
-                               clock_set(true, AHB_40_44MHZ);
+                               clock_set(AHB_40_44MHZ, true);
                } else {
                        return ;
                }
index 649dc4bd9f797ce8d92671aac5b763ff816ebb14..cdaf760cdf285605e3575bc6803bbc5b649796e4 100644 (file)
@@ -245,7 +245,7 @@ static void turn_power_off(void)
                                  AR9170_PWR_RESET_WLAN_MASK);
        set(AR9170_PWR_REG_RESET, 0x0);
 
-       set(AR9170_PWR_REG_CLOCK_SEL, AHB_40MHZ_OSC);
+       clock_set(AHB_20_22MHZ, false);
 
        set(AR9170_PWR_REG_PLL_ADDAC, 0x5163);  /* 0x502b; */
        set(AR9170_PHY_REG_ADC_SERIAL_CTL, AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO);