2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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38 #include <adf_os_types.h>
43 #define GMAC_MAX_PKT_LEN 1600
44 #define GMAC_MAX_DESC 5
46 #define GMAC_DISCV_PKT_SZ 1024
47 #define GMAC_DISCV_WAIT 2000
49 #define ATH_P_MAGBOOT 0x12 /*Magpie GMAC 18 for boot downloader*/
50 #define ATH_P_MAGNORM 0x13 /*Magpie GMAC 19 for HTC & others*/
52 #define ETH_P_ATH 0x88bd
54 typedef enum hif_gmac_pipe{
55 HIF_GMAC_PIPE_RX = 1, /*Normal Priority RX*/
56 HIF_GMAC_PIPE_TX = 2, /*Normal Priority TX*/
60 void (*gmac_boot_init)(void);
63 void cmnos_gmac_module_install(struct gmac_api *boot_apis);
64 void hif_gmac_module_install(struct hif_api *apis);
66 enum __gmac_mii_mode {
75 GMAC_HST_QUERY = 0x0001,
76 GMAC_HST_REPLY = 0x0002,
77 GMAC_TGT_QUERY = 0x0003,
78 GMAC_TGT_REPLY = 0x0004
82 MAG_REG_GPIO_OE = 0x00052000,/*GPIO Output Enable*/
83 MAG_REG_RST = 0x00050010,/*Magpie reset reg*/
84 MAG_REG_RST_AHB = 0x00050018,/*Magpie AHB_ARB reset reg*/
85 MAG_REG_MII0_CTRL = 0x00054100,/*Magpie MII0 Control reg*/
86 MAG_REG_STAT_CTRL = 0x00054104,/*Magpie Status reg*/
88 MAG_REG_ETH_PLL = 0x5600c,
89 MAG_REG_ETHPLL_BYPASS = 0x56010,
93 GMAC_REG_BASE = 0x00060000,
94 GMAC_REG_MAC_CFG1 = 0x00 + GMAC_REG_BASE,/*MAC config 1*/
95 GMAC_REG_MAC_CFG2 = 0x04 + GMAC_REG_BASE,/*MAC config 2*/
96 GMAC_REG_IPG_IFG = 0x08 + GMAC_REG_BASE,/*Inter-packet-gap*/
97 GMAC_REG_HALF_DPLX = 0x0c + GMAC_REG_BASE,/*Half duplex*/
98 GMAC_REG_MAX_FRAME = 0x10 + GMAC_REG_BASE,/*Max frame length*/
99 GMAC_REG_MII_CFG = 0x20 + GMAC_REG_BASE,/*MII mgmt config*/
100 GMAC_REG_MII_CMD = 0x24 + GMAC_REG_BASE,/*MII mgmt command*/
101 GMAC_REG_MII_ADDR = 0x28 + GMAC_REG_BASE,/*MII mgmt address*/
102 GMAC_REG_MII_CTRL = 0x2c + GMAC_REG_BASE,/*MII mgmt control*/
103 GMAC_REG_MII_STAT = 0x30 + GMAC_REG_BASE,/*MII mgmt status*/
104 GMAC_REG_MII_PSTAT = 0x34 + GMAC_REG_BASE,/*MII mgmt Phy status/ind*/
105 GMAC_REG_IF_CTRL = 0x38 + GMAC_REG_BASE,/*Interface control*/
106 GMAC_REG_IF_STAT = 0x3c + GMAC_REG_BASE,/*Interface status*/
107 GMAC_REG_MAC_ADDR1 = 0x40 + GMAC_REG_BASE,/*MAC address 1*/
108 GMAC_REG_MAC_ADDR2 = 0x44 + GMAC_REG_BASE,/*MAC address 2*/
109 GMAC_REG_FIFO_CFG0 = 0x48 + GMAC_REG_BASE,/*FIFO config reg0*/
110 GMAC_REG_FIFO_CFG1 = 0x4c + GMAC_REG_BASE,/*FIFO config reg1*/
111 GMAC_REG_FIFO_CFG2 = 0x50 + GMAC_REG_BASE,/*FIFO config reg2*/
112 GMAC_REG_FIFO_CFG3 = 0x54 + GMAC_REG_BASE,/*FIFO config reg3*/
113 GMAC_REG_FIFO_CFG4 = 0x58 + GMAC_REG_BASE,/*FIFO config reg4*/
114 GMAC_REG_FIFO_CFG5 = 0x5c + GMAC_REG_BASE,/*FIFO config reg5*/
115 GMAC_REG_FIFO_RAM0 = 0x60 + GMAC_REG_BASE,/*FIFO RAM access reg0*/
116 GMAC_REG_FIFO_RAM1 = 0x64 + GMAC_REG_BASE,/*FIFO RAM access reg1*/
117 GMAC_REG_FIFO_RAM2 = 0x68 + GMAC_REG_BASE,/*FIFO RAM access reg2*/
118 GMAC_REG_FIFO_RAM3 = 0x6c + GMAC_REG_BASE,/*FIFO RAM access reg3*/
119 GMAC_REG_FIFO_RAM4 = 0x70 + GMAC_REG_BASE,/*FIFO RAM access reg4*/
120 GMAC_REG_FIFO_RAM5 = 0x74 + GMAC_REG_BASE,/*FIFO RAM access reg5*/
121 GMAC_REG_FIFO_RAM6 = 0x78 + GMAC_REG_BASE,/*FIFO RAM access reg6*/
122 GMAC_REG_FIFO_RAM7 = 0x7c + GMAC_REG_BASE,/*FIFO RAM access reg7*/
126 RST_GMAC = (1 << 9),/*Reset the GMAC */
127 RST_MII = (3 << 11),/*Reset the MII*/
128 RST_OTHERS = 0x5df,/*Reset everybody other than GMAC & MII*/
131 enum __mag_reg_rst_ahb{
134 enum __mag_mii0_ctrl_mode{
135 MII0_CTRL_MODE_GMII = 0x00, /* GMII*/
136 MII0_CTRL_MODE_MII = 0x01, /*MII*/
137 MII0_CTRL_MODE_RGMII = 0x02,/* RGMII */
138 MII0_CTRL_MODE_RMII = 0x03, /* RMII */
139 MII0_CTRL_MASTER_MODE = 0x04 /* master mode */
141 enum __mag_mii0_ctrl_speed {
142 MII0_CTLR_SPEED_10 = 0x00, /* 10 mbps*/
143 MII0_CTRL_SPEED_100 = 0x10, /*MII control address 100 Mbps*/
144 MII0_CTRL_SPEED_1000 = 0x20 /* 1000 */
148 enum __gmac_reg_mac_cfg1{
149 MAC_CFG1_TX_EN = (1 << 0),/*TX enable*/
150 MAC_CFG1_RX_EN = (1 << 2),/*RX enable*/
151 MAC_CFG1_TX_FLOW = (1 << 4),/*TX Flow control enable*/
152 MAC_CFG1_RX_FLOW = (1 << 5),/*RX Flow control enable*/
153 MAC_CFG1_LOOP_EN = (1 << 8),/*Enable loopback*/
155 enum __gmac_reg_mac_cfg2{
156 MAC_CFG2_FULL_DUP = (1 << 0),/*Enable Full Duplex*/
157 MAC_CFG2_PAD_CRC = (1 << 2),/*Enable MAC based CRC insertion*/
158 MAC_CFG2_CHK_LEN = (1 << 4),/*Check Length field*/
159 MAC_CFG2_HUGE_FRM = (1 << 5),/*Allow sending huge frames*/
160 MAC_CFG2_MII = (1 << 8),/*MAC is MII in mode*/
161 MAC_CFG2_GMII = (1 << 9),/*MAC is in GMII mode*/
162 MAC_CFG2_PREAMBLE = (7 << 12),/*Default Preamble Length*/
164 enum __gmac_reg_mii_cfg{
165 MII_CFG_CLK_2MHZ = 0x0006,/*Clock is 2Mhz*/
169 /* following are only for F1 phy on emulation board.*/
170 enum __gmac_reg_mii_addr{
171 MII_ADDR_RESET = 0x000,/*Flush the MII address register*/
172 MII_ADDR_STATS = 0x001,/* Stauts register*/
173 MII_ADDR_PHY_IDENT_1 = 0x002,/* phy identifier [18:3]*/
174 MII_ADDR_PHY_IDENT_2 = 0x003,/* phy identifier [19:24]*/
175 MII_ADDR_AUTONEG_ADV = 0x004,/* Autonegotiaion advertise*/
176 MII_ADDR_LINKPART_ABILITY = 0x0005,/* link partner ability*/
177 MII_ADDR_AUTONEG_EXP = 0x0006,/* Autonegotiation expansion*/
178 MII_ADDR_NEXTPG_TX = 0x0007,/* Next page transmit*/
179 MII_ADDR_LINKPART_NEXTPG = 0x0008,/* Link partnet next page*/
180 MII_ADDR_1000BASET_CNTRL = 0x0009,/* 1000 base-t control*/
181 MII_ADDR_1000BSAET_STATUS = 0x000a,/* 1000 base-t status*/
182 MII_ADDR_EXTENDED_STATUS = 0x000f,/* extended status*/
183 MII_ADDR_FUNCTION_CTRL = 0x0010,/* function control*/
184 MII_ADDR_PHY_REG = 0x0011,/*Phy Status Reg*/
185 MII_ADDR_INTERRUPT_ENA = 0x0012,/* interrupt enable*/
186 MII_ADDR_INTERRUPT_STATUS = 0x0013,/* interrupt status*/
187 MII_ADDR_EXTPHY_CTRL = 0x0014,/* extemded phy specific control*/
188 MII_ADDR_CABDET_CTRL = 0x0016,/* cable detect testser control*/
189 MII_ADDR_LED_CTRL = 0x0018,/* LED control*/
190 MII_ADDR_MANLED_OVER = 0x0019,/* Manual LED override*/
191 MII_ADDR_CABDET_STAT = 0x001c,/* cable detect tester status*/
192 MII_ADDR_DEBUGPORT_OFF = 0x001d,/* Debug port address offset*/
193 MII_ADDR_DEBUGPORT_DATA = 0x001e,/* Debug port data */
196 /* definitions for MII_ADDR_RESET register definitions*/
197 #define MII_ADDR_RESET_RESTART_AUTONEG (1 << 9)
198 #define MII_ADDR_RESET_ENABLE_AUTONEG (1 << 12)
199 #define MII_ADDR_RESET_ENABLE_LOOPBACK (1<<14)
200 #define MII_ADDR_RESET_SOFT_RESET (1<<15)
201 /* flags for autonegotiaion register MII_ADDR_AUTONEG_ADV,
202 All writes to this register should be followed by a soft
204 The list is not exhaustive, only required fields added
206 #define MII_AUTONEG_10BT_HALF (1<<5)
207 #define MII_AUTONEG_10BT_FULL (1<<6)
208 #define MII_AUTONEG_100BT_HALF (1<<7)
209 #define MII_AUTONEG_100BT_FULL (1<<8)
210 #define MII_AUTONEG_PAUSE (1<<9)
211 #define MII_1000BASET_1000BT_HALF (1<<8)
212 #define MII_1000BASET_1000BT_FULL (1<<9)
213 enum __gmac_reg_mii_ctrl{
214 MII_CTRL_FULL_DPLX = 0x0100,/*Full Duplex mode*/
215 MII_CTRL_SPEED_100 = 0x2000,/*Link Speed 100 Mbps*/
216 MII_CTRL_LOOPBACK = 0x4000,/*Enable Loopback mode at PHY*/
217 MII_CTRL_RESET = 0x8000,/*BMCR reset*/
219 enum __gma_reg_mii_cmd{
221 MII_CMD_READ = 0x1,/*Perform a Read cycle*/
223 enum __gmac_reg_fifo_cfg0{
224 FIFO_CFG0_EN = 0x1f00,/*Enable all the Fifo module*/
226 enum __gmac_reg_fifo_cfg1{
227 FIFO_CFG1_SIZE_2K = (0x7ff << 16),/*Fifo size is 2K*/
229 enum __gmac_reg_fifo_cfg4{
230 FIFO_CFG4_RX_ALL = 0x3ffff,/*receive all frames*/
232 enum __gmac_reg_if_ctrl{
233 IF_CTRL_SPEED_100 = (1 << 16),/*Interface speed 100 Mbps for MII*/
237 #define MAX_MDIO_IO_LEN 14
238 #define MDIO_REG_WIDTH 4
239 #define MDIO_REG_BASE 0x54200
240 #define MDIO_REG_TO_OFFSET( __reg_number__)\
241 (MDIO_REG_BASE + (MDIO_REG_WIDTH * (__reg_number__)))
243 #define MDIO_OWN_TGT 0x01
244 #define MDIO_OWN_HST 0x02
245 #define MDIO_REG_WRITE_DELAY 5 /* 5 micro seconds */
247 /*************************GMAC Data types*******************************/
248 typedef enum __gmac_pkt_type{
254 unsigned char dst[ETH_ALEN];/*destination eth addr */
255 unsigned char src[ETH_ALEN]; /*source ether addr*/
256 A_UINT16 etype;/*ether type*/
257 }__attribute__((packed));
259 * @brief this is will be in big endian format
271 }__attribute__((packed));
273 typedef struct __gmac_hdr{
276 A_UINT16 align_pad;/*pad it for 4 byte boundary*/
277 }__attribute__((packed)) __gmac_hdr_t;
279 /*********************************GMAC softC************************/
281 typedef struct __gmac_softc{