2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
3 * processor CORE configuration
5 * See <xtensa/config/core.h>, which includes this file, for more details.
9 * Xtensa processor core configuration information.
11 * Customer ID=4748; Build=0x2230f; Copyright (c) 1999-2008 by Tensilica Inc. ALL RIGHTS RESERVED.
12 * These coded instructions, statements, and computer programs are the
13 * copyrighted works and confidential proprietary information of Tensilica Inc.
14 * They may not be modified, copied, reproduced, distributed, or disclosed to
15 * third parties in any manner, medium, or form, in whole or in part, without
16 * the prior written consent of Tensilica Inc.
19 #ifndef _XTENSA_CORE_CONFIGURATION_H
20 #define _XTENSA_CORE_CONFIGURATION_H
23 /****************************************************************************
24 Parameters Useful for Any Code, USER or PRIVILEGED
25 ****************************************************************************/
28 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
29 * configured, and a value of 0 otherwise. These macros are always defined.
33 /*----------------------------------------------------------------------
35 ----------------------------------------------------------------------*/
37 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
38 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
39 #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
40 #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
41 #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
42 #define XCHAL_HAVE_DEBUG 1 /* debug option */
43 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
44 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
45 #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
46 #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
47 #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
48 #define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */
49 #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
50 #define XCHAL_HAVE_MUL32 1 /* MULL instruction */
51 #define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
52 #define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
53 #define XCHAL_HAVE_L32R 1 /* L32R instruction */
54 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
55 #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
56 #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
57 #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
58 #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
59 #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
60 #define XCHAL_HAVE_ABS 1 /* ABS instruction */
61 /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
62 /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
63 #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
64 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
65 #define XCHAL_HAVE_SPECULATION 0 /* speculation */
66 #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
67 #define XCHAL_NUM_CONTEXTS 1 /* */
68 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
69 #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
70 #define XCHAL_HAVE_PRID 1 /* processor ID register */
71 #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
72 #define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
73 #define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
74 #define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */
75 #define XCHAL_HAVE_MAC16 0 /* MAC16 package */
76 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
77 #define XCHAL_HAVE_FP 0 /* floating point pkg */
78 #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
79 #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
80 #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
83 /*----------------------------------------------------------------------
85 ----------------------------------------------------------------------*/
87 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
88 #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
89 #define XCHAL_DATA_WIDTH 4 /* data width in bytes */
90 /* In T1050, applies to selected core load and store instructions (see ISA): */
91 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
92 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
94 #define XCHAL_CORE_ID "Magpie_P0" /* alphanum core name
95 (CoreID) set in the Xtensa
96 Processor Generator */
98 #define XCHAL_BUILD_UNIQUE_ID 0x0002230F /* 22-bit sw build ID */
101 * These definitions describe the hardware targeted by this software.
103 #define XCHAL_HW_CONFIGID0 0xC280DBFF /* ConfigID hi 32 bits*/
104 #define XCHAL_HW_CONFIGID1 0x0D02230F /* ConfigID lo 32 bits*/
105 #define XCHAL_HW_VERSION_NAME "LX2.1.0" /* full version name */
106 #define XCHAL_HW_VERSION_MAJOR 2210 /* major ver# of targeted hw */
107 #define XCHAL_HW_VERSION_MINOR 0 /* minor ver# of targeted hw */
108 #define XCHAL_HW_VERSION 221000 /* major*100+minor */
109 #define XCHAL_HW_REL_LX2 1
110 #define XCHAL_HW_REL_LX2_1 1
111 #define XCHAL_HW_REL_LX2_1_0 1
112 #define XCHAL_HW_CONFIGID_RELIABLE 1
113 /* If software targets a *range* of hardware versions, these are the bounds: */
114 #define XCHAL_HW_MIN_VERSION_MAJOR 2210 /* major v of earliest tgt hw */
115 #define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */
116 #define XCHAL_HW_MIN_VERSION 221000 /* earliest targeted hw */
117 #define XCHAL_HW_MAX_VERSION_MAJOR 2210 /* major v of latest tgt hw */
118 #define XCHAL_HW_MAX_VERSION_MINOR 0 /* minor v of latest tgt hw */
119 #define XCHAL_HW_MAX_VERSION 221000 /* latest targeted hw */
122 /*----------------------------------------------------------------------
124 ----------------------------------------------------------------------*/
126 #define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */
127 #define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */
128 #define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */
129 #define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */
131 #define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
132 #define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
134 #define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
139 /****************************************************************************
140 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
141 ****************************************************************************/
144 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
146 /*----------------------------------------------------------------------
148 ----------------------------------------------------------------------*/
150 #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
152 /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
154 /* Number of cache sets in log2(lines per way): */
155 #define XCHAL_ICACHE_SETWIDTH 0
156 #define XCHAL_DCACHE_SETWIDTH 0
158 /* Cache set associativity (number of ways): */
159 #define XCHAL_ICACHE_WAYS 1
160 #define XCHAL_DCACHE_WAYS 1
162 /* Cache features: */
163 #define XCHAL_ICACHE_LINE_LOCKABLE 0
164 #define XCHAL_DCACHE_LINE_LOCKABLE 0
165 #define XCHAL_ICACHE_ECC_PARITY 0
166 #define XCHAL_DCACHE_ECC_PARITY 0
168 /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
169 #define XCHAL_CA_BITS 4
172 /*----------------------------------------------------------------------
173 INTERNAL I/D RAM/ROMs and XLMI
174 ----------------------------------------------------------------------*/
176 #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
177 #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
178 #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
179 #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
180 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
181 #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
183 /* Instruction RAM 0: */
184 #define XCHAL_INSTRAM0_VADDR 0x00800000
185 #define XCHAL_INSTRAM0_PADDR 0x00800000
186 #define XCHAL_INSTRAM0_SIZE 4194304
187 #define XCHAL_INSTRAM0_ECC_PARITY 0
190 #define XCHAL_DATARAM0_VADDR 0x00400000
191 #define XCHAL_DATARAM0_PADDR 0x00400000
192 #define XCHAL_DATARAM0_SIZE 4194304
193 #define XCHAL_DATARAM0_ECC_PARITY 0
196 /*----------------------------------------------------------------------
197 INTERRUPTS and TIMERS
198 ----------------------------------------------------------------------*/
200 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
201 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
202 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
203 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
204 #define XCHAL_NUM_TIMERS 1 /* number of CCOMPAREn regs */
205 #define XCHAL_NUM_INTERRUPTS 19 /* number of interrupts */
206 #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
207 #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
208 #define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels
209 (not including level zero) */
210 #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
211 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
213 /* Masks of interrupts at each interrupt level: */
214 #define XCHAL_INTLEVEL1_MASK 0x00000001
215 #define XCHAL_INTLEVEL2_MASK 0x00007FFE
216 #define XCHAL_INTLEVEL3_MASK 0x00038000
217 #define XCHAL_INTLEVEL4_MASK 0x00000000
218 #define XCHAL_INTLEVEL5_MASK 0x00040000
219 #define XCHAL_INTLEVEL6_MASK 0x00000000
220 #define XCHAL_INTLEVEL7_MASK 0x00000000
222 /* Masks of interrupts at each range 1..n of interrupt levels: */
223 #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00000001
224 #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00007FFF
225 #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x0003FFFF
226 #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x0003FFFF
227 #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x0007FFFF
228 #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x0007FFFF
229 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x0007FFFF
231 /* Level of each interrupt: */
232 #define XCHAL_INT0_LEVEL 1
233 #define XCHAL_INT1_LEVEL 2
234 #define XCHAL_INT2_LEVEL 2
235 #define XCHAL_INT3_LEVEL 2
236 #define XCHAL_INT4_LEVEL 2
237 #define XCHAL_INT5_LEVEL 2
238 #define XCHAL_INT6_LEVEL 2
239 #define XCHAL_INT7_LEVEL 2
240 #define XCHAL_INT8_LEVEL 2
241 #define XCHAL_INT9_LEVEL 2
242 #define XCHAL_INT10_LEVEL 2
243 #define XCHAL_INT11_LEVEL 2
244 #define XCHAL_INT12_LEVEL 2
245 #define XCHAL_INT13_LEVEL 2
246 #define XCHAL_INT14_LEVEL 2
247 #define XCHAL_INT15_LEVEL 3
248 #define XCHAL_INT16_LEVEL 3
249 #define XCHAL_INT17_LEVEL 3
250 #define XCHAL_INT18_LEVEL 5
251 #define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
252 #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
253 #define XCHAL_NMILEVEL 5 /* NMI "level" (for use with
254 EXCSAVE/EPS/EPC_n, RFI n) */
256 /* Type of each interrupt: */
257 #define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE
258 #define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER
259 #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
260 #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
261 #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
262 #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
263 #define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
264 #define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
265 #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
266 #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
267 #define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
268 #define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
269 #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
270 #define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
271 #define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
272 #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
273 #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
274 #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
275 #define XCHAL_INT18_TYPE XTHAL_INTTYPE_NMI
277 /* Masks of interrupts for each type of interrupt: */
278 #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFF80000
279 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000001
280 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
281 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0003FFFC
282 #define XCHAL_INTTYPE_MASK_TIMER 0x00000002
283 #define XCHAL_INTTYPE_MASK_NMI 0x00040000
284 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
286 /* Interrupt numbers assigned to specific interrupt sources: */
287 #define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */
288 #define XCHAL_TIMER1_INTERRUPT XTHAL_TIMER_UNCONFIGURED
289 #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
290 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
291 #define XCHAL_NMI_INTERRUPT 18 /* non-maskable interrupt */
293 /* Interrupt numbers for levels at which only one interrupt is configured: */
294 #define XCHAL_INTLEVEL1_NUM 0
295 #define XCHAL_INTLEVEL5_NUM 18
296 /* (There are many interrupts each at level(s) 2, 3.) */
300 * External interrupt vectors/levels.
301 * These macros describe how Xtensa processor interrupt numbers
302 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
303 * map to external BInterrupt<n> pins, for those interrupts
304 * configured as external (level-triggered, edge-triggered, or NMI).
305 * See the Xtensa processor databook for more details.
308 /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
309 #define XCHAL_EXTINT0_NUM 2 /* (intlevel 2) */
310 #define XCHAL_EXTINT1_NUM 3 /* (intlevel 2) */
311 #define XCHAL_EXTINT2_NUM 4 /* (intlevel 2) */
312 #define XCHAL_EXTINT3_NUM 5 /* (intlevel 2) */
313 #define XCHAL_EXTINT4_NUM 6 /* (intlevel 2) */
314 #define XCHAL_EXTINT5_NUM 7 /* (intlevel 2) */
315 #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
316 #define XCHAL_EXTINT7_NUM 9 /* (intlevel 2) */
317 #define XCHAL_EXTINT8_NUM 10 /* (intlevel 2) */
318 #define XCHAL_EXTINT9_NUM 11 /* (intlevel 2) */
319 #define XCHAL_EXTINT10_NUM 12 /* (intlevel 2) */
320 #define XCHAL_EXTINT11_NUM 13 /* (intlevel 2) */
321 #define XCHAL_EXTINT12_NUM 14 /* (intlevel 2) */
322 #define XCHAL_EXTINT13_NUM 15 /* (intlevel 3) */
323 #define XCHAL_EXTINT14_NUM 16 /* (intlevel 3) */
324 #define XCHAL_EXTINT15_NUM 17 /* (intlevel 3) */
325 #define XCHAL_EXTINT16_NUM 18 /* (intlevel 5) */
328 /*----------------------------------------------------------------------
329 EXCEPTIONS and VECTORS
330 ----------------------------------------------------------------------*/
332 #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
333 number: 1 == XEA1 (old)
335 0 == XEAX (extern) */
336 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
337 #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
338 #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
339 #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
340 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
341 #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
342 #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
343 #define XCHAL_VECBASE_RESET_VADDR 0x008E0800 /* VECBASE reset value */
344 #define XCHAL_VECBASE_RESET_PADDR 0x008E0800
345 #define XCHAL_RESET_VECBASE_OVERLAP 0
347 #define XCHAL_RESET_VECTOR0_VADDR 0x008E0000
348 #define XCHAL_RESET_VECTOR0_PADDR 0x008E0000
349 #define XCHAL_RESET_VECTOR1_VADDR 0x0F000000
350 #define XCHAL_RESET_VECTOR1_PADDR 0x0F000000
351 #define XCHAL_RESET_VECTOR_VADDR 0x008E0000
352 #define XCHAL_RESET_VECTOR_PADDR 0x008E0000
353 #define XCHAL_USER_VECOFS 0x00000620
354 #define XCHAL_USER_VECTOR_VADDR 0x008E0E20
355 #define XCHAL_USER_VECTOR_PADDR 0x008E0E20
356 #define XCHAL_KERNEL_VECOFS 0x00000540
357 #define XCHAL_KERNEL_VECTOR_VADDR 0x008E0D40
358 #define XCHAL_KERNEL_VECTOR_PADDR 0x008E0D40
359 #define XCHAL_DOUBLEEXC_VECOFS 0x00000720
360 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x008E0F20
361 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x008E0F20
362 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000
363 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040
364 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080
365 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
366 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100
367 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140
368 #define XCHAL_WINDOW_VECTORS_VADDR 0x008E0800
369 #define XCHAL_WINDOW_VECTORS_PADDR 0x008E0800
370 #define XCHAL_INTLEVEL2_VECOFS 0x00000220
371 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x008E0A20
372 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x008E0A20
373 #define XCHAL_INTLEVEL3_VECOFS 0x00000320
374 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x008E0B20
375 #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x008E0B20
376 #define XCHAL_INTLEVEL4_VECOFS 0x00000420
377 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x008E0C20
378 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x008E0C20
379 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS
380 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
381 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
382 #define XCHAL_NMI_VECOFS 0x000004E4
383 #define XCHAL_NMI_VECTOR_VADDR 0x008E0CE4
384 #define XCHAL_NMI_VECTOR_PADDR 0x008E0CE4
385 #define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS
386 #define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
387 #define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
390 /*----------------------------------------------------------------------
392 ----------------------------------------------------------------------*/
394 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
395 #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
396 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
397 #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
400 /*----------------------------------------------------------------------
402 ----------------------------------------------------------------------*/
404 /* See core-matmap.h header file for more details. */
406 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
407 #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
408 #define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
409 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
410 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
411 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
412 #define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
413 [autorefill] and protection)
414 usable for an MMU-based OS */
415 /* If none of the above last 4 are set, it's a custom TLB configuration. */
417 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
418 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
419 #define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
421 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
424 #endif /* _XTENSA_CORE_CONFIGURATION_H */