1 /* This is a bcm43xx microcode assembly example.
4 * GPRs: r0 - r63 (General Purpose Register)
5 * Offset Registers: off0 - off5
6 * SPRs: spr000 (Special Purpose Register)
8 * SPRs map to the driver-side IHR registers.
9 * An SPR offset is converted to an IHR offset by the following
10 * calculation: IHR = (SPR + 0x400) * 2
12 * To access memory, two methods can be used. Examples follow.
15 * Indirect through Offset Register (pointer):
20 /* The target architecture. Supported versions are 5 and 15 */
23 /* Program entry point */
26 #define PSM_BRC spr848
28 #define ECOND_MAC_ON (0x20 | 4)
30 %assert ((((1))) == ((((2 - 1) & 0xFF))))
31 %assert ((1 == 2) || (1 == (0xFF & 1)))
33 %assert ((1 == (2 - 1)) && (2 == 2))
37 /* Inline assertion inside of a complex immediate.
38 * The %assert() expression will always return zero. */
39 mov (1 + (%assert(1 == ((1 + 2) - 2)))), r0
42 /* ADD instructions */
43 add r0,r1,r2 /* add */
44 add. r0,r1,r2 /* add, set carry */
45 addc r0,r1,r2 /* add with carry */
46 addc. r0,r1,r2 /* add with carry, set carry */
49 /* SUB instructions */
50 sub r0,r1,r2 /* sub */
51 sub. r0,r1,r2 /* sub, set carry */
52 subc r0,r1,r2 /* sub with carry */
53 subc. r0,r1,r2 /* sub with carry, set carry */
55 sra r0,r1,r2 /* arithmetic rightshift */
57 /* Logical instructions */
58 or r0,r1,r2 /* bitwise OR */
59 and r0,r1,r2 /* bitwise AND */
60 xor r0,r1,r2 /* bitwise XOR */
61 sr r0,r1,r2 /* rightshift */
62 sl r0,r1,r2 /* leftshift */
64 srx 7,8,r0,r1,r2 /* eXtended right shift (two input regs) */
66 rl r0,r1,r2 /* rotate left */
67 rr r0,r1,r2 /* rotate right */
68 nand r0,r1,r2 /* clear bits (notmask + and) */
70 orx 7,8,r0,r1,r2 /* eXtended OR */
72 /* Copy instruction. This is a virtual instruction
73 * translated to more lowlevel stuff like OR. */
74 mov r0,r2 /* copy data */
77 jmp label /* unconditional jump */
78 jand r0,r1,label /* jump if binary AND */
79 jnand r0,r1,label /* jump if not binary AND */
80 js r0,r1,label /* jump if all bits set */
81 jns r0,r1,label /* jump if not all bits set */
82 je r0,r1,label /* jump if equal */
83 jne r0,r1,label /* jump if not equal */
84 jls r0,r1,label /* jump if less (signed) */
85 jges r0,r1,label /* jump if greater or equal (signed) */
86 jgs r0,r1,label /* jump if greater (signed) */
87 jles r0,r1,label /* jump if less or equal (signed) */
88 jl r0,r1,label /* jump if less */
89 jge r0,r1,label /* jump if greater or equal */
90 jg r0,r1,label /* jump if greater */
91 jle r0,r1,label /* jump if less or equal */
93 jzx 7,8,r0,r1,label /* Jump if zero after shift and mask */
94 jnzx 7,8,r0,r1,label /* Jump if nonzero after shift and mask */
96 /* jump on external conditions */
97 jext ECOND_MAC_ON,label /* jump if external condition is TRUE */
98 jnext ECOND_MAC_ON,label /* jump if external condition is FALSE */
101 call lr0,label /* store PC in lr0, call func at label */
102 ret lr0,lr1 /* store PC in lr0, return to lr1
103 * Both link registers can be the same
104 * and don't interfere. */
106 /* TKIP sbox lookup */
107 tkiph r0,r2 /* Lookup high */
108 tkiphs r0,r2 /* Lookup high, byteswap */
109 tkipl r0,r2 /* Lookup low */
110 tkipls r0,r2 /* Lookup low, byteswap */
112 nap /* sleep until event */
114 /* raw instruction */
115 @160 r0,r1,r2 /* equivalent to or r0,r1,r2 */
116 @1C0 @C11, @C22, @BC3
119 /* Support for directional jumps.
120 * Directional jumps can be used to conveniently jump inside of
121 * functions without using function specific label prefixes. Note
122 * that this does not establish a sub-namespace, though. "loop"
123 * and "out" are still in the global namespace and can't be used
124 * anymore for absolute jumps (Assembler will warn about duplication).
145 /* The assembler has support for fancy assemble-time
146 * immediate constant expansion. This is called "complex immediates".
147 * Complex immediates are _always_ clamped by parentheses. There is no
148 * operator precedence. You must use parentheses to tell precedence.
160 mov (1 << (0x3 + 2)),r0
161 mov (1 + (2 + (3 + 4))),r0
162 mov (4 >> (((((~5 | 0x21)))) | (~((10) & 2)))),r0
165 /* Some regression testing for the assembler follows */
166 mov 2,off0 /* test memory stuff */
167 xor 0x124,r1,[0x0,off0] /* test memory stuff */
168 xor 0x124,r0,[0x0] /* test memory stuff */
169 mov -34,r0 /* negative dec numbers are supported */
170 or r0,r1,@BC2 /* We also support single raw operands */
171 mov 0xEEEE,r0 /* MOV supports up to 16bit */
172 jand 0x3800,r0,label /* This is emulated by jnzx */
173 jnand 0x3800,r0,label /* This is emulated by jzx */
174 or spr06c,0,spr06c /* Can have one spr input and one spr output */
175 or [0],0,[0] /* Can have one mem input and one mem output */
176 mov testlabel, r0 /* Can use label as immediate value */
177 mov r0,r1;mov r2, r3 /* ; does split instructions */
178 mov [(1+1)],[(2+2),off0] /* Can use complex immediates as memory offsets */
179 orx (0 + 1), (1 * 2), 0, 0, r0 /* Allow complex immediates as M or S */
182 /* The .initvals section generates an "Initial Values" file
183 * with the name "foobar" in this example, which is uploaded
184 * by the kernel driver on load. This is useful for writing ucode
185 * specific values to the chip without bloating the small ucode
186 * memory space with this initialization stuff.
187 * Values are written in order they appear here.
190 mmio16 0x1234, 0xABC /* Write 0x1234 to MMIO register 0xABC */
191 mmio32 0x12345678, 0xABC /* Write 0x12345678 to MMIO register 0xABC */
192 phy 0x1234, 0xABC /* Write 0x1234 to PHY register 0xABC */
193 radio 0x1234, 0xABC /* Write 0x1234 to RADIO register 0xABC */
194 shm16 0x1234, 0x0001, 0x0002 /* Write 0x1234 to SHM routing 0x0001, register 0x0002 */
195 shm32 0x12345678, 0x0001, 0x0002 /* Write 0x12345678 to SHM routing 0x0001, register 0x0002 */
196 tram 0x12345678, 0x1234 /* Write 0x12345678 to Template Ram offset 0x1234 */
199 // vim: syntax=b43 ts=8