#include <adf_net.h>
#include <adf_net_wcmd.h>
-#include "if_ethersubr.h"
#include "if_llc.h"
#ifdef USE_HEADERLEN_RESV
#include "if_athrate.h"
#include "if_athvar.h"
#include "ah_desc.h"
-#include "if_ath_pci.h"
+#include "ah_internal.h"
#define ath_tgt_free_skb adf_nbuf_free
ath_tx_update_baw(ath_atx_tid_t *tid, int seqno);
static void
ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
- ath_bufhead *bf_q, struct ath_tx_buf **bar);
+ ath_tx_bufhead *bf_q, struct ath_tx_buf **bar);
static void
ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_atx_tid_t *tid);
int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc,
struct ath_buf *bf,int datatype,
ath_atx_tid_t *tid, int is_burst);
+int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
+ ath_tx_bufhead *bf_q);
struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb)
{
static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
struct ath_tx_desc *ds0, *ds = bf->bf_desc;
+ struct ath_hal *ah = sc->sc_ah;
a_uint8_t i;
ds0 = ds;
} else
ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
- ath_hal_filltxdesc(sc->sc_ah, ds
+ ah->ah_fillTxDesc(ds
, bf->bf_dmamap_info.dma_segs[i].len
, i == 0
, i == (bf->bf_dmamap_info.nsegs - 1)
static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
- struct ath_desc *ds = bf->bf_desc;
+ struct ath_tx_desc *ds = bf->bf_desc;
+ struct ath_hal *ah = sc->sc_ah;
switch (bf->bf_protmode) {
case IEEE80211_PROT_RTSCTS:
break;
}
- ath_hal_set11n_txdesc(sc->sc_ah, ds
+ ah->ah_set11nTxDesc(ds
, bf->bf_pktlen
, bf->bf_atype
, 60
{
struct ath_hal *ah = sc->sc_ah;
const HAL_RATE_TABLE *rt;
- struct ath_desc *ds = bf->bf_desc;
+ struct ath_tx_desc *ds = bf->bf_desc;
HAL_11N_RATE_SERIES series[4];
a_int32_t i, flags;
a_uint8_t rix, cix, rtsctsrate;
- a_uint32_t ctsduration = 0;
a_int32_t prot_mode = AH_FALSE;
rt = sc->sc_currates;
cix = rt->info[sc->sc_protrix].controlRate;
prot_mode = AH_TRUE;
} else {
- if (ath_hal_htsupported(ah) && (!bf->bf_ismcast))
+ if (ath_hal_getcapability(ah, HAL_CAP_HT) && (!bf->bf_ismcast))
flags = HAL_TXDESC_RTSENA;
for (i = 4; i--;) {
rtsctsrate = rt->info[cix].rateCode |
(bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
- ath_hal_set11n_ratescenario(ah, ds, 1,
- rtsctsrate, ctsduration,
+ ah->ah_set11nRateScenario(ds, 1,
+ rtsctsrate,
series, 4,
flags);
}
if (txs == NULL)
return;
+ txs->txstatus[txs->cnt].ts_flags = 0;
+
txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
static void owltgt_tx_process_cabq(struct ath_softc_tgt *sc, struct ath_txq *txq)
{
- ath_hal_intrset(sc->sc_ah, sc->sc_imask & ~HAL_INT_SWBA);
+ struct ath_hal *ah = sc->sc_ah;
+ ah->ah_setInterrupts(ah, sc->sc_imask & ~HAL_INT_SWBA);
owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
- ath_hal_intrset(sc->sc_ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
}
void owl_tgt_tx_tasklet(TQUEUE_ARG data)
{
struct ath_tx_buf *bf;
struct ath_tx_desc *ds;
+ struct ath_hal *ah = sc->sc_ah;
HAL_STATUS status;
for (;;) {
bf = asf_tailq_first(&txq->axq_q);
ds = bf->bf_lastds;
- status = ath_hal_txprocdesc(sc->sc_ah, ds);
+ status = ah->ah_procTxDesc(ah, ds);
if (status == HAL_EINPROGRESS) {
if (txqstate == OWL_TXQ_ACTIVE)
txq = bf->bf_txq;
- status = ath_hal_txprocdesc(sc->sc_ah, bf->bf_lastds);
+ status = ah->ah_procTxDesc(ah, bf->bf_lastds);
ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
if (txq->axq_link == NULL) {
- ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
+ ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
} else {
*txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
- txe_val = OS_REG_READ(ah, 0x840);
+ txe_val = ioread32_mac(0x0840);
if (!(txe_val & (1<< txq->axq_qnum)))
- ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
+ ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
}
txq->axq_link = &bf->bf_lastds->ds_link;
- ath_hal_txstart(ah, txq->axq_qnum);
+ ah->ah_startTxDma(ah, txq->axq_qnum);
}
static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
void
ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
- struct ath_node_target *an = bf->bf_node;
+ struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
struct ath_rc_series rcs[4];
struct ath_rc_series mrcs[4];
a_int32_t shortPreamble = 0;
ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
a_int32_t i ;
- struct ath_desc *bfd = NULL;
+ struct ath_tx_desc *bfd = NULL;
+ struct ath_hal *ah = sc->sc_ah;
for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
- ath_hal_clr11n_aggr(sc->sc_ah, bfd);
- ath_hal_set11n_burstduration(sc->sc_ah, bfd, 0);
- ath_hal_set11n_virtualmorefrag(sc->sc_ah, bfd, 0);
+ ah->ah_clr11nAggr(bfd);
+ ah->ah_set11nBurstDuration(bfd, 0);
+ ah->ah_set11nVirtualMoreFrag(bfd, 0);
}
ath_dma_unmap(sc, bf);
struct ath_vap_target *avp;
struct ath_hal *ah = sc->sc_ah;
a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
- a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration;
+ a_uint32_t subtype, flags, ctsduration;
a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
- struct ath_desc *ds=NULL;
+ struct ath_tx_desc *ds=NULL;
struct ath_txq *txq=NULL;
struct ath_tx_buf *bf;
HAL_PKT_TYPE atype;
flags |= HAL_TXDESC_INTREQ;
- ath_hal_setuptxdesc(ah, ds
+ ah->ah_setupTxDesc(ds
, pktlen
, hdrlen
, atype
, 60
, txrate, try0
, keyix
- , 0
, flags
, ctsrate
- , ctsduration
- , icvlen
- , ivlen
- , ATH_COMP_PROC_NO_COMP_NO_CCS);
+ , ctsduration);
bf->bf_flags = flags;
* in Auth frame 3 of Shared Authentication, owl needs this.
*/
if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
- (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
- ath_hal_fillkeytxdesc(ah, ds, mh->keytype);
+ (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
+ ah->ah_fillKeyTxDesc(ds, mh->keytype);
ath_filltxdesc(sc, bf);
series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
series[i].RateFlags = 0;
}
- ath_hal_set11n_ratescenario(ah, ds, 0, ctsrate, ctsduration, series, 4, 0);
+ ah->ah_set11nRateScenario(ds, 0, ctsrate, series, 4, 0);
ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
return;
ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
if (txq->axq_link == NULL) {
- ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
+ ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
} else {
*txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
}
txq->axq_link = &lastds->ds_link;
- ath_hal_txstart(ah, txq->axq_qnum);
+ ah->ah_startTxDma(ah, txq->axq_qnum);
}
void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
static void
ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
{
- struct ath_buf *bf;
+ struct ath_tx_buf *bf;
struct ath_txq *txq =TID_TO_ACTXQ(tid->tidno);;
do {
{
struct ath_tx_buf *bf, *bf_last;
ATH_AGGR_STATUS status;
- ath_bufhead bf_q;
+ ath_tx_bufhead bf_q;
struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno);
- struct ath_desc *ds = NULL;
+ struct ath_tx_desc *ds = NULL;
+ struct ath_hal *ah = sc->sc_ah;
int i;
break;
bf = asf_tailq_first(&bf_q);
- bf_last = asf_tailq_last(&bf_q, ath_bufhead_s);
+ bf_last = asf_tailq_last(&bf_q, ath_tx_bufhead_s);
if (bf->bf_nframes == 1) {
bf->bf_next = NULL;
for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
- ath_hal_clr11n_aggr(sc->sc_ah, ds);
+ ah->ah_clr11nAggr(ds);
ath_buf_set_rate(sc, bf);
bf->bf_txq_add(sc, bf);
bf->bf_isaggr = 1;
ath_buf_set_rate(sc, bf);
- ath_hal_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al,
+ ah->ah_set11nAggrFirst(bf->bf_desc, bf->bf_al,
bf->bf_ndelim);
bf->bf_lastds = bf_last->bf_lastds;
for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
- ath_hal_set11n_aggr_last(sc->sc_ah, &bf_last->bf_descarr[i]);
+ ah->ah_set11nAggrLast(&bf_last->bf_descarr[i]);
if (status == ATH_AGGR_8K_LIMITED) {
adf_os_assert(0);
}
int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
- ath_bufhead *bf_q)
+ ath_tx_bufhead *bf_q)
{
struct ath_tx_buf *bf_first ,*bf_prev = NULL;
int nframes = 0, rl = 0;;
- struct ath_desc *ds = NULL;
+ struct ath_tx_desc *ds = NULL;
struct ath_tx_buf *bf;
+ struct ath_hal *ah = sc->sc_ah;
u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta;
u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
bf_prev = bf;
for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
- ath_hal_set11n_aggr_middle(sc->sc_ah, ds, bf->bf_ndelim);
+ ah->ah_set11nAggrMiddle(ds, bf->bf_ndelim);
} while (!asf_tailq_empty(&tid->buf_q));
int ba_index;
int nbad = 0;
int nframes = bf->bf_nframes;
- struct ath_buf *bf_next;
- ath_bufhead bf_q;
+ struct ath_tx_buf *bf_next;
+ ath_tx_bufhead bf_q;
int tx_ok = 1;
- struct ath_buf *bar = NULL;
+ struct ath_tx_buf *bar = NULL;
struct ath_txq *txq;
txq = bf->bf_txq;
struct ath_tx_desc lastds;
- struct ath_desc *ds = &lastds;
+ struct ath_tx_desc *ds = &lastds;
struct ath_rc_series rcs[4];
- struct ath_buf *bar = NULL;
- struct ath_buf *bf_next;
+ struct ath_tx_buf *bar = NULL;
+ struct ath_tx_buf *bf_next;
int nframes = bf->bf_nframes;
- ath_bufhead bf_q;
+ ath_tx_bufhead bf_q;
struct ath_txq *txq;
asf_tailq_init(&bf_q);
int ba_index;
int nbad = 0;
int nframes = bf->bf_nframes;
- struct ath_buf *bf_next;
+ struct ath_tx_buf *bf_next;
int tx_ok = 1;
adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
static void
ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
- ath_bufhead *bf_q, struct ath_tx_buf **bar)
+ ath_tx_bufhead *bf_q, struct ath_tx_buf **bar)
{
struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
- struct ath_desc *ds = NULL;
+ struct ath_tx_desc *ds = NULL;
+ struct ath_hal *ah = sc->sc_ah;
int i = 0;
__stats(sc, txaggr_compretries);
for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
- ath_hal_clr11n_aggr(sc->sc_ah, ds);
- ath_hal_set11n_burstduration(sc->sc_ah, ds, 0);
- ath_hal_set11n_virtualmorefrag(sc->sc_ah, ds, 0);
+ ah->ah_clr11nAggr(ds);
+ ah->ah_set11nBurstDuration(ds, 0);
+ ah->ah_set11nVirtualMoreFrag(ds, 0);
}
if (bf->bf_retries >= OWLMAX_RETRIES) {
{
struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
- struct ath_desc *ds = bf->bf_lastds;
+ struct ath_tx_desc *ds = bf->bf_lastds;
ath_update_stats(sc, bf);
ath_rate_tx_complete(sc, an, ds, bf->bf_rcs, 1, 0);
static void ath_bar_tx_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
{
- struct ath_desc *ds = bf->bf_lastds;
+ struct ath_tx_desc *ds = bf->bf_lastds;
struct ath_node_target *an;
ath_atx_tid_t *tid;
struct ath_txq *txq;
adf_nbuf_t skb;
struct ieee80211_frame_bar *bar;
u_int8_t min_rate;
- struct ath_desc *ds, *ds0;
+ struct ath_tx_desc *ds, *ds0;
+ struct ath_hal *ah = sc->sc_ah;
HAL_11N_RATE_SERIES series[4];
int i = 0;
adf_nbuf_queue_t skbhead;
__stats(sc, tx_bars);
- memset(&series, 0, sizeof(series));
+ adf_os_mem_set(&series, 0, sizeof(series));
ath_aggr_pause_tid(sc, tid);
adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
ds = bf->bf_desc;
- ath_hal_setuptxdesc(sc->sc_ah, ds
+ ah->ah_setupTxDesc(ds
, adf_nbuf_len(skb) + IEEE80211_CRC_LEN
, 0
, HAL_PKT_TYPE_NORMAL
, min_rate
, ATH_TXMAXTRY
, bf->bf_keyix
- , 0
, HAL_TXDESC_INTREQ
| HAL_TXDESC_CLRDMASK
- , 0, 0, 0, 0
- , ATH_COMP_PROC_NO_COMP_NO_CCS);
+ , 0, 0);
skbhead = bf->bf_skbhead;
bf->bf_isaggr = 0;
bf->bf_next = NULL;
for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
- ath_hal_clr11n_aggr(sc->sc_ah, ds0);
+ ah->ah_clr11nAggr(ds0);
}
ath_filltxdesc(sc, bf);
series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
}
- ath_hal_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 0, 0, 0, series, 4, 4);
+ ah->ah_set11nRateScenario(bf->bf_desc, 0, 0, series, 4, 4);
ath_tgt_txq_add_ucast(sc, bf);
}
projects / open-ath9k-htc-firmware.git / blobdiff