+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Qualcomm Atheros nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
#ifndef _DEV_ATH_ATHVAR_H
#define _DEV_ATH_ATHVAR_H
#define TARGET_NODE_MAX ATH_NODE_MAX
#define TARGET_VAP_MAX ATH_VAP_MAX
-#define ATH_NODE_TARGET(_n) ((struct ath_node *)(_n))
-
#define MAX_RATE_POWER 63
#define ATH_COMP_PROC_NO_COMP_NO_CCS 3
#define ath_free_rx_skb(_sc,_skb) BUF_Pool_free_buf(_sc->pool_handle, POOL_ID_WLAN_RX_BUF, _skb)
#define ath_free_tx_skb(_htc_handle, endpt, _skb) HTC_ReturnBuffers(_htc_handle, endpt, _skb);
-typedef void (*ath_txq_add_fn_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
-typedef void (*ath_tx_comp_fn_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
+struct ath_tx_buf;
+
+typedef void (*ath_txq_add_fn_t)(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
+typedef void (*ath_tx_comp_fn_t)(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
struct ath_buf_state {
ath_tx_comp_fn_t bfs_comp; /* completion function */
#define bf_retries bf_state.bfs_retries
#define ATH_GENERIC_BUF \
- asf_tailq_entry(ath_buf) bf_list; \
- struct ath_buf *bf_next; \
- struct ath_desc *bf_desc; \
- struct ath_desc *bf_descarr; \
adf_os_dma_map_t bf_dmamap; \
adf_os_dmamap_info_t bf_dmamap_info; \
struct ieee80211_node_target *bf_node; \
adf_nbuf_queue_t bf_skbhead; \
- adf_nbuf_t bf_skb; \
- struct ath_desc *bf_lastds;
+ adf_nbuf_t bf_skb;
struct ath_buf
{
ATH_GENERIC_BUF
+ asf_tailq_entry(ath_buf) bf_list;
+ struct ath_buf *bf_next;
+ struct ath_desc *bf_lastds;
+ struct ath_desc *bf_desc;
+ struct ath_desc *bf_descarr;
};
struct ath_tx_buf
{
ATH_GENERIC_BUF
+ asf_tailq_entry(ath_tx_buf) bf_list;
+ struct ath_tx_buf *bf_next;
+ struct ath_tx_desc *bf_desc;
+ struct ath_tx_desc *bf_descarr;
+ struct ath_tx_desc *bf_lastds;
struct ath_buf_state bf_state;
a_uint16_t bf_flags;
HTC_ENDPOINT_ID bf_endpt;
struct ath_rx_buf
{
ATH_GENERIC_BUF
+ asf_tailq_entry(ath_rx_buf) bf_list;
+ struct ath_rx_buf *bf_next;
+ struct ath_rx_desc *bf_desc;
+ struct ath_rx_desc *bf_descarr;
+ struct ath_rx_desc *bf_lastds;
a_uint32_t bf_status;
struct ath_rx_status bf_rx_status;
};
-#define ATH_BUF_GET_DESC_PHY_ADDR(bf) bf->bf_desc
+#define ATH_BUF_GET_DESC_PHY_ADDR(bf) (a_uint32_t)bf->bf_desc
#define ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, idx) (adf_os_dma_addr_t)(&bf->bf_descarr[idx])
#define ATH_BUF_SET_DESC_PHY_ADDR(bf, addr)
#define ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, idx, addr)
typedef asf_tailq_head(ath_deschead_s, ath_rx_desc) ath_deschead;
typedef asf_tailq_head(ath_bufhead_s, ath_buf) ath_bufhead;
+typedef asf_tailq_head(ath_rx_bufhead_s, ath_rx_buf) ath_rx_bufhead;
+typedef asf_tailq_head(ath_tx_bufhead_s, ath_tx_buf) ath_tx_bufhead;
#define WME_NUM_TID 8
#define WME_BA_BMP_SIZE 64
a_int32_t baw_tail;
a_uint32_t tx_buf_bitmap[ATH_TID_MAX_BUFS/TX_BUF_BITMAP_SIZE];
asf_tailq_entry(ath_atx_tid) tid_qelem;
- asf_tailq_head(ath_tid_rbq,ath_buf) buf_q;
+ asf_tailq_head(ath_tid_rbq,ath_tx_buf) buf_q;
a_int8_t paused;
a_int8_t sched;
a_uint8_t flag;
struct ath_txq {
a_uint32_t axq_qnum;
a_uint32_t *axq_link;
- asf_tailq_head(,ath_buf) axq_q;
+ asf_tailq_head(,ath_tx_buf) axq_q;
a_uint32_t axq_depth;
- struct ath_buf *axq_linkbuf;
+ struct ath_tx_buf *axq_linkbuf;
asf_tailq_head(,ath_atx_tid) axq_tidq;
};
struct ath_vap_target {
struct ieee80211vap_target av_vap;
struct ath_txq av_mcastq;
- struct ath_buf *av_bcbuf;
+ struct ath_tx_buf *av_bcbuf;
a_uint32_t av_rate_mask[2]; /* 0 - 2G, 1 - 5G */
a_uint8_t av_minrateidx[2]; /* 0 - 2G, 1 - 5G */
a_int8_t av_valid;
struct ath_ratectrl *sc_rc;
a_uint32_t sc_invalid : 1,
- sc_txstbcsupport : 1,
- sc_rxstbcsupport : 2,
sc_tx_draining : 1,
sc_enable_coex : 1;
tq_struct sc_txtotq;
tq_struct sc_fataltq;
- ath_bufhead sc_rxbuf;
+ ath_rx_bufhead sc_rxbuf;
ath_deschead sc_rxdesc_idle;
ath_deschead sc_rxdesc;
- struct ath_desc *sc_rxdesc_held;
+ struct ath_rx_desc *sc_rxdesc_held;
- struct ath_buf *sc_txbuf_held;
+ struct ath_tx_buf *sc_txbuf_held;
struct ath_descdma sc_rxdma;
struct ath_descdma sc_txdma;
struct ath_descdma sc_bdma;
a_uint32_t *sc_rxlink;
- ath_bufhead sc_txbuf;
+ ath_tx_bufhead sc_txbuf;
a_uint8_t sc_txqsetup;
struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
struct ath_vap_target sc_vap[TARGET_VAP_MAX];
struct ieee80211com_target sc_ic;
- ath_bufhead sc_bbuf;
+ ath_tx_bufhead sc_bbuf;
a_uint64_t sc_swba_tsf;
WMI_TXSTATUS_EVENT tx_status[2];
} owl_txq_state_t;
a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp);
-
-#define ath_hal_getratetable(_ah, _mode) \
- ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
-#define ath_hal_intrset(_ah, _mask) \
- ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
-#define ath_hal_intrpend(_ah) \
- ((*(_ah)->ah_isInterruptPending)((_ah)))
-#define ath_hal_getisr(_ah, _pmask) \
- ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
-#define ath_hal_updatetxtriglevel(_ah, _inc) \
- ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
-#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
- ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
-#define ath_hal_rxprocdescfast(_ah, _ds, _dspa, _dsnext, _rx_stats) \
- ((*(_ah)->ah_procRxDescFast)((_ah), (_ds), (_dspa), (_dsnext), (_rx_stats)))
-#define ath_hal_stoptxdma(_ah, _qnum) \
- ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
-#define ath_hal_aborttxdma(_ah) \
- ((*(_ah)->ah_abortTxDma)(_ah))
-#define ath_hal_set11n_txdesc(_ah, _ds, _pktlen, _type, _txpower,\
- _keyix, _keytype, _flags) \
- ((*(_ah)->ah_set11nTxDesc)(_ah, _ds, _pktlen, _type, _txpower, _keyix,\
- _keytype, _flags))
-#define ath_hal_set11n_ratescenario(_ah, _ds, _durupdate, _rtsctsrate, _rtsctsduration, \
- _series, _nseries, _flags) \
- ((*(_ah)->ah_set11nRateScenario)(_ah, _ds, _durupdate, _rtsctsrate, _rtsctsduration,\
- _series, _nseries, _flags))
-#define ath_hal_clr11n_aggr(_ah, _ds) \
- ((*(_ah)->ah_clr11nAggr)(_ah, _ds))
-#define ath_hal_set11n_burstduration(_ah, _ds, _burstduration) \
- ((*(_ah)->ah_set11nBurstDuration)(_ah, _ds, _burstduration))
-#define ath_hal_set11n_virtualmorefrag(_ah, _ds, _vmf) \
- ((*(_ah)->ah_set11nVirtualMoreFrag)(_ah, _ds, _vmf))
-#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
- _txr0, _txtr0, _keyix, _ant, _flags, \
- _rtsrate, _rtsdura, \
- _compicvlen, _compivlen, _comp) \
- ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
- (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
- (_flags), (_rtsrate), (_rtsdura), \
- (_compicvlen), (_compivlen), (_comp)))
-#define ath_hal_fillkeytxdesc(_ah, _ds, _keytype) \
- ((*(_ah)->ah_fillKeyTxDesc)((_ah), (_ds), (_keytype)))
-#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
- ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
-#define ath_hal_txprocdesc(_ah, _ds) \
- ((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
-#define ath_hal_putrxbuf(_ah, _bufaddr) \
- ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
-#define ath_hal_rxena(_ah) \
- ((*(_ah)->ah_enableReceive)((_ah)))
-#define ath_hal_stopdmarecv(_ah) \
- ((*(_ah)->ah_stopDmaReceive)((_ah)))
-#define ath_hal_stoppcurecv(_ah) \
- ((*(_ah)->ah_stopPcuReceive)((_ah)))
-#define ath_hal_htsupported(_ah) \
- (ath_hal_getcapability(_ah, HAL_CAP_HT, 0, NULL) == HAL_OK)
-#define ath_hal_rxstbcsupport(_ah, _rxstbc) \
- (ath_hal_getcapability(_ah, HAL_CAP_RX_STBC, 0, _rxstbc) == HAL_OK)
-#define ath_hal_txstbcsupport(_ah, _txstbc) \
- (ath_hal_getcapability(_ah, HAL_CAP_TX_STBC, 0, _txstbc) == HAL_OK)
-#define ath_hal_getrtsaggrlimit(_ah, _pv) \
- (ath_hal_getcapability(_ah, HAL_CAP_RTS_AGGR_LIMIT, 0, _pv) == HAL_OK)
-#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
- ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
- #define ath_hal_txstart(_ah, _q) \
- ((*(_ah)->ah_startTxDma)((_ah), (_q)))
-#define ath_hal_setrxfilter(_ah, _filter) \
- ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
-#define ath_hal_gettsf64(_ah) \
- ((*(_ah)->ah_getTsf64)((_ah)))
-#define ath_hal_intrset(_ah, _mask) \
- ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
-#define ath_hal_getcapability(_ah, _cap, _param, _result) \
- ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
-#define ath_hal_set11n_aggr_first(_ah, _ds, _aggrlen, _numdelims) \
- ((*(_ah)->ah_set11nAggrFirst)(_ah, _ds, _aggrlen, _numdelims))
-#define ath_hal_set11n_aggr_middle(_ah, _ds, _numdelims) \
- ((*(_ah)->ah_set11nAggrMiddle)(_ah, _ds, _numdelims))
-#define ath_hal_set11n_aggr_last(_ah, _ds) \
- ((*(_ah)->ah_set11nAggrLast)(_ah, _ds))
-#define ath_hal_numtxpending(_ah, _q) \
- ((*(_ah)->ah_numTxPending)((_ah), (_q)))
+void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an,
+ ath_atx_tid_t *tid, a_uint8_t discard_all);
+void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
+void ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
+void ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid);
+void ath_tx_status_clear(struct ath_softc_tgt *sc);
+
+void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
+ void *buffer, a_int32_t Length);
#endif /* _DEV_ATH_ATHVAR_H */
projects / open-ath9k-htc-firmware.git / blobdiff